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C Interview Questions
o Question 25. What Is The Difference Between Program Block And
Module ?
Answer :
Program block is newly added in SystemVerilog. It serves these purposes
o It separates testbench from DUT
o It helps in ensuring that testbench doesn't have any race condition
with DUT
o It provides an entry point for execution of testbench
o It provides syntactic context (via program ... endprogram) that
specifies scheduling in the Reactive Region.
Having said this the major difference between module and program blocks are
o Program blocks can't have always block inside them, modules can
have.
o Program blocks can't contain UDP, modules, or other instance of
program block inside them. Modules don't have any such restrictions.
o Inside a program block, program variable can only be assigned using
blocking assignment and non-program variables can only be assigned
using non-blocking assignments. No such restrictions on module
o Program blocks get executed in the re-active region of scheduling
queue, module blocks get executed in the active region
o A program can call a task or function in modules or other programs.
But a module can not call a task or function in a program.
o Question 26. What Is The Use Of Modports ?
Answer :
Modports are part of Interface. Modports are used for specifing the direction of
the signals with respect to various modules the interface connects to.
o ...
o interface my_intf;
o wire x, y, z;
o modport master (input x, y, output z);
o modport slave (output x, y, input z);