Designed By M.

Asefi
Synchronization with external clock to avoid glitch Noise Discriminator
Monostable chip
External clock from a PLL on Controller
S
C
D
R
S
C
D
R
A
B
C
D
1 2 3 4 5 6
A
B
C
D
1 2 3 4 5 6
13 12
Q
1
A1
3
A2
4
B
5
Q
6
R
9
C
10
R/C
11
IC2
1
2
3
IC4A
4
5
6
IC4B 3
4
5
1
2
6
V1/1
1
2
3
SV1
13 12
Q
1
A1
3
A2
4
B
5
Q
6
R
9
C
10
R/C
11
IC5 3
4
5
1
2
6
V2/1
PWM_MICRO
CLK
74121N
74ALS08N
74ALS08N
7474N
V
C
C
V
C
C
74121N
7474N
V
C
C
Positive Edge Snap Shot
Negative Edge Snap Shot
Positive Edge Snap Shot
Negative Edge Snap Shot
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
A
B
C
D
1 2 3 4 5 6
A
B
C
D
1 2 3 4 5 6
3
4
5
1
2
6
V3/1 11
10
9
13
12
8
V3/2
1
2
3
IC7A
4
5
6
IC7B
9
10
8
IC7C
12
13
11
IC7D
A
1
B
2
QA
3
QB
4
QC
5
QD
6
CLK
8
CLR
9
QE
10
QF
11
QG
12
QH
13
IC6
A
1
B
2
QA
3
QB
4
QC
5
QD
6
CLK
8
CLR
9
QE
10
QF
11
QG
12
QH
13
IC8
3
4
5
1
2
6
V4/1
11
10
9
13
12
8
V4/2
3
4
5
1
2
6
V5/1 11
10
9
13
12
8
V5/2
A
1
B
2
QA
3
QB
4
QC
5
QD
6
CLK
8
CLR
9
QE
10
QF
11
QG
12
QH
13
IC10
A
1
B
2
QA
3
QB
4
QC
5
QD
6
CLK
8
CLR
9
QE
10
QF
11
QG
12
QH
13
IC11
CLK
CLK
RESET
RESET
7474N
7474N
74ALS08N
74ALS08N
74ALS08N
74ALS08N
74LS164N
74LS164N
7474N
7474N
V
C
C
7474N
7474N
74LS164N
74LS164N
V
C
C