CONVERSION

FROM
BOOLEAN LOGIC TO LAYOUT DESIGN
Process Flow
Boolean Expression
Gate Level Logic
Transistor Level Logic
Stick Diagram
Layout Diagram
Implementation with NOT gate
Boolean Expression
Gate Level Logic
Converting into transistor level
Step 1:
Identify the parts of the logic-level schematic; input, output,
internal nodes, logic symbols.
input A
ouput out
Contd..
Step 2:
Identify the inverted logic function.
Step 3:
Identify the transistor level logic.
NOT gate in transistor level
Stick diagram
A stick diagram is a cartoon of layout
material color Representation
Polysilicon RED
P-diff YELLOW
N-diff GREEN
Metal1 BLUE
Metal2 Light Blue
Formation of PMOS & NMOS
NMOS PMOS
Inverter Stick diagram
Transistor level Stick diagram
Steps for Layout Design
MOS layers (color) representation
n-diffusion
p-diffusion
Poly
Metal1
Metal2
MOS layers (Monochrome) representation
n-diffusion
p-diffusion
Poly
Metal1
Metal2
Layout Design Specifications
Polysilicon
Minimum Width - 2
Minimum Spacing - 2
Poly Diff Spacing - 1
2
2
Contd..
Diffusion
Minimum Width - 3
Minimum Spacing(same-type) - 2
Minimum Spacing(diff-type) - 10
Metal
Minimum Width - 3
Minimum Space (metal1-metal1) - 3
Minimum Space (metal2-metal2) - 4
Contact cuts and vias
Contacts and vias provide Electrical connections between
different material layers
Contact cuts:
Contacts are necessary connections to access the
various regions of silicon
Vias:
Vias are used between two interconnect layers to simplify
the layout
Metal 1 /Diffusion
Metal 1 / Polysilicon
Metal 1 / Metal 2
Formation of NMOS & PMOS:
NMOS PMOS
2
3
2
3
Layout of CMOS inverter
How to Draw
The Transistor Level for a Boolean
Expression ?
Consider the figure shown
below
Out= (A+B)+(CD)
Conversion steps:
Step 1:
Identify parts of the logic level schematic.
They are inputs, outputs, internal logic.
Inputs A,B,C,D
Outputs OUT
Contd..
Step 2:
Draw the box around the logic
which is connected to output and treat that as
parent.
Contd..
Step 3: Identify the inputs
to the parent. Draw the
box around the each of the
logic symbols.
Contd..
Step 4:
Begin the transistor level schematic.
Draw the horizontal line and label the node as OUT.
Step 5:
Determine the logic function of the n-type transistors of
the parent as they determine the logic function of the logic
symbol.
Contd..
Step 6:
Implement the n-type logic, in this example it is
NAND and they are in series.
Contd
Step 7:
Box 1 :
OR Function transistors
are in parallel
Box 2 :
AND Function transistors
are in series
Contd..
Step 8:
Draw the transistors for
p-type which is reverse of
the n type logic.
Box 1:
AND functions are in
series.
Box 2:
OR functions are in
parallel.
Contd..
Step 9:
Final Transistor level
diagram is shown.
Significance of DOT convention
Dot drawn on the logic gate indicates how the series
transistors are drawn.
Dot indicates which series transistor is closest to output
node.
The placement of dot is determined by design engineer for
the timing analysis.
Example(NAND Gate):
Gate level Transistor Level
Consider the NAND gate
with the DOT convention
at the a input.
Contd..
NOR gate Transistor level
Drawing Stick Diagrams is truly fun!!!
Enjoy it!!!!