1

Lp trnh h thng nhng

s dng vi iu khin MSP430
(Embedded System I)
Ts. L Mnh Hi
Khoa CNTT,
H Cng ngh TP HCM
11/2013
2
M au
I Mc ch mn hc:
Cung cp kin thc v lp trnh vi iu khin TI MSP430.
II. Thi gian:
30 tit l thuyt (2 tn ch) + 30 tit thc hnh (1 tn ch)
III Gio trnh v ti liu tham kho
MSP430 Microcontroller Basics. John H. Davies. Elsevier.
2008 (685 trang)
Embedded Systems Design using the TI MSP430 Series.
Chris Nagy. Elsevier. 2003 (296trang)
Introduction to Embedded Systems - A Cyber-Physical
Systems Approach, E. A. Lee and S. A. Seshia.
http://LeeSeshia.org. 2011
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4
IV. nh gi:
Thi kt thc mn: Bi t lun vi 3 cu hi.
V. Gio vin:
Ts. L Mnh Hi. Tel: 0985399000.
Khng gi in thoi hi hay xin im,
email: hailemanh@yahoo.com,
lm.hai@hutech.edu.vn
Website: giangvien.hutech.edu.vn
GV thc hnh: Nguyn Ngc c.
0978629557
5
Ni dung chi tit
Chng 1: Cc h thng nhng v vi iu khin
MSP430
Chng 2: Pht trin ng dng nhng.
Chng 3: Cc hm v ngt
Chng 4: Nhp/xut
Chng 5: B nh thi
Chng 6: ADC
Chng 7: Kt ni
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Chng 1: Cc h thng nhng v
vi iu khin MSP430
Sau khi hc bi ny, sinh vin s nm c
1. H thng nhng l g?
2. Cc hng pht trin h thng nhng
3. Cu trc in hnh mt vi iu khin
4. Cu trc vi iu khin MSP430G2553
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H thng nhng l g?
Theo vi.wikipedia.org: H thng nhng (Embedded
system) l mt thut ng ch mt h thng c kh
nng t tr (my tnh) c nhng vo trong mt
mi trng hay mt h thng m.
l cc h thng tch hp c phn cng v phn
mm phc v cc bi ton chuyn dng trong nhiu
lnh vc cng nghip, t ng ho iu khin, quan
trc v truyn tin. c im ca cc h thng nhng
l hot ng n nh v c tnh nng t ng ho
cao.
8
H thng nhng l g?
My git
Xe hi i mi c trn 100 b x l
Khong 99% chp tnh ton c ng dng trong
cc h thng nhng
9
10
in thoi di ng thng minh (smartphone)
TV

11
Bo Launchpad MSP430
MSP-EXP430G2 LaunchPad Experimenter Board
MSP430G2543
MSP430G2553
IAR Kickstart or
Code Composer
Studio Ver 5 (CCS)
12
Cc hng pht trin h thng nhng
Mt h thng iu khin tng t (trc nm
1970)
H thng my tnh s: Vi x l v vi iu khin
(1970 nay)
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Mch s tch hp thp: transitor, IC 555
Mch s tch hp trung bnh : CMOS 4000
Mch s tch hp cao: Vi iu khin
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Cc hng ng dng
Application-specific integrated circuits (ASICs)
Chp (IC) thit k dnh ring cho mt ng dng
Field-programmable gate arrays (FPGAs) and
programmable logic devices (PLDs)
Chp thit k c th lp trnh thay i cu to
chc nng bng cch to cc mi lin kt gia
cc cng bn trong chp. C hng triu cng
trong mt chp.
Microcontrollers
C mt s khi rt hay c s dng cng vi
mt khi x l trung tm (CPU) .
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Vi iu khin nh
CPU x l 8 hoc 16 bt
B nh 64 KB
Tc ti a : 16Mhz
Chc nng chnh: iu
khin, khng phi tnh
ton!
http://www.diendanti.com
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Cu trc chung ca vi iu khin
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Vi iu khin c 6 thnh phn c bn sau:
1. Khi x l trung tm (CPU) bao gm:
Khi tnh ton s hc/logic(ALU).
Khi gii m lnh v cc mch h tr x l
ngt, ti khi ng
Cc thanh ghi bao gm thanh ghi m chng
trnh PC, con tr ngn xp SP, thang ghi trng
thi (SR), thanh ghi to hng s CG v 12 thanh
ghi a nng
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2. B nh chng trnh: L b nh khng mt d
liu khi mt in. Trc kia l ROM, nay s dng
FLASH. Chp MSP430G2553 ch c 16KB
3. B nh d liu: RAM truy xut ty nhng d
liu b xa khi mt in
Hin c b nh d liu khng b xa khi mt
in
4. Cc cng nhp/xut: Kt ni vi cc h thng
khc
5. ng BUS d liu v BUS a ch: truyn
d liu v lnh gia cc khi.
6. Khi xung nhp: To xung ng b cc khi
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08 khi thng gp khc:
Khi nh thi (Timer): m thi gian chnh xc. Cc vi iu
khin hin nay c t nht 2 khi ny.
Khi nh thi cnh bo: L khi kim sot li chng trnh
theo thi gian. Khi ny s ti khi ng chp khi chng
trnh b li .
Khi giao tip tun t: Kt ni vi cc IC khc bng cch
truyn tng bt.
Khi nh d liu khng bay hi: Lu tr d liu ngay c khi
mt in. Thng dng lu cu hnh thit b nh a ch IP
trong cc ADSL router
Khi bin i tng t - s : Cho php chuyn i tn hiu
tng t sang dng s.
Khi bin i s -tng t : Cho php chuyn i tn hiu
tng t sang dng s, thng dng iu khin ng c
bng phng php xung s (PWM).
ng h thi gian thc: Lu gi gi tr nm thng ngy.
B np v chy chng trnh: Cho php np chng trnh t
my tnh vo b nh chng trnh
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Cu trc Harvard v von Neumann
MSP 430 c cu trc von Neumann
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Cu hi
Hy k tn mt vi thit b dn dng l h
thng nhng?
Cc thnh phn c bn ca mt vi iu
khin?
Cc khi h tr thng gp mt VK?
S khc bit gia cu trc Harvard v von
Neumann ?
22
Bi 2: Cu trc vi iu khin
MSP430G2553
Cc chn VK MSP430G2553
Cc khi chc nng
T chc b nh
Khi x l trung tm (CPU)
B to xung nhp
Ngt v ti khi ng
Cc ti liu chnh thng
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Cc chn VK MSP430G2553
Chn ra: 20 chn t v nha PDIP
Phn ln cc chn c nhiu chc nng.
V d chn s 3 c 5 chc nng
Cc ng dng ti mi thi im ch yu cu
mi chn thc hin mt chc nng =>
khng b mu thun
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M t cc chn
VCC( chn 1) VSS (chn 20) dng cp ngun
3,3V cho chp. Ngun c th dao ng trong
khong 1,8V 3,6 V
P1.0P1.7, P2.0, and P2.7 l 2 cng nhp xut s.
Mi cng 8 chn (8 bt), gi tt l P1 v P2.
Cc khi chc nng cng s dng cc chn ny
khi cn nh cu hnh thanh ghi chn khi P1SEL
v P2SEL.
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Cc khi chc nng MSP430G2553
M t cc khi chc nng
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Cc khi c bn: CPU, Xung nhp, Flash, RAM,
Ports,v Bus.
Cc khi b xung:
Khi np chng trnh: JTAG : 4 dy v 2 dy
Khi bin i tng t - s ADC.
Khi bo v st p (Brownout Protection)
Khi so snh p (Compare A+)
Khi ng h canh gc (WDT)
2 khi nh thi loi A (Timer0_A3 v Timer_A3)
2 khi giao tip tun t (USCI A0 v USCI B0)
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B nh
B nh l cc thanh ghi 8 bt, t chc thnh
cc nh,
a ch nh 16 bit t 0x0000 ti 0xFFFF
Bus d liu 16 bit c th truyn 16 bt hoc
8 bt.
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Bus a ch v cc nh
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Th t nh
Little-endian ordering: Khi d liu c trn
1 byte th byte gi tr thp nm v tr di,
byte gi tr cao nm bn trn trong b
nh. Dng MSP430 c th t ny.
Big-endian ordering: Byte gi tr thp nm
v tr cao. Mt s chp ca Motorola,
Freescale HCS08 c cu trc ny.
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T chc b nh
T chc b nh ca MSP430G2553 gmcc thnh phn sau
Thanh ghi chc nng chuyn dng: Cc thanh ghi ca cc
khi c chc nng xc nh trc. V d cc thanh ghi PC, SP,
SR, CG ca CPU, thanh ghi P1REN, P1DIR ca P1...
Cc thanh ghi a nng ca CPU v cc thit b ngoi vi, nh
cc thanh ghi R4-R15 ca CPU, P1IN, P1OUT ca P1.
Cc thanh ghi 8 bt
Cc thanh ghi 16 bt
Random access memory (RAM): Cc thanh ghi t trong
khi RAM c a ch t 0x0200 v ch c 256/512 Bytes
Bootstrap loader : L phn b nh khng b xa cha chng
trnh kt ni my tnh qua cng COM ca TI
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B nh d liu khng bay hi (Information
memory): L 256 Byte flash, cho php lu cc
thng tin quan trng v khng b mt khi mt in.
B nh chng trnh (Code memory): L b nh
ch c (ROM) v cha chng trnh c np t
my tnh xung. Sau khi np v khi ng, chng
trnh ny s c c vo CPU thc thi . Chp
hin nay c t 2KB-16KB.
Interrupt and reset vectors: L phn b nh cha
cc a ch ca cc hm x l ngt v ti khi ng.
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Khi x l trung tm (CPU)
Chc nng: Khi CPU thc thi cc lnh ct trong
b nh chng trnh. Cc lnh c c tun t v
thc thi nu khng gp cc lnh r nhnh hoc x
l ngt
Cu to: Gm mt khi tnh ton ALU 16 bt,
mch gii m lnh v 16 thanh ghi.
Tn s ti a (cng l tc ) do xung nhp
MCLK to l 16MHz.

CPU
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Cc thanh ghi ca CPU
Thanh ghi m chng trnh (Program counter PC): Cha
a ch lnh k tip cn thc hin. PC t ng tng 2 sau mi
xung nhp, ngoi tr c lnh r nhnh hoc gi hm
Con tr ngn xp (Stack pointer- SP): Tr n vng nh
RAM dng lm ngn xp. Khi mt hm c gi, PC v SR
c ct vo ngn xp v khi thc hin xong hm, cc gi tr
ny c tr li PC v SR tip tc oc6ng vic ang thc hin
d
Thanh ghi trng thi (Status register SR): Cha cc c trang
thi. Cc bt trng thi hay c dng l C, Z, N, v V. Ngoi
ra c mt s bt tt xung nhp nh CPUOFF (tt MCLK)
Thanh ghi hng s (Constant generator) Dng to ra mt s
hng s thng gp
12 thanh ghi a nng : l cc thanh ghi dng lu thng tin
trung gian. Cc thanh ghi c tc tru cp tng ng CPU
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B to xung nhp
Xung nhp l thit b khng th thiu ca cc h thng s
Linh kin thng dng to xung nhp l thch anh c th
to dao ng khong vi MHz cho chp (max = 16MHz)
Tuy nhin khi chy tc cao, chp tiu tn nhiu in. Cc
h thng di ng cn tit kim pin nn mt s b phn ch
chy tn s thp s tit kim v tng thi gian s dng pin.
B to xung nhp cn a dng ha cc ch hot ng ca
VK.
Nhiu ng dng nhng phn ln thi gian trng thi ng
(cng sut thp)-> Cn tt xung nhp khi c th. Khi c s
kin ngt, CPU s c cp xung ng b li hot ng.
.
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B to xung nhp
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B to xung thp tn bng thch anh LFXT1: C th to
cc xung nhp t vi chc KHz ti 1 MHz vi chnh xc
cao.
B to xung cao tn bng thch anh- XT2: Ging LFXT1
ngoi tr tn s cao hn (8-16MHz)
B to xung tn s thp VLO vi chnh xc thp. Cc
VK c th to xung nhp tn s thp m khng cn thch
anh. Dng VLO nu cn tit kim nng lng (ko di thi
gian s dng gia hai ln sc pin)
B to xung iu khin k thut s (DCO): To cc xung
nhp tn s cao (8-10MHz) m khng dng thch anh. Cc
VK s dng DCO trong giai on u khi khi ng
(khong 1 giy) .
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Kim sot cc xung nhp thng qua thanh ghi
trng thi (SR)
CPUOFF kha MCLK, v dng CPU cng nh
cc khi no dng MCLK ng b
SCG1 kha SMCLK v cc khi dng MCLK
ng b
SCG0 kha DCO
OSCOFF kha VLO v LFXT1.
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Cc loi xung nhp
Master clock, MCLK, s dng cho CPU
v mt s khi tc cao (1-16MHz).
Subsystem master clock, SMCLK, dng
cho cc cc khi tc trung bnh (1MHz)
Auxiliary clock, ACLK, Dng cho cc
khi tc thp (32KHz).
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Khi nim Ngt v ti khi ng
Ngt (Interrupts): L mt s kin gy bi phn cng , mc
d c ci t bng phn mm) v thng cn c x l
ngay lp tc. Khi xy ra mt ngt, VK dng chng trnh
ang thc thi, ct cc thng tin/ trang thi hin ti (PC, SR)
chuyn sang chng trnh x l ngt (ISR) ngay lp tc.
Sau khi x l ngt xong, VK quay li thc hin tip cng
vic ang thc hin trc. Nh vy chng trnh x l ngt
c gi bi phn cng ch khng phi phn mm.
Ti khi ng (Resets): c to bi phn cng, thng
c dng khi c s kin bt thng ngu hi khin VK
khng th tip tc cng vic. Thng thng ng h canh gc
s ti khi ng VK sau mt khong thi gian nht nh
nu khng c can thip kp thi. Ti khi ng gip h
thng vo trng thi n nh
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Cu hi
Lit k cc thanh ghi CPU
Cc ngun xung v cc loi xung ca VK TI
MSP430G2553?
Ngt l g, ti sao h thng nhng cn c ch
ngt?
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Bi tip
Mi trng pht trin ng dng
Chng trnh n gin u tin
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Bi 3: Mi trng pht trin ng
ng dng
Sau khi hc xong SV cn nm c:
1. Cc cng c h tr pht trin ng dng
2. Ngn ng lp trnh nhng C
3. Truy cp v g ri
4. Bo Launchpad MSP430 v cc chng
trnh bt tt n LED
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Cc cng c pht trin ng dng
B son CT (Editor): Cho php vit CT v kim tra c php
tc th
Bin dch (compiler): Chng trnh chuyn m C sang m
my, c kh nng d li
Gn a ch (Linker): Phi hp cc th vin v cc hm, gn
a ch b nh ( khi np vo VK khng b nhm)
B m phng (Stand-alone simulator): Chng trnh
phng to hot ng ca VK, thay cho chp tht.
Embedded emulator/debugger: Thit b cho php np tng
lnh t my tnh xung VK g ri
B np trc tip (In-circuit emulator): Thit b g ri cho
php VK chay tng lnh t trn my tnh. Gi khong
1000$
Chng trnh np (Flash programmer): L phn mm
min ph ca TI dng np chng trnh t my tnh vo b
nh chng trnh ca VK.
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Cc phn mm thng dng
IAR EmbeddedWorkbench. Phn mm min ph
cho SV.
http://www.iar.com
Code Composer Studio
Phn mm min ph cho SV : 16KB chng trnh
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The C Programming Language
if ((P1IN & BIT3) == 0) // Kim tra chn s 3 Port1 c bng 0?
{
P1OUT = 0x01; //cp ra port 1 gi tr 0b00000001
}
else
{
P1OUT = 0x00; //cp ra port 1 gi tr 0b00000000
}
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Hp ng
V d:
mov.w #WDTPW|WDTHOLD ,& WDTCTL
Sinh vin s hc lp trnh hp ng nu
thnh tho lp trnh bng C
51
Bo thc hnh
The TI MSP430G2553 Launchpad Board.
Mch np
VK
2 LED
Cng
tc S2
Cng tc
S1
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Cc chng trnh m u
Bt /tt cc n LED
c trng thi cng tc S2
T ng bt tt n dng hm gi chm
Automatic Control: Use of Subroutines
Automatic Control: Flashing a Light by Polling
Timer_A
Header Files and Issues Brushed under the
Carpet
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Bt tt cc n LED
#include <msp430g2553.h> // Specific device
void main (void)
{
WDTCTL = WDTPW | WDTHOLD; // dng watchdog timer
P1DIR = 0x41; // t cc chn P1.0 v P1.6 l OUTPUT:0b01000001
P1OUT = 0x41; // c hai led cng sng
for (;;) { // Loop forever ...
} // ... doing nothing
}
Hy sa li chuong trnh Led 1 sng , led 2 tt
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c trng thi cng tc
Nu cng tc S2 h (m) in p chn P1.3 s ln 1 (3,3v )
Nu cng tc S2 ng : in p trn P1.3 s xung 0 (0v)
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#include <msp430g2553.h> // Specific device
#define LED1 BIT0
#define LED2 BIT6
#define S2 BIT3
void main (void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P1DIR = LED1|LED2; // Set pin with LED1 and LED2 to output
P1OUT = LED1|LED2; // bat LED1 va LED2 sang
P1REN |= S2; //su dung dien tro keo len/xuong, chi dung voi Launchpad v1.5
P1OUT |= S2; //dien tro keo len, sau lenh nay, S2 thuong xuyen cao (1)
while(1) { // Loop forever
if ((P1IN & S2) == 0)
P1OUT |= LED1; // Yes: bat LED1
else
P1OUT &= ~ LED1; // No: tt LED1, LED2 khng thay doi
}
}
Hy vit CT bt tt LED2 bng cng tc S2. LED1 khng thay i
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Chp n bng hm Delay()
Chng trnh tip theo s chp n LED1
(sng/tt) vi chu k 1 giy. Nh vy thi
gian sng/tt l 0,5 s
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while(1){ // Loop forever
for (LoopCtr = 0; LoopCtr < DELAYLOOPS; ++ LoopCtr) {
} // Empty delay loop
P1OUT = LED1|LED2; // Toggle LEDs
}
}
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T ng chp n: S dng
timerA
S dng vng lp l gii php n gin
nhng khng chnh xc: khi xy ra mt s
kin ngt, vng lp s b ko di.
on chng trnh sau s bt tt n theo
timer.
Timer s c trnh by phn sau
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TimerA
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#include "msp430g2553.h" //2542
#define S2 BIT3
void main(void) {
WDTCTL = WDTPW |WDTHOLD;
P1DIR = BIT0|BIT6;
P1OUT = 0x00;
CCTL0 = CCIE; // CCR0 interrupt enabled
CCR0 = 30000;
TACTL = TASSEL_2 + MC_2 + ID_2; // SMCLK, upmode
_BIS_SR( GIE); // Enter LPM0 w/ interrupt
while(1){}
}
#pragma vector=TIMER0_A0_VECTOR
__interrupt void Timer_A (void)
{
P1OUT ^=BIT0 | BIT6;
CCR0 += 30000;
}
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Quizzes
Cc phng php chp mt n LED?
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Chng tip theo
Hm, ngt v cc ch tit kim nng
lng
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Bi 4: Hm, ngt v ch tit kim
nng lng
1. Hm v cc bc thc thi khi gi hm
2. Ngt v chng trnh phc v ngt
3. Cc bc thc thi khi xy ra mt ngt
4. Cc ch tit kim nng lng
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Hm
Hm l cch vit chng trnh thnh cc m un
nh. Vic to chng trnh t cc m un khin
chng trnh tr nn r rng, d vit, d kim th v
c th dng nhiu ln
Mt khi hm c vit, c th ng gi thnh th
vin s dng khi cn (th vin ng)
Cc chng trnh nhng vit bng ngn ng c
thng c cc hm di khng qu 30 dng lnh
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Cc bc thc thi khi gi hm
Cc thng tin ca chng trnh ang thc thi c
ct vo ngn xp
a ch ca chng trnh mi c lu vo PC.
Chng trnh mi c thc hin cho ti khi gp
lnh return.
Cc thng tin ca chng trnh c c np li t
ngn xp. a ch lnh chng trnh c cn tip
tc thc hin c np vo PC v CPU s tip tc
chng trnh c
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Ngt
Ngt l c ch dng mt chng trnh ang chy
thc hin mt chng trnh khc khi xy ra mt s
kin do phn cng gy ra.
Ngt c dng khi
Mt s kin khn cp cn c p ng tc thi.
Cc s kin rt chm.
Chuyn CPU t ch ng sang tch cc.
Gi h iu hnh
69
Chng trnh phc v ngt
on chng trnh c gi khi xy ra mt ngt gi
l Chng trnh phc v ngt ( interrupt service
routine - ISR).
Chng trnh x l ngt ging mt hm, ngoi tr:
N c gi bt k khi no xy ra s kin gy ra
ngt, v s kin ny thng khng bit trc thi
im.
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C ngt
Mi ngt c mt c ngt ring, ch th rng c
s kin cn x l gp. Chng hn Timer A c c
ngt TAIFG C TAIFG s t ng bt ln khi TAR
v 0. Khi c ngt bt ln, chng trnh x l ngt
tng ng s c gi, tr trng hp b che.
Chng trnh x l mt ngt ch c thc thi khi
ngt ny khng b che bi bit GIE cho php ngt
ton cc. Chng trnh chnh phi bt bt GIE (thuc
thanh ghi SR) c ch ngt c php thc hin

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Vector ngt
Vector ngt l vng nh cao trong b nh MSP430.
Vng ny cha cc a ch ca cc ISR. Khi GIE cao
v mt c ngt bt ln, a ch ca ISR tng ng s
c np t IV vo PC.
Mi ngt c mt th t u tin. Nu 2 ngt xy ra
ng thi, th ngt c u tin cao hn s c thc
thi. Th t u tin cao cao th v tr ISR trong IV cng
cao.
72
Cc bc thc thi khi mt ISR c gi
1. Nu CPU ang thc hin mt lnh Lnh cn c hon tt.
Nu CPU ang ng, xung MCLK c cp a CPU v ch
tch cc.
2. Ct PC vo ngn xp.
3. Ct SR vo ngn xp.
4. Chn IRS c u tin cao nht
5. Xa c ngt ca ISR c chn.
6. Xa SR.
7. t a ch ca ISR t IV vo PC.
73
chm
chm l thi gian t lc xy ra s kin
ti khi chng trnh x l ngt c bt
u.
Trong trng hp CPU ang thc hin d 1
lnh, th CPU s cn mt nhp hon tt v
su nhp thc hin su bc cn li trc
khi bt u ISR.
74
Khai bo ISR
Interrupt Service Routines in C
#pragma vector = TIMERA0_VECTOR
__interrupt void TA0_ISR (void)
75
void main (void)
{
WDTCTL = WDTPW|WDTHOLD; // Stop watchdog timer
P2OUT = LED1; // Preload LED1 on , LED2 off
P2DIR = LED1|LED2; // Set pins with LED1 ,2 to output
TACCR0 = 49999; // Upper limit of count for TAR
TACCTL0 = CCIE; // Enable interrupts on Compare 0
TACTL = MC_1|ID_3|TASSEL_2|TACLR; // Set up and start Timer A
// "Up to CCR0" mode , divide clock by 8, clock from SMCLK , clear timer
__enable _interrupt (); // Enable interrupts (intrinsic)
for (;;) { // Loop forever doing nothing
} // Interrupts do the work
}
// ----------------------------------------------------------------------
// Interrupt service routine for Timer A channel 0
#pragma vector = TIMERA0_VECTOR
__interrupt void TA0_ISR (void)
{
P2OUT = LED1|LED2; // Toggle LEDs
}
76
Ngt khng che
C mt s ngt m c GIE khng che c
l
Li b to dao ng OFIFG.
Tranh chp b nh ACCVIFG.
Chn RST b a xung thp
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Ch cng sut thp
C 1 ch tch cc v 5 ch cng sut thp
Ch tch cc: CPU v mi xung nhp, mi khi u hot ng. Dng
tiu th I 300uA. C th gim dng tiu th nu gim p ngun nui
xung 1,8V, tn s DCO =1Mhz, dng tiu th cn khong I 200uA.
LPM0: CPU v MCLK b kha. SMCLK v ACLK hot ng, dng
tiu th I 85uA.
LPM3: CPU, MCLK, SMCLK, v DCO b kha ch cng ACLK hot
ng, I 1uA.
LPM4: CPU v mi xung nhp b kha. CPU s ch tnh li khi c ngt bn
ngoi. I 0.1uA.
V d lp trnh C
_lowpower_mode_3 ();
78
Quizzes
V sao Ngt li quan trng vi HTN?
C ngt lm g?
Bt GIE l g?
79
Bi sau?
Cng nhp xut s
80
Bi 5: Cng nhp xut s
1. Cu trc cng nhp xut s (IO Port)
2. Cc thanh ghi ca IO
3. Chng di
4. Ma trn bn phm
5. Li LED v LED 7 on
6. LCD
81
82
Cng nhp xut s
Nhp xut thng dng nht l cc tn
hiu s vi 2 gi tr 0/1(0/3,3,V)
Chng trnh v d s dng PORT 1
li LED
.
83
Cng nhp xut s
Cc chp MSP430 c th c t 10-80 chn IO s.
Mc d l chn nhp xut s, cc chn cn c dng
cho cc khi khc nh Timer, ADC Khi ti khi
ng cc chn u l IO s
Chng hn chn P1.0 cn c dng lm TACLK
84
85
Cc thanh ghi ca P1
Cc Port u c cc thanh ghi ca ring mnh
Port P1 input, P1IN: nhn d liu logic (0/1) t
cc chn ca P1 (8 bt)
Port P1 output, P1OUT: Ghi d liu ra cc chn
ca P1
86
Cc thanh ghi ca P1
Port P1 direction, P1DIR: xc nh hng truyn d liu. Nu
bt i =0, chn P1.i s l INPUT, nu bt i=1, chn P1.i s l
OUTPUT . Khi khi ng cc bt P1DIR c gi tr 0
Port P1 resistor enable, P1REN: Bt mt bt ca thanh ghi ny
ln 1 s kich hot in tr ko ln hoc ko xung ti chn tng
ng.
Port P1 selection, P1SEL: Chn chn tng ng l chn nhp
xut s (0 gi th mc nhin khi khi ng) hoc c chc nng
khc (1).
87
Digital Input and Output
Port P1 interrupt enable, P1IE: Cho php ngt trn chn tng
ng nu bt ln 1, cm ngt nu bt tng ng l 0
Port P1 interrupt edge select, P1IES: chn cnh ln to ngt
nu bt tng ng l 0, hoc cnh xung nu l 1. Thanh ghi ny
ch c hiu lc nu thanh ghi P1IE bt
Port P1 interrupt flag, P1IFG: L thanh ghi cha cc c ngt .
Khi mt chn c bt cho php ngt v c s thay i tn hiu
ng nh thanh ghi P1IES t th c ngt tu7ong ng chn ny
bt ln. Nu GIE bt th ISR s c thc thi
88
Qut ma trn bn phm
Khi s nt nhn kh ln, s chn chp dng
iu kin cc cng tc s ln.
C th gim s chn VDK bn ma trn bn
phm
89
90
Qut bn phm
1. Cp 011 cho X1X2X3 c Y1Y2Y3Y4 kim
tra cc nt 1, 4, 7, or *. Cc nt khc s khng
lm thay i Y1-Y4 v X2,X3 c gi tr 1
2. Cp 101 cho X1X2X3 c Y1Y2Y3Y4 kim
tra cc nt 2, 5, 8, or 0.
3. Cp 110 cho X1X2X3 c Y1Y2Y3Y4 kim
tra cc nt 3, 6, 9, or #.
91
LED 7 on
92
Bi tip theo
1. Cc loi Timer thng gp
2. Watchdog Timer
3. Timer A
93
Bi 6: B nh thi
1. Cc loi timer
2. Watchdog timer
3. Timer A
94
95
Cc loi B nh thi
Watchdog timer: ng h canh gc : c trong mi thit b dng
MSP430. Chc nng chnh l chng li chng trinh nhng c th s
dng nh mt b m thi gian chnh xc
.
Timer_A: C trong mi thit b. Loi Timer A c 3 knh v l thit
b nh thi n gin nht. Timer Ac th m thi gian, o tn s
hoc m cc s kin lp
Timer_B: Ch c trong mt s chp ln. y l cu trc m rng ca
Timer A vi s knh ln n 7 , c s dng to cc xung PWM
iu khin ng c
Timer Basic1: Ch c trong mt s chp MSP430F4XX.
Real time clock: Ch c trong mt s chp MSP430 ln
96
Watchdog Timer (WDT)
Chc nng chnh: chng li chng trnh nh lp
qun, treo VK
WDT c mt thanh ghi m ln WDTCNT v khi t
gii hn trn (65535) n s khi ng li VK.
Chng trnh c vit phi nh k xa thanh ghi
m ln ca WDT trc khi t gii hn. Nu khng
h thng s b reset.
Tuy nhin hot ng ca WDT c cu hnh bi
thanh ghi iu khin 16-bit WDTCTL. Bt bt
WDTHOLT s ngng hot ng ca WDT
97
WDT lun s dng xung nhp DCO 1MHz. Khi hot ng,
bt WDTCNTCL bt ln 1 s xa thanh ghi WDTCNT
98
// Watchdog config: active , ACLK /32768 -> 1s interval; clear counter
#define WDTCONFIG (WDTCNTCL|WDTSSEL)
// Include settings for _RST/NMI pin here as well
// ----------------------------------------------------------------------
void main (void)
{
WDTCTL = WDTPW | WDTCONFIG; // Configure and clear watchdog
P2DIR = BIT3 | BIT4; // Set pins with LEDs to output
P2OUT = BIT3 | BIT4; // LEDs off (active low)
for (;;) { // Loop forever
LED2 = IFG1_bit.WDTIFG; // LED2 shows state of WDTIFG
if (B1 == 1) { // Button up
LED1 = 1; // LED1 off
} else { // Button down
WDTCTL = WDTPW | WDTCONFIG; // Feed/pet/kick/clear watchdog
LED1 = 0; // LED1 on
}
}
}
99
S dng WDT nh mt b
nh thi
Nu khng dng kim tra li chng
trnh, WDT c th c s dng nh mt
b nh thi .
Bt bt WDTTMSEL trong thanh ghi
WDTCTL s t WDT vo ch m, tuy
nhin khi t gii hn th WDTIFG bt ln
m khng khi ng li VK
Vic c WDTCNT cho bit thi gian
xy mt s kin
100
Timer_A
L b nh thi a nng thng dng, c mt trong mi chp
MSP430. B nh thi gm 2 khi ln
Timer block: L khi li vi thanh ghi TAR 16 bt, khi
chn xung nhp v khi chia tn lm chm. Khi TAR
khng c tn hiu ra nhng c th bt c TAIFG khi TAR
v 0
Capture/compare channels: L khi bt tn hiu v so
snh, c 3 khi c lp vi cc ch s 0,1 v 2. Khi ny
gm 0 khi con nh sau
101
Khi bt tn hiu Capture : Nhn tn hiu cn m t bn
ngoi
Khi so snh Compare Gm thanh ghi TACCR0 (hoc
1,2) m s tn hiu hoc c t bng phn mm.
Khi to ngt : bt c CCIFG khi TAR v TACCR bng
nhau.
Khi ly mu Sample to tn hiu so snh
.
102
103
Cc ch nh thi
104
Bn ch hot ng
Stop (MC = 0): B nh thi dng hot ng. Mi thanh
ghi gi nguyn gi.
m ln (MC=1) TAR s m ln ti TACCR0 (i vi
knh 0) v quay v 0.
Lin tc (MC= 2): m ln 0xFFF ri quay v 0
m ln/xung(MC= 3): Thanh ghi TAR m ln n
TACCR0 ri m xung ti 0 v lp li
.
105
H thng nhng
Ts. L Mnh Hi
Khoa CNTT,
H K thut Cng ngh TP HCM
Embedded Systems
106
Chapter 10 : Communication
1. Communication Peripherals in the MSP430
2. Serial Peripheral Interface
3. SPI with the USI
4. SPI with the USCI
5. Inter-integrated Circuit Bus
6. A Simple IC Master with the USCI_B0
7. A Simple IC Slave with the USI on a F2013
107
108
Communication Peripherals in the
MSP430
The universal serial interface (USI) is a lightweight module, which
is included in the small F20x2 and F20x3 devices. For a start, it
handles only synchronous communicationSPI and IC.
Universal Serial Communication Interface
larger devices in the MSP430F2xx and MSP430F4xx families contain
one or more universal serial communication interface (USCI)
modules. The hardware handles almost all aspects of the
communication, unlike the USI, so the software needs only to provide
the data to transmit and store the received data in normal operation.
Typically this requires only a couple of small interrupt service
routines.
Universal Synchronous/Asynchronous Receiver/Transmitter
(USART) is an older module, which has been superseded by the
USCI.
109
110
Serial Peripheral Interface
The serial peripheral interface was introduced by
Motorola and is the simplest synchronous
communication protocol in general use.
The only problem is that it is not a fixed standard like
IC. There are plenty of options within standard SPI
and innumerable variations that go beyond this.
111
The concept of SPI is based on two shift registers, one in
each device, which are connected to form a loop.
The registers usually hold 8 bits. Each device places a new
bit on its output from the most significant bit (msb) of the
shift register when the clock has a negative edge and reads
its input into the lsb of the shift register on a positive edge
of the clock.
Thus a bit is transferred in each direction during each clock
cycle.
After eight cycles the contents of the shift registers have
been exchanged and the transfer is complete.
Transmission and reception are clearly inseparable.
112
The main pins are labeled SOMI, SIMO, and CLK (2 USCI)
113
SPI block in USCI
114
SPI operation
There are separate shift registers for transmitting and receiving
Moreover, these registers are double-buffered and the user has no
direct access to the shift registers themselves.
This means that a byte is moved from the receive shift register to
RXBUF as soon as reception is complete, which leaves the shift
register ready to accept the next transfer.
Similarly, a byte written to TXBUF remains in its buffer until the
previous byte has been transmitted, at which point it is moved to the
transmit shift register.
This relaxes considerably the constraints on handling interrupts in
the USI, where the shift register must be read and updated rapidly
between transfers. Although there are separate registers,
reception and transmission are not independent because of the
nature of SPI.
115
Read an examples C code for SPI communication
For Master
msp430g2xx3_uscia0_spi_09.c
And for Slave
msp430g2xx3_uscia0_spi_10.c
116
Inter-integrated Circuit Bus
The IC bus was introduced by Philips (now NXP)
Semiconductors. It was widely adopted and has become
even more popular since its patents expired in 2006. It is a
true bus, unlike SPI, with a specification and user manual
that can be downloaded from NXP.
Revision 03 of the user manual is document UM10204,
dated June 19, 2007. It is clearly written and a lot easier to
read than you might expect. The IC bus uses only two,
bidirectional lines:
Serial data (SDA).
Serial clock (SCL).
117
Structure
Operation: Read from page 534 -542
n tp H thng nhng
1. Cu trc tng th ca vi iu khin
2. S khi ca chp TI MSP430G2553
3. B nh MSP430G2553: Phn b v tr b nh v
ngha tng vng nh
4. Cu to CPU v ngha cc thanh ghi trong CPU
5. Cc loi xung nhp (clock) v cc ch hot ng
6. Hm v cc bc thc hin khi gi mt hm
7. Khi nim ngt v chng trnh phc v ngt
8. Cc bc thc thi khi thc hin mt ngt.
9. Cc ch cng sut thp.
10. Cc cng nhp xut s (Digital Input and Output).
11. Qut ma trn bn phm. Chng di
12. Cc loi LCD. S chn kt ni theo chun
HD44780
13. Cc loi timer. Cu trc v hot ng ca WDT
14. Cu trc v cc ch hot ng ca TimerA0
15. Kt ni Serial Peripheral Interface (SPI). Cu trc
v hot ng.
16. Kt ni Inter-integrated Circuit Bus (I2C).
Kim tra gia k
Vit CT hin th pht v giy trn Led 7
on. S dng Timer A (7 im)
C 1 mi giy n LED L4 phi sng / tt
du chm (LED h) 1 ln