Sinh vin thc hin: Phm Vn Hng 20116122 Nguyn Cng Thnh 20136941 L Cng Khu 20136922
1.Cu trc,chc nng ca b iu khin Clock B iu khin Clock to cc xung ng h cho ton b chip,bao gm c clock h thng v cc clock ngoi vi.B iu khin clock cng thc hin chc nng kim sot ngun vo i vi chc nng On/Off,la chn ngun clock v chia clock. Chip thc hin ch power-down v CPU thc hin ccWFI khi PWR_DOWN_EN (PWRCON [7]) bit v PD_WAIT_CPU (PWRCON [8]) bit c hai thit lp 1. Trong ch power-down,b iu khin clock tt clock thch anh 4~24MHz ngoi v b dao ng ni 22.1148MHz tit kim in nng tiu th ca h thng. 1.1 B to clock gm c 5 b pht xung: ngun xung ngoi 32.768kHz ,tc thp ngun xung ngoi 4-24MHz,tc cao ngun xung lp trnh PLL out b dao ng ni 22.1184MHz b dao ng ni 10kHz
1.2 System Clock v SysTick Clock a.System Clock system clock c 5 ngun clock c to ra t B to clock.Vic chuyn i ngun clock ph thuc vo thanh ghi HCLK_S(CLKSEL0[2:0])
b.Systick Clock Ngun clock ca SysTick trong Cortex -M0 c th s dng ng h CPU hoc ng h bn ngoi (SYST_CSR [2]). Nu s dng ng h bn ngoi, ng h SysTick (STCLK) c 5 ngun ng h. Vic chuyn i ngun ng h ph thuc vo cc thit lp ca thanh ghi STCLK_S (CLKSEL0 [5: 3])
1.3 Clock ngoi vi Cc clock ngoi vi c th c coi l 1 ngun clock ph thuc vo ngun clock trong thanh ghi iu khin(CLKSEL1,CLKSEL2 v CLKSEL3) 1.4 Clock ch Power-down Khi chip vo ch power-down th 1 s ngun clock,system clock v 1 s clock ngi vi s dng hot ng.Tuy nhin vn cn 1 s clock hot ng : + B to clock -B to dao ng 10KHz -Thch anh ngoi 32.768KHz
2.Cu trc,chc nng GPIO NUC140 c 80 chn I/O dng chung c th c chia s cho nhiu chc nng khc nhau.80 chn ny c chia lm 5 cng GPIOA,GPIOB,GPIOC,GPIOD,GPIOE. Cc cng A,B,C,D,E c ti a 16 chn,cng F c ti a 4 chn.80 chn ny l c lp v c cc bit tng ng kim sot ch . C 4 loi I/O: quasi bi-direction push-pull output open-drain output input vi tr khng cao
Cc chn I/O c th cu nh bng phn mm mang chc nng input,output,m cng hoc l quasi bi-direction.Sau khi reset, ch I / O ca tt c cc chn l ty thuc vo cc thit lp trong Config0 [10] .