Mini-project: QPSK Digital

Transmitter/Receiver
Mani Vaya
Nasir Ahmed
Introduction:
In this project we implement quadrature phase shift keying (QPSK) end-to-end digital
transmitter/receiver. The digital transmitter in our project randomly generates binary
data, which is then modulated using QPSK. This signal is then received by the digital
receiver, which performs multiple operations to recover the transmitted signal. Firstly,
because we are using a carrier to modulate the transmitted signal, we must demodulate
the signal. The demodulation requires knowledge of the carrier frequency, and the use of
a low pass filter. The first step in demodulation is to break up the received signal into its
constituent inphase and quadrature phase components. This is procedure is easily done
using knowledge of the carrier frequency and low pass filters. However, because the
channel may introduce an offset into the transmitted signal, a carrier offset recovery
block is needed. This block performs a phase lock loop (PLL) to recover the phase of the
transmitted signal. After phase recovery, the inphase and quadrature phase data are sent
to match filters, which produce peaks at the time at which the filter output should be
sampled. To discover the correct sampling instance, a symbol timing recovery block is
needed. This block uses a delay lock loop (DLL) to lock onto the correct sampling
instance. After the symbol timing recovery, the sampled data is then unmapped to
discover which bits were sent from the transmitter. Each of the constituent components
of the transmitter and receiver described above will be further elaborated upon in the
coming sections. The focus of our project was the MATLAB implementation of the
digital transmitter/receiver. In our simulations, we will incorporate distortion at the
receiver to test the abilities of our PLL and DLL. That is, we will put a carrier offset that
is to be discovered by the PLL, and also assume no knowledge of the symbol timing at
the output of the matched filter.
DIGITAL TRANSMITTER
Quadrature phase shift keying:
Binary data bits are grouped into chunks and each chunk is mapped to a particular
waveform called a symbol which is sent across the channel after modulation by the
carrier. This requires having a separate symbol for each possible combination of data
chunks. In QPSK, each chunk consists of two bits, which determine the inphase and
quadrature gain for the modulator. To produce a unique waveform for each two bit
chunk, we keep the gains constant over a number of samples which is called the symbol
period.

To transmit two bits per symbol period, QPSK uses orthogonal waveforms (sine
and cosine) referred to as the quadrature signals. The data to be transmitted on the
inphase is modulated with the cosine wave, while the quadrature phase data is modulated
with the sine wave. Due to the orthogonality of the sine and cosine basis functions, the
data on the inphase and quadrature phase can be independently recovered at the receiver.
The figure below demonstrates the typical organization and bit mapping of the QPSK
constellation:
quadrature phase
01

00

inphase

11

10

Figure 1: QPSK constellation diagram

The following is the QPSK modulated waveform that was produced from our
simulations:
QPSK transmitted signal

1
0.8
0.6

amplitude

0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1

10

15

time

20

25

30

Figure 2: QPSK transmitted signal

35

Figure 3: QPSK Transmitter:

Cos(c*n)

I/Q
LUT

S/P
Data
bits

Si(n)
T(n)
Sq(n)

Sin(c*n)

Figure 4: Digital Receiver System:

Symbol
timing
recovery

Carrier
recovery

Fsymb

Cos(c*n)
LPF

Si(n)

MF
Symbol
Quantization
and
Unmapping

Y(n)

Sq(n)
LPF
Sin(c*n)

MF

Serial Data
Output

DIGITAL RECEIVER
Carrier Offset Recovery :

For locking on to the carrier of a received modulated signal,

the phase locked loop plays a critical role in any coherent communication system. In an ideal
communication system we know the transmitted carrier frequency and we need to calculate its
phase offset for accurate demodulation. Due to imperfections in the transmitter, the actual carrier
frequency may be slightly different than the expected frequency.
We can model the difference between the actual and expected carrier frequencies as a
time varying phase. A Phase locked looping system can track this time varying phase if the
frequency mismatch is small relative to the carrier frequency.

Cos(n*^c )
Zi(n)

X(n)

Low-Pass
Filter

Zq(n)

Low-Pass
Filter
Phase
Detector

Loop
Filter

Sin(n*^c)

Figure 5: PLL Block Diagram

Numerically Controlled Oscillator: Given an analog system, the phase recovery is often

achieved using a voltage controlled oscillator that allows for precise adjustment of the
carrier frequency based on the output of the phase detecting circuit.
In a digital system we use a Numerically controlled oscillator to recover the
phase. Consider the following expression for carrier sinusoid:
sin(n + c)
=
sin((n))
where (n) = n + c (n and c represent the carrier frequency and phase respectively.)
This time varying phase can be expressed as (n)= nm=0 (c)+ c and recursively as :
(n)

(n-1) + c

The Numerically controlled oscillator keeps track of the phase and forces a phase offset
into the demodulationg carrier by incorporating an extra term as follows:
(n)

(n-1) + c +pd(n)

where pd(n) is the phase offset at time n.

Phase detector: We can represent the actual received carrier frequency as the expected
carrier frequency with some offset:
c = c + (n)
The NCO generates the demodulating sine and cosine with the expected digital frequency
c and offsets this frequency with the output of the loop filter. The NCO frequency can
hence be modeled as
^c = c + ^(n)
Zi(n)= (cos(c)+ sin(c)) * cos(^c)
= * (cos(c+^c) +cos(c-^c) + sin(c+^c) + sin(c-^c))
Zq(n)= (cos(c)+ sin(c)) * sin(^c)
= *{sin(^c+c)-sin(^c-c) + cos(^c+c)+ cos(^c-c)}
We can now apply a low pass filter to remove the double frequency terms and we will be
left with:
Yi(n)= cos( (n)- ^(n)) + sin((n)- ^(n))
Yq(n)= cos(^(n)- (n)) - sin((n)- (n))
We now subtract the above two to obtain only the sine terms:
Yi(n)- Yq(n) = sin((n)- ^(n))
When the phases are only slightly mismatched we can say that :
Sin() = for small
Hence we can approximate the value of Yi(n)-Yq(n) to be equal to phase difference. To
get a correct sign estimate of the phase, the phase detector is set to minus one times the
value of the subtracted signal.
Loop filter: The estimated phase mismatch estimate is fed to the NCO via a loo filter often a
simple low pass filter:
Y(n) = o.4*x(n) + 0.6*y(n-1)
We also use a gain factor of 0.15 for the loop gain.

We have to note that each time an amplitude transition occurs, it is equivalent to a phase
shift of the carrier by pi/2. Immediately after this phase change occurs the PLL begins to
adjust the phase to force the phase difference to zero.

The following curves were obtained for different constant offsets that were introduced in
the channel. Note the behavior of Zi-Zq, which is the received signal, demodulated by
quadrature phase signal and offset by the PLL. Upon low pass filtering Zi-Zq we get the
crude phase offset, which is then processed by the loop filter and NCO to get the new
demodulating signals.
Figure 6: Zi-Zq plots for various offsets
0.15
0.1
0.05

Zq

0
-0.05
-0.1
offset = 1/1000
offset= 10/1000
offset= 100/1000

-0.15
-0.2

50

100

150

200

250

300

Figure 7: Phase offset obtained after low pass filtering Zi-Zq

0.15
0.1
0.05
0
-0.05
-0.1
offset = 10/1000
offset = 1/1000

-0.15

offset= 100/1000
-0.2

50

100

150

200

250

300

Symbol Timing Recovery:

The symbol timing recovery block assumes that the received signal has been
coherently demodulated and filtered using a low pass FIR filter. The next step is for the
receiver to sample the recovered message signals (inphase and quadrature channels) at
the desired symbol rate. Even though the symbol rate is typically known to the receiver,
when to actually sample the signal is generally unknown. This is the job of the symbol
timing recovery, to discover when to sample the signal. Prior to symbol timing
recovery, a matched filter is used. This matched filter is to aid in the timing recovery for
it will have a peak at multiples of the sampling interval, and it also helps suppress the
effects of noise.
The method we used for symbol timing recovery was a delay locked loop (DLL).
The block diagram is shown next:

Offset
Decision

Si(n)
Averaging Filter

Symbol
Sampler

late sampling

early sampling
on time sampling

Figure: DLL Block diagram

In this figure, the averaging filter is the matched filter. The input to the matched
filter is the low pass filtered output of the demodulation process using the carrier-offset
recovery. Si in the above figure denotes this value for the I (inphase) channel. The
Symbol sampler takes in samples at the sampling rate, and the system also knows the
number of samples per symbol (Ts). In our implementation, the number of samples per
symbol was 16. The symbol sampler simply counts until 16 samples have passed, then it
knows to make an on time sample. This on time sample is assumed to be the correct
sampling time, and is fed to the next stage of the decoding. However, the symbol timing
recovery then checks the validity of the on time sampling. Basically, it takes the previous
sample, and the next sample and subtracts them. Ideally, if the on time sample was at a
peak of the match filter output, then the early and late sample would be equal. However,

if this is not the case, then the difference between the early and late is multiplied by the
on time sampling value and summed together. Once this sum passes a threshold, then it
is apparent that we are not sampling at the correct time for our on time sample. So, an
appropriate offset is incorporated (we simply increment/decrement the counter which was
counting from Ts to zero). Then, the running sum for the decision is cleared and we once
again start performing our test to see if our new estimate of the on time sampling instance
is correct. For example, if after the first adjustment we are now sampling at the correct
location, then the early sample would equal the late sample, and the running sum would
never exceed the threshold. We are thus locked onto the correct sampling instance.
This DLL system works quite well in locking on to the correct sampling instance. It is
dependent on the threshold value chosen. After experimentation with thresholds, we
chose one that would give us a quick lock to the correct sampling instance. The figure
below shows an example of this DLL algorithm for a square wave signal:
Matched filtered signal and on time sampling instance using DLL

1.5

amplitude

0.5

-0.5

-1

-1.5

20

40

60

80

100
time

120

140

160

180

200

Figure 8: Symbol Timing Recovery

As can be seen from the above figure, after just a few samples, the DLL algorithm
locks on to the correct sampling instance, which is the peak of the triangle wave. This
simple example assumed a square wave as the input to the matched filter, and the data
was of the form (+1,-1,..). The DLL was incorporated into our system to match to the
correct sampling instance for the inphase and quadrature phase components of the
received signal.

Conclusions:
We implemented an end-to-end digital transmitter system, which comprised of:

Digital QPSK transmitter

Carrier offset recovery
Symbol timing recovery
Bit error rate calculation

The simulation parameters we used were:

Modulation scheme = QPSK
Digital carrier frequency = /2
Symbol period = 16 samples
Block length = 256 bits
Average transmit power = 1 unit
Our implementation was robust to different channel carrier offsets, and the timing
recovery (DLL) performed optimally. Even for time varying carrier offsets, our system
was able to correctly demodulate using the recovered phase. For the timing recovery, the
receiver assumed the first sample was on-time even though it wasnt. However, within
a few symbol periods, it was able to lock onto the correct sample.
We also analyzed the performance of our system under a noisy channel defined by :
t=t+sigma*randn(1,length(t)); which produces additive white gaussian noise of variance
sigma squared.

-3

BER v/s noise variance

x 10

BER

0
0.1

0.2

0.3

0.4

0.5
0.6
noise variance

0.7

0.8

0.9