Bi th nghim 1

Cng tc, n, v b ghp knh

Mc ch ca bi th nghim ny l tm hiu cch kt ni cc thit b u vo v u ra n
gin vo mt chip FPGA v thc hin mt mch s dng cc thit b ny. Chng ta s s dng cc
cng tc SW170 trn Kit DE2 nh cc u vo ca mch. Chng ta cng s s dng it pht
quang (LED) v LED 7 thanh nh cc thit b u ra.
Phn I
Kit DE2 cung cp 18 cng tc , c gi l SW170, c th c s dng nh cc u vo cho
mch, v 18 n chiu sng mu , c gi l LEDR170, c th c s dng hin th gi tr
u ra. Hnh 1 cho thy mt mun Verilog n gin s dng cc cng tc v th hin trng thi
ca chng trn cc n LED. Do chng ta c 18 cng tc v n, nn rt thun tin khi coi chng
nh cc vect trong m Verilog, nh miu t. Chng ta s dng mt biu thc gn n l cho tt
c 18 LEDR u ra, vic ny tng ng vi cc php gn hn hp:
assign LEDR [17] = SW [17];
assign LEDR [16] = SW [16];
...
assign LEDR [0] = SW [0];
Kit DE2 c cc kt ni cng gia chip FPGA, cc cng tc v n ca n. s dng SW170 v
LEDR170, chng ta cn thm vo d n Quartus II ca bn cc php gn chn chnh xc, c ch
ra n cun Hng dn S dng DE2. V d, hng dn s dng xc nh rng SW0 c kt ni
vi chn N25 v LEDR0 c kt ni vi chn AE23 ca FPGA. Mt cch rt hay gn chn
theo yu cu l import vo Quartus II tp tin DE2_pin_assignments.csv, c cung cp trong a
CD H thng DE2 v trong mc Chng trnh i hc trn trang web ca Altera. Cc th tc
thc hin vic gn chn c m t trong hng dn Gii thiu Quartus II S dng Thit k bng
Verilog, cng c sn t Altera.
Vic nhn thc c cc php gn chn trong tp tin DE2_pin_assignments.csv ch c ch khi khi
tn chn c a ra trong tp tin chnh xc ging nh tn cng c s dng trong module
Verilog ca bn. Tp tin s dng cc tn gi SW [0] ... SW [17] cho cc cng tc v cc tn gi
LEDR [0] ... LEDR [17] cho cc n, y l l do ti sao chng ta s dng cc tn ny trong hnh
1.
// Mt m un Verilog n gin kt ni cc cng tc SW vi cc n LEDR
module part1 (SW, LEDR);
input [17:0] SW;
// cc cng tc gt
output [17:0] LEDR; // cc LEDs
assign LEDR = SW;
endmodule
Hnh 1. M Verilog s dng cc cng tc v n ca Kit DE2.
Thc hin cc bc sau y thc hin mt mch tng ng vi m trong hnh 1 trn Kit DE2.
1. To mt d n Quartus II mi cho mch ca bn. Chn Cyclone II EP2C35F672C6 lm target
chip, y l chip FPGA trn Kit DE2 Altera.
2. To mt module Verilog cho on m trong hnh 1 v thm n vo trong d n ca bn.

3. Thm vo trong d n ca bn cc php gn chn cn thit cho Kit DE2, nh ch ra trn.

Bin dch d n.
4. Ti mch bin dch vo chip FPGA. Kim tra chc nng ca mch bng cch gt cc cng tc
v quan st cc n LED.
Phn II
Hnh 2a biu din mt mch tngcatch thc hin mt b ghp knh 2to1 vi mt u vo la
chn s. Nu s = 0 the b ghp knh ca output m is bng input x, v nu s = 1 the u ra l bng
y. Phn b of hnh cho mt s tht Kit cho b ghp knh ny, part c shows biu tng mch ca n.

a) Mch

b) Bng chn l

c) K hiu

Hnh 2. Mt b ghp knh 2to1.

B ghp knh c th c m t bi biu thc Verilog sau y:
assign m = (~ s & x) | (s & y);
Bn hy vit mt module Verilog bao gm 8 php gn ging nh trn m t mch c a ra
trong hnh 3a. Mch ny c hai u vo 8bit, X v Y, v to nn u ra 8bit M. Nu s = 0 th M =
X, trong khi nu s = 1 th M = Y. Chng ta hy coi mch ny l b ghp knh 8bit 2to1. K
hiu ca n c biu din trong hnh 3b, trong X, Y, v M c m t nh cc wire c rng
8bit. Thc hin cc bc sau y.

a) Mch

b) K hiu
Hnh 3. Mt tmbit 2to1 b ghp knh.

1. To mt d n Quartus II mi cho mch ca bn.

2. Thm tp tin Verilog cho b ghp knh 2to1 8bit vo trong d n ca bn. S dng cng tc
SW17 trn Kit DE2 cho u vo s, cng tc SW70 cho u vo X v SW158 cho u vo Y. Kt
ni cc cng tc SW n cc n mu LEDR v kt ni u ra M ti cc n mu xanh
LEDG70.
3. Thm vo trong d n ca bn cc php gn chn cn thit cho Kit DE2. Nh tho lun trong
phn I, cc php gn chn ny cn m bo rng cc cng u vo ca m Verilog ca bn s s
dng cc chn trn FPGA Cyclone II c kt ni vi cc cng tc SW, v cc cng u ra ca m
Verilog bn vit s s dng cc chn FPGA kt ni vi cc n LEDR v LEDG.
4. Bin dch d n.
5. Np mch bin dch vo chip FPGA. Kim tra chc nng ca b ghp knh 8bit 2to1 bng
cch gt cc cng tc v quan st cc n LED.
Phn III
Trong hnh 2, chng ta c th thy mt b ghp knh 2to1 la chn gia cc u vo x v y.
Trong phn ny, chng ta s xem xt mt mch trong u ra m c la chn t 5 u vo u, v,
w, x, v y. Phn a ca Hnh 4 cho chng ta thy lm th no c th xy dng mt b ghp knh
5to1 theo yu cu bng cch s dng bn b ghp knh 2to1. Mch s dng mt u vo la
chn 3bit s2s1s0 v a ra cc bng chn l c biu din trong hnh 4b. K hiu cho b ghp
knh ny c a ra trong phn c ca hnh 4a.
Nh li t hnh 3 rng mt b ghp knh 2to1 8bit c th c xy dng bng cch s dng
8 b ghp knh 2to1. Hnh 5 p dng nguyn l ny nh ngha mt b ghp knh 5to1 3
bit. N bao gm 3 trng hp ca mch trong hnh 4a.

a) Mch

b) Bng Chn l

c) K hiu
Hnh 4. Mt b ghp knh 5to1.

Hnh 5. Mt b ghp knh 5to1 3bit.

Thc hin cc bc sau y thc hin b ghp knh 5to1 3bit.
1. To mt d n Quartus II mi cho mch ca bn.
2. To mt module Verilog cho b ghp knh 5to1 3bit. Kt ni u vo la chn ca n ti cc
cng tc SW1715, v s dng 15 cng tc cn li SW140 cung cp cho 5 u vo 3 bit t U
n Y. Ni cc cng tc SW vi cc n LEDR v kt ni u ra M vi cc n xanh LEDG2
0.
3. Thm vo trong d n ca bn cc php gn chn cn thit cho Kit DE2. Bin dch d n.

4. Np mch bin dch vo chip FPGA. Kim tra cc chc nng ca b ghp knh 5to1 3bit
bng cch gt cc cng tc v quan st cc n LED. m bo rng mi u vo U ti Y c th
c chn ng ging nh u ra M.
Phn IV
Hnh 6 cho thy mt mun gii m LED 7 thanh c u vo 3bit c2c1c0. B gii m ny to
nn 7 u ra c s dng hin th mt k t trn mt LED 7 thanh. Bng 1 lit k cc k t
c hin th cho mi gi tr ca c2c1c0. gi cho thit k n gin, ch c bn k t c a
vo trong bng (Cng vi k t 'trng', c dnh cho m 100 111).
7 thanh LED c xc nh bi cc ch s t 0 n 6 c biu din trong hnh. Mi on c
chiu sng bng vic a n v gi tr 0 logic. Bn s vit mt module Verilog thc hin chc nng
logic nhm i din cho cc mch cn thit kch hot mi thanh ca LED 7 thanh. Ch cn s
dng cc biu thc gn assign n gin trong on m Verilog ca bn xc nh tng chc nng
logic bng cch s dng mt biu thc Boolean.

Hnh 6. Mt b gii m LED 7 thanh.

Bng 1. Bng m cc k t.
Thc hin cc bc sau y:
1. To mt d n Quartus II mi cho mch ca bn.
2. To mt module Verilog cho cc b gii m LED 7 thanh. Kt ni cc u vo c2c1c0 cho cc
cng tc SW20, v kt ni cc u ra ca b gii m ti LED 7 thanh tng ng vi HEX0 trn
Kit DE2. Cc thanh trn HEX0 c gi l HEX00, HEX01, ..., HEX06, tng ng vi hnh 6.
Bn nn khai bo cng 7bit
output [0:6] HEX0;
trong m Verilog ca bn tn ca cc kt qu u ra ph hp vi tn tng ng trong Hng
dn S dng DE2 v tp tin DE2_pin_assignments.csv.
3. Sau khi thc hin gn chn theo yu cu trn Kit DE2, bin dch d n.

4. Np mch bin dch vo chip FPGA. Kim tra chc nng ca mch bng cch gt cc cng
tc SW20 v quan st trn LED 7 thanh.
Phn V
Hy xem xt mch c biu din trong hnh 7. N s dng mt b ghp knh 5to1 3bit cho
php la chn mt trong nm k t c hin th trn mt LED 7 thanh. S dng cc b gii m
LED 7 thanh t Phn IV, mch ny c th hin th bt k k t no trong s cc k t H, E, L, O,
v 'trng'. Cc m k t c thit lp theo bng 1 bng cch s dng cc cng tc SW140, v
mt k t c th c la chn hin th bng cch thit lp cc cng tc SW1715.
Mt bn phc tho m Verilog i din cho mch ny c cung cp trong hnh 8. Lu rng
chng ta s dng cc mch t Phn III v IV nh nhng mch nh trong on m ny. Bn ang
m rng cc m trong hnh 8 sao cho n c th s dng 5 LED 7 thanh thay v ch s dng mt
thanh. Bn s cn phi s dng nm mch nh. Mc ch ca mch ny l hin th bt k t no
bao gm cc k t trong bng 1, v c th xoay vng t ny trn LED 7 thanh khi cc cng tc
SW1715 c gt. V d, nu ch hin th l Hello, sau mch ca bn cn sn xut cc m
hnh u ra minh ha trong bng 2.

Hnh 7. Mt mch in c th la chn v hin th mt trong nm k t.

module part5 (SW, HEX0);
input [17: 0] SW;
// cc cng tc gt
output [0:6] HEX0; // LED 7 thanh
wire [02:00] M;
mux_3bit_5to1 M0 (SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3],
SW[2:0], M);
char7_seg H0 (M, HEX0);
endmodule
// Thc hin mt b ghp knh 5to1 3bit
module mux_3bit_5to1 (S, U, V, W, X, Y, M);
input [2:0] S, U, V, W, X, Y;
output [2:0] M;
// ... Code khng c hin th

endmodule
// Thc hin mt b gii m LED 7 thanh cho H, E, L, O, v 'trng'
module char_7seg (C, Display);
input [2:0] C;
// m u vo
output [0:6] Hin th;
// m u ra LED 7 thanh
// ... Code khng c hin th
endmodule
Hnh 8. M Verilog cho cc mch trong hnh 7.

Bng 2. Xoay vng t Hello trn nm LED 7 thanh

Thc hin cc bc sau y.
1. To mt d n Quartus II mi cho mch ca bn.
2. Thm mun Verilog ca bn vo trong d n Quartus II. Kt ni cc cng tc SW1715 ti
cc u vo la chn ca mi b ghp knh 5to1 3bit. Ngoi ra, ni SW140 ti tng b ghp
knh theo yu cu to ra cc m hnh ca cc k t c biu din trn Bng 2. Kt ni u ra
ca nm b ghp knh ti cc LED 7 thanh: HEX4, HEX3, HEX2, HEX1 v HEX0.
3. Thm cc php gn chn theo yu cu cho Kit DE2 cho tt c cc cng tc, n LED, v LED 7
thanh. Bin dch d n.
4. Np mch bin dch vo chip FPGA. Kim tra chc nng ca mch bng cch thit lp cc m
s k t thch hp trn cc cng tc SW140 v sau gt cc cng tc SW1715 quan st s
quay vng ca cc k t.
Phn VI
M rng thit k ca bn t Phn V c th s dng tt c 8 LED 7 thanh trn Kit DE2. Mch
ca bn c th hin th cc t vi nm k t (hoc t hn) trn 8 LED 7 thanh, v xoay vng t
c hin th khi cc cng tc SW1715 c gt. Nu t hin th l HELLO, mch ca bn s to
nn cc m hnh c biu din trn bng 3.

Bng 3. Xoay t Hello trn 8 LED 7 thanh

Thc hin cc bc sau y:
1. To mt d n Quartus II mi cho mch ca bn v chn chip mc tiu l Cyclone II
EP2C35F672C6.
2. Thm mun Verilog ca bn vo trong d n Quartus II. Kt ni cc cng tc SW1715 ti
cc u vo la chn ca tng b ghp knh trong mch ca bn. Ngoi ra, ni cc cng tc
SW140 ti tng b ghp knh theo yu cu to ra cc m hnh ca cc k t c biu din
trong bng 3. (Gi : i vi mt s u vo ca b ghp knh, bn c th s phi chn k t
'trng'). Kt ni u ra ca b ghp knh ca bn ti cc LED 7 thanh HEX7, ..., HEX0.
3. Thm cc php gn chn theo yu cu cho Kit DE2 cho tt c cc cng tc, n LED, v LED 7
thanh. Bin dch d n.
4. Np mch bin dch vo chip FPGA. Kim tra chc nng ca mch bng cch thit lp cc m
s k t thch hp trn cc cng tc SW140 v sau gt cc cng tc SW1715 quan st s
quay vng ca cc k t.

Bi th nghim 2
S v Hin th
y l mt bi th nghim thit k mch t hp c th chuyn i s nh phn sang s thp phn v
s thp phn di dng m nh phn (BCD).
Phn I
Chng ta mun hin th trn LED 7 thanh HEX3 n HEX0 cc gi tr c thit lp bi cc cng
tc SW150. Hy cc gi tr thit lp bng SW1512, SW118, SW74 v SW30 c hin th
tng ng trn HEX3, HEX2, HEX1 v HEX0. Mch ca cc bn s c th hin th cc ch s t 0
n 9, v s coi cc gi tr t 1010 n 1111 l cc gi tr don'tcare (d).
1. To mt d n mi s c s dng thc hin cc mch mong mun trn Kit Altera DE2 .
Mc ch ca bi tp ny l iu khin bng tay cc chc nng logic cn thit cho cc LED 7 thanh.
Cc bn s s dng cc biu thc gn Verilog n gin trong m ca cc bn v xc nh tng hm
logic nh mt biu thc Boolean.
2. Vit mt tp tin Verilog cung cp cc chc nng cn thit. Thm tp tin ny vo trong d n ca
cc bn v gn cc chn trn FPGA kt ni vi cc cng tc v LED 7 thanh, nh c vit
trong Hng dn S dng Kit DE2. Php gn chn c m t trong phn hng dn Gii thiu
Quartus II S dng Thit k Verilog, c sn trong a CD DE2 System v trong phn Chng trnh
i hc trn trang web ca Altera Quartus II.
3. Bin dch d n v np mch bin dch vo chip FPGA.
4. Kim tra cc chc nng ca thit k ca cc bn bng cch gt cc cng tc v quan st cc LED
7 thanh.
Phn II
Cc bn ang thit k mt mch chuyn i mt s nh phn bn bit V = v3v2v1v0 thnh mt s
thp phn hai ch s tng ng D = d1d0. Bng 1 cho thy cc gi tr u ra cn thit. Thit k
mt phn ca mch ny c a ra trong hnh 1. N bao gm mt b so snh kim tra xem gi
tr ca V c ln hn 9 khng, v s dng u ra ca b so snh ny iu khin LED 7 thanh.
Cc bn sp hon thnh thit k ca mch ny bng cch to ra mt mun Verilog bao gm b so
snh, b ghp knh, v mch A (khng bao gm mch B hoc b gii m LED 7 thanh ti thi
im ny). Module Verilog ca cc bn s c u vo 4bit V, u ra 4bit M v u ra z. Mc
ch ca bi tp ny l s dng cc biu thc gn Verilog n gin xc nh cc chc nng logic
yu cu ca mch bng cch s dng cc biu thc Boolean. M Verilog ca cc bn s khng c
bt k biu thc if else, case, hoc cc biu thc tng t no c.

Bng 1. Cc gi tr chuyn i nh phn thp phn.

Thc hin cc bc sau y:
1. To mt d n Quartus II mi cho module Verilog ca cc bn.
2. Bin dch mch v s dng chc nng m phng nhm xc minh cc hot ng chnh xc ca b
so snh, b ghp knh, v mch A ca cc bn.
3. M rng m Verilog ca cc bn thm vo mch B trong hnh 1 cng nh b gii m LED 7
thanh. Thay i cc u vo v u ra trong m Verilog ca cc bn s dng cc cng tc SW3
0 trn Kit DE2 i din cho s nh phn V, v cc LED 7 thanh HEX1 v HEX0 hin th 2
ch s thp phn d1 v d0. Hy chc chn rng trong d n ca cc bn c cc php gn chn
cn thit cho Kit DE2.
4. Bin dch li d n, v sau np li mch bin dch vo chip FPGA.
5. Kim tra mch ca cc bn bng cch th tt c cc gi tr c th ca V v quan st LED 7 thanh.

Hnh 1. Thit k mt phn ca mch chuyn i nh phn thp phn.

Phn III
Hnh 2a biu din mch cho mt b cng y , bao gm cc u vo a, b, v ci, v cc u ra s
v co. Phn b v c ca hnh biu din k hiu v bng chn l cho b cng y , thnh phn ny
a ra tng nh phn hai bit cos = a + b + ci. Hnh 2d cho thy lm th no 4 mun b cng y
ny c th c s dng thit k mt mch cng hai s bnbit. y l loi mch thng
c gi l b cng c nh, v cc tn hiu nh s t b cng y ny n b cng y tip
theo. Vit m Verilog thc hin mch ny, nh c m t di y.

a) Mch b cng y

b) K hiu b cng y

c) Bng chn l ca b cng y

d) Mch b cng 4bit c nh

Hnh 2. Mch b cng y c nh

1. To mt d n Quartus II mi cho mch b cng. Vit mt module Verilog cho mch con b
cng y v vit mt mun Verilog mc cao nht gm bn b cng y .
2. S dng cc cng tc SW74 v SW30 tng ng cho cc u vo A v B. S dng SW8 lm
bit nh cin ca b cng. Kt ni cc cng tc SW vi cc n LEDR tng ng ca chng, v
kt ni u ra ca b cng, cout v S, ti cc n mu xanh l cy LEDG.
3. Thm vo d n cc php gn chn cn thit cho Kit DE2, bin dch mch, v np n vo chip
FPGA.
4. Kim tra mch ca cc bn bng cch th cc gi tr khc nhau cho cc s A, B, v cin
Phn IV
Trong phn II, chng ta tho lun v vic chuyn i cc s nh phn thnh s thp phn. i
khi, vic ny l hu ch khi xy dng cc mch s dng phng php ny hin th s thp phn,
trong mi ch s thp phn c i din bng bn bit. Phng php ny c bit n vi ci
tn s thp phn di dng m nh phn (BCD). V d, gi tr thp phn 59 c m ha di dng
BCD l 0101 1001. Cc bn s thit k mt mch cng 2 s BCD. Cc u vo cho mch l 2 s
BCD A v B, cng vi mt bit nh, cin. u ra s l mt tng BCD S1S0. Lu rng tng ln nht
mch ny c th tnh c l S1S0 = 9 + 9 + 1 = 19. Thc hin cc bc di y.
1. To mt d n Quartus II mi cho b cng BCD ca cc bn. Cc bn nn s dng mch b
cng bnbit t phn III tnh tng 4bit v mt bit nh cho php ton A + B. Mt mch in c
th chuyn i kt qu nmbit ny, vi gi tr ti a 19, vo hai ch s BCD S1S0 c th c
thit k theo mt cch rt ging vi cc b chuyn i nh phn thp phn t phn II. Vit m
Verilog ca cc bn bng cch s dng cc lnh gn n gin xc nh chc nng logic cn thit
khng s dng cc biu thc nh if else hoc case cho phn ny ca bi th nghim.
2. S dng cc cng tc SW74 v SW30 tng ng cho cc u vo A v B, v s dng SW8
cho bit nh cin.
Kt ni cc cng tc SW vi cc n LEDR tng ng, v kt ni tng 4bit cng vi bit nh
to thnh bi php cng A + B ti cc n xanh LEDG. Hin th cc gi tr BCD ca A v B trn
cc LED 7 thanh HEX6 v HEX4, v hin th kt qu S1S0 trn HEX1 v HEX0.
3. Do mch ca cc bn ch x l cc ch s BCD, hy kim tra cc trng hp khi u vo A hoc
B ln hn chn.
Nu iu ny xy ra, hy hin th bng cch bt n xanh LEDG8.
4. Thm vo d n cc php gn chn cn thit cho Kit DE2, bin dch mch, v np n vo chip
FPGA

5. Kim tra mch ca cc bn bng cch th cc gi tr khc nhau cho cc s A, B, v cin.

Phn V
Thit k mt mch cng hai s BCD 2 ch s, A1A0 v B1B0 sn xut S2S1S0 tng ba ch s
BCD. S dng hai trng hp ca mch ca cc bn t phn IV xy dng b cng BCD hai ch
s ny. Thc hin cc bc di y:
1. S dng cc cng tc SW158 v SW70 biu din tng ng 2 s BCD A1A0 v B1B0.
Gi tr ca A1A0 s c hin th trn LED 7 thanh HEX7 v HEX6, trong khi B1B0 s c hin
th ln trn HEX5 v HEX4. Hin th tng BCD, S2S1S0, trn cc LED 7 thanh HEX2, HEX1 v
HEX0.
2. Thc hin cc php gn chn cn thit. Bin dch mch.
3. Ti v mch trong chip FPGA, v kim tra hot ng ca n.
Phn VI
Trong phn V cc bn to ra m Verilog m cho mt b cng BCD hai ch s bng cch s
dng hai on m Verilog cho hai b cng BCD mt ch s t phn IV. Mt cch tip cn khc
m t b cng hai ch s BCD trong Verilog m xc nh mt thut ton ging nh c i
din bng m gi sau:
1) T0 = A0+B0
2) if (T0 > 9) then
3) Z0 = 10;
4) c1 = 1;
5) else
6) Z0 = 0;
7) c1 = 0;
8) end if
9) S0 = T0 Z0
10) T1 = A1 + B1 + c1
11) if (T1 > 9) then
12) Z1 = 10;
13) c2 = 1;
14) else
15) Z1 = 0;
16) c2 = 0;
17) end if
18) S1 = T1 Z1
19) S2 = c2

Tht hp l thng tin khi xem mch no c th c s dng thc hin m gi ny. Dng 1,
9, 10, v 18 i din cc cho b cng, dng 2 8 v 1117 tng ng vi c b ghp knh, v vic
kim tra cc iu kin T0 > 9 v T1 > 9 s cn n cc b so snh. Cc bn s vit m Verilog
tng ng vi m gi ny. Lu rng cc bn c th thc hin cc php cng trong m Verilog ca
cc bn thay v cc php tr c biu din trn dng 9 v 18. Mc ch phn ny ca bi th
nghim l kim tra nh hng ca vic s dng cc biu thc if else so vi cc ton t > v v
+ ca Verilog. Thc hin cc bc sau y:
1. To mt d n Quartus II mi cho m Verilog ca cc bn. S dng cc cng tc, n, v LED 7
thanh nh trong phn V. Bin dch mch ca cc bn.
2. S dng cng c Quartus II RTL Viewer cng c kim tra cc mch c tajora bng cch
bin dch m Verilog ca cc bn. So snh cc mch c cc bn thit k trong phn V.
3. Np mch ca cc bn v Kit DE2 v kim tra n bng cch th cc gi tr khc nhau cho s
A1A0 v B1B0.
Phn VII
Thit k mt mch t hp c th chuyn i mt s nh phn 6bit thnh mt s thp phn dng
BCD. S dng cc cng tc SW50 nhp s nh phn , cc LED 7 thanh HEX1 v HEX0
hin th s thp phn. Thc hin mch ca cc bn trn Kit DE2 v kim tra chc nng ca n.

Bi th nghim 3
Cht, Flipflop, v Thanh ghi
Mc ch ca bi th nghim ny l kho st cc cht, flipflop, v thanh ghi.
Phn I
Cc FPGA ca Altera bao gm cc flipflop sn sng thc hin mch ca ngi s dng. Chng ta
s tm hiu cch s dng cc flipflop trn trong Phn IV ca bi tp ny. Nhng trc tin chng
ta s th hin cch cc phn t nh c th c to ra trong mt FPGA m khng cn s dng flip
flop chuyn dng ca n.
Hnh 1 m t mch cht RS. Hai kiu m Verilog c th c s dng m t mch ny c a
ra trong hnh 2. Phn a ca hnh v nh ngha cht c to thnh t cc cng logic, v phn b s
dng cc biu thc logic to ra cng mt mch. Nu cht ny c thc hin trn mt FPGA c
4 bng tra cu u vo (LUTs), th ch c mt bng l cn thit, nh biu din trong hnh 3a.

Hnh 1. Mch cht RS.

// Mt cht RS
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule
Hnh 2a. M t cht RS bng cc cng logic.
// Mt cht RS
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign R_g = R & Clk;
assign S_g = S & Clk;
assign Qa = (R_g | Qb);
assign Qb = (S_g | Qa);

assign Q = Qa;
endmodule
Hnh 2b. M t cht RS bng cc biu thc logic.
Mc d cht c th c thc hin mt cch chnh xc trong mt LUT 4u vo, song cch ny
khng cho php cc tn hiu ni b ca n, v d nh R_g v S_g, c quan st, bi chng khng
c cung cp di dng u ra t LUT. gi cc tn hiu ni b trong mch thc hin, chng
ta cn thm mt ch th bin dch trong m. Trong hnh 2, ch th /* synthesis keep */ c thm
vo hng dn cho trnh bin dch Quartus II s dng cc cng logic ring bit cho mi tn hiu
R_g, S_g, Qa, v QB. Bin dch m s to ra cc mch vi bn 4LUTs c m t trong Hnh 3b.

(a) S dng mt bng tra cu 4u vo cho cc cht RS.

(b) S dng bn bng tra cu 4u vo cho cc cht RS.

Hnh 3. Thc hin ca cc cht RS trong hnh 1.
To mt d n Quartus II cho cc mch cht RS nh sau:
1. To mt d n mi cho cc cht RS. Chn chip mc tiu l Cyclone II EP2C35F672C6, y l
chip FPGA trn Kit DE2 ca Altera.
2. To ra mt tp tin Verilog vi m phn a hoc b ca hnh 2 (c hai on m ny u m t
cng mt mch) v thm n vo trong d n.
3. Bin dch m. S dng cng c Quartus II RTL Viewer kim tra cc mch mc cng c sinh
ra t m, v s dng cng c Technology Viewer chc chn rng cht c thc hin nh biu
din trong hnh 3b.
4. To mt File VectorWaveform (.vwf) trong quy nh c th cc u vo v u ra ca mch.
V dng sng cho cc u vo R v S v s dng Quartus II Simulator to cc dng sng tng
ng cho R_g, S_g, Qa, v QB. Chc chn rng cht hot ng nh mong i bng cch s dng c
hai kiu m phng theo chc nng v thi gian.
Phn II
Hnh 4 biu din mch cho mt cht D

Hnh 4. Mch cho mt cht D

Thc hin cc bc sau y:
1. To mt d n mi Quartus II. To ra mt file Verilog bng cch s dng kiu m trong hnh 2b
cho cc cht D gated. S dng /* synthesis keep */ ch th m bo rng cc phn t logic ring
bit c s dng thc hin cc tn hiu R, S_g, R_g, Qa, Qb.
2. Chn chip mc tiu l Cyclone II EP2C35F672C6 v bin dch m. S dng cng c Technology
Viewer kim tra mch va thc hin.
3. Chc chn rng cht lm vic ng cho tt c cc iu kin u vo bng cch s dng m
phng chc nng. Kim tra c tnh thi gian ca mch bng cch s dng m phng thi gian.
4. To mt d n Quartus II mi s c s dng thc hin cc cht D trn Kit DE2. D n ny
bao gm mt mun cp cao nht c cha cc cng u vo v u ra (pins) thch hp cho Kit
DE2. Gn cc cht vo trong mun cp cao nht ny. S dng cng tc SW0 iu khin u
vo cht D, v s dng SW1 nh u vo CLK. Kt ni u ra Q n LEDR0.
5. Bin dch li d n ca bn v np mch bin dch vo Kit DE2.
6. Kim tra chc nng ca mch ca bn bng cch gt cc cng tc D v CLK, ng thi quan st
u ra Q.
Phn III
Hnh 5 biu din mch cho mt masterslave flipflop D.

Hnh 5. Mch cho mt masterslave flipflop D.

Thc hin cc bc sau:
1. To mt d n mi Quartus II. To ra mt file Verilog bao gm hai bn sao ca mun cht D
trong phn II thc hin cc masterslave flipflop D.
2. Thm vo trong d n ca bn cc cng u vo v u ra thch hp cho Kit DE2 ca Altera. S
dng cng tc SW0 lm u vo cho flipflop D, v s dng SW1 nh l u vo Clock. Kt ni
u ra Q n LEDR0.

3. Bin dch d n ca bn.

4. S dng cng c Technology Viewer kim tra cc mch flipflop D, v s dng m phng
chc chn hot ng chnh xc ca n.
5. Np mch bin dch vo Kit DE2 v kim tra chc nng ca n bng cch gt cc cng tc D,
Clock v quan st u ra Q.
Phn IV
Hnh 6 biu din mt mch vi ba phn t nh khc nhau: mt cht D, mt flipflop D sn
dng, v flipflop D sn m.

(a) Mch

(b) S thi gian

Hnh 6. Mch v dng sng cho Phn IV.
Thc hin v m phng mch ny bng cch s dng phn mm Quartus II nh sau:
1. To mt d n mi Quartus II.
2. Vit mt tp tin Verilog bao gm ba phn t nh. i vi phn ny, bn khng cn phi s dng
ch th /* synthesis keep */ t Phn I v III. Hnh 7 a ra m hnh hnh vi ca m Verilog nh

ngha cc cht D trong hnh 4. Cht ny c th c thc hin theo mt bng tra cu 4u vo. S
dng m theo kiu tng t nh ngha cc flipflop trong hnh 6.
3. Bin dch m ca bn v s dng cng c Technology Viewer kim tra vic thc hin mch.
Chc chn rng cht ch s dng mt bng tra cu u vo v cc flipflop c thc hin bng
cch s dng cc flipflop cung cp sn trong chip FPGA mc tiu.
4. To mt tp tin VectorWaveform (.vwf), trong quy nh c th cc u vo v u ra ca
mch. V cc phn t u vo D v Clock nh c biu din trong hnh 6. S dng m phng
chc nng c c ba tn hiu u ra. Quan st cc hnh vi khc nhau ca ba phn t nh.
module D_latch (D, Clk, Q);
input D, Clk;
output reg Q;
always@ (D, Clk)
if (Clk)
Q = D;
endmodule
Hnh 7. M Verilog kiu hnh vi nh ngha mt cht D.
Phn V
Chng ta mun hin th gi tr thp lc phn ca mt s 16bit A trn 4 LED 7 thanh HEX74.
Chng ta cng mun hin th gi tr hex ca mt s B 16bit trn 4 LED 7 thanh HEX30. Cc gi
tr ca A v B l cc u vo ca mch c cung cp bi cc cc cng tc SW150. iu ny
c thc hin bng cch thit lp cc cng tc ng vi gi tr ca A v sau thit lp cc cng
tc cn li ng vi gi tr ca B, do , gi tr ca A phi c nh trong mch.
1. To mt d n Quartus II mi s c s dng thc hin cc mch mong mun trn Kit DE2
ca Altera.
2. Vit mt tp tin Verilog cung cp cc chc nng cn thit. S dng KEY0 lm nt reset mc
thp, v s dng KEY1 lm u vo Clock.
3. Thm tp tin Verilog vo trong d n ca bn v bin dch mch.
4. Gn chn trn FPGA kt ni vi cc cng tc v cc LED 7 thanh, nh c ch ra trong
Hng dn S dng cho Kit DE2.
5. Bin dch li mch v np vo chip FPGA.
6. Kim tra cc chc nng ca thit k ca bn bng cch gt cng tc v quan st hin th u ra.

Bi th nghim 4
B m
y l bi th nghim s dng cc b m
Phn I
Hy xem xt cc mch trong hnh 1. y l mt b m 4bit ng b s dng bn flipflop loi T.
B m tng s m ca n trn mi sn dng ca xung ng h nu tn hiu Enable xut hin.
B m c ti lp v 0 bng cch s dng tn hiu Reset. Bn s thc hin mt b m 16bit
thuc loi ny.

Hnh 1. B m 4bit.
1. Vit mt tp tin Verilog nh ngha mt 16bit b m bng cch s dng cu trc c m t
trong hnh 1. Code ca bn nn bao gm mt mun flipflop loi T s m 16 ln to thnh
b m. Bin dch mch.
C bao nhiu phn t logic c s dng thc hin mch ca bn? Tn s ti a, Fmax, mch
ca bn c th hot ng l bao nhiu?
2. M phng mch ca bn xc minh tnh ng n ca n.
3. Ci thin Verilog tp tin ca bn s dng cc nt bm KEY0 lm u vo Clock, cng tc
SW1 v SW0 l cc u vo Enable v Reset, v LED 7 thanh HEX30 hin th cc s thp lc
phn m s ln mch ca bn hot ng. Thc hin cc php gn chn cn thit cn thit thc
hin cc mch trn Kit DE2, v bin dch cc mch.
4. Np mch ca bn vo chip FPGA v kim tra chc nng ca n bng cch vn hnh cc cng
tc thc hin.
5. Thc hin mt phin bn 4bit ca mch trn v s dng Quartus II RTL Viewer xem phn
mm Quartus II tng hp mch ca bn nh th no. S khc bit so vi hnh 1 l g?
Phn II
n gin ha m Verilog m ca bn sao cho cc c im k thut ca b m s da trn biu
thc Verilog sau:
Q <= Q +1;
Bin dch mt phin bn 16bit ca b m ny v so snh s lng cc phn t logic cn thit v
Fmax c th t c.

S dng RTL Viewer xem cu trc thc hin ny v nhn xt v s khc bit vi thit k t
Phn I.
Phn III
S dng mt LPM t Th vin cc module tham s ha thc hin mt b m 16bit. Chn cc
ty chn LPM ph hp vi thit k trn, tc l kch hot v ng b r rng. So snh phin bn
ny vi cc thit k trc y?
Phn IV
Thit k v thc hin mt mch lin tc nhp nhy ch s t 0 n 9 trn LED 7 thanh HEX0.
Mi ch s s c hin th trong khong mt giy. S dng mt b m xc nh khong thi
gian mt giy. B m ny s c tng ln bi cc tn hiu ng h 50 MHz do Kit DE2 cung
cp. Khng dng thm bt k tn hiu ng h khc trong thit k ca bn, hy chc chn rng tt
c cc flipflops trong mch ca bn c nh thi trc tip bi cc tn hiu ng h 50 MHz.
Phn V
Thit k v thc hin mt mch hin th t HELLO, theo kiu ticker tape, trn tm LED 7 thanh
HEX70. Hy lm cho cc ch di chuyn t phi sang tri trong khong thi gian khong mt giy.
Cc mu s c hin th trong cc khong thi gian ng h lin tip c a ra trong Bng 1.

Bng 1. Di chuyn t HELLO theo kiu ticker tape

Bi th nghim 5
ng h v B nh thi

y l bi th nghim v vic thc hin v s dng mt ng h thi gian thc.

Phn I
Thc hin mt b m BCD 3 ch s. Hin th ni dung ca cc truy b m trn cc LED 7 thanh,
HEX20. Ly ra cc tn hiu iu khin, t tn hiu ng h 50 MHz c cung cp trn Kit DE2
ca Altera, tng gi tr ca b m trong khong thi gian mt giy. S dng nt bm KEY0
thit lp li b m v 0.
1. To mt d n Quartus II mi s c s dng thc hin mch mong mun trn Kit DE2.
2. Vit mt tp tin Verilog m t c th mch mong mun.
3. Thm tp tin Verilog trn trong d n ca bn v bin dch mch.
4. M phng mch c thit k xc minh chc nng ca n.
5. Gn chn trn FPGA kt ni vi LED 7 thanh v cc nt bm, nh c ch ra n trong
Hng dn S dng Kit DE2.
6. Bin dch li mch v np n vo chip FPGA.
7. Xc minh rng mch ca bn lm vic mt cch chnh xc bng cch quan st cc LED 7 thanh.

Phn II

Thit k v thc hin mt mch trn Kit DE2 hot ng nh mt ng h thi gian trong ngy. N
s hin th gi (t 0 n 23) trn LED 7 thanh HEX76, pht (t 0 n 60) trn HEX54 v giy (t
0 n 60) trn HEX32. S dng cc cng tc SW150 thit lp cc phn gi v pht ca ng
h c hin th.

Phn III

Thit k v thc hin trn Kit DE2 mt mch phn ng hn gi. Mch s hot ng nh sau:
1. Mch c thit lp li bng cch n phm bm KEY0.
2. Sau mt khong thi gian nht nh, n mu LEDR0 s bt v b m BCD bn ch s s
bt u m trong khong thi gian tnh bng mili giy. Khong thi gian trong vi giy t khi
mch c ti lp cho n khi LEDR0 bt c thit lp bi cc cng tc SW70.

3. Mt ngi c phn x ang c th nghim phi nhn KEY3 cng nhanh cng tt ngt LED
v ng bng cc b m trong trng thi hin ti ca n. S m cho thy thi gian phn ng s
c hin th trn LED 7 thanh HEX20.

Bi th nghim 6
Cc b cng, b tr v b nhn
Mc ch ca bi tp ny l kim tra cc mch s hc thc hin php cng, tr, v nhn cc s.
Mi loi mch s c thc hin theo hai cch: th nht bng cch vit m Verilog m t cc chc
nng cn thit, v th hai bng cch s dng cc mch ph nh ngha sn t th vin cc mun
tham s ha ca ca Altera (LPMs).
Cc kt qu c to ra cho cc cch trin khai khc nhau s c so snh, c v cu trc mch v
tc hot ng ca n.

Phn I

Xem xt li cc mch cng bnbit c nh c s dng trong bi th nghim 2, mt s ca

mch ny c sao chp li trong Hnh 1a. Bn ang to ra mt phin bn 8bit ca b cng ny v
thm n vo trong cc mch c biu din trong Hnh 1b. Mch ca bn s c thit k h tr
cc s c du di dng m b 2, v u ra Overflow s c thit lp v 1 bt c khi no tng
c to bi cc b cng khng a ra ng s c du.

a) Mch b cng 4 bit c nh

b) Mch b cng tm bit s dng thanh ghi

Hnh 1. Mt b cng 8bit vi u vo v u ra l cc thanh ghi

Thc hin cc bc nh m t di y.
1. To mt d n Quartus II mi v vit m Verilog m t cc mch trong Hnh 1b. S dng cu
trc mch trong Hnh 1a m t b cng ca bn.
2. Thm cc cng u vo v u ra cn thit vo trong d n ca bn thc hin cc mch b
cng trn Kit DE2.
Kt ni cc u vo A v B ti cc cng tc SW158 v SW70 tng ng. S dng KEY0 lm
u vo Reset ng b mc thp, v s dng KEY2 lm u vo ng h iu khin bng tay. Hin
th cc kt qu u ra ca b cng trn cc n LEDR70 v hin th u ra Overflow trn n mu
xanh l cy LEDG8. Cc gi tr thp lc phn ca A v B s c hin th trn cc LED 7 thanh
HEX76 v HEX54, cn gi tr thp lc phn ca S s xut hin trn HEX10.
3. Bin dch m ca bn v s dng m phng thi gian xc minh tnh chnh xc cho hot ng
ca mch. Sau khi m phng hot ng ng cch, np mch bin dch ln Kit DE2 v kim tra
n bng cch s dng cc gi tr khc nhau ca A v B. Hy chc chn bn s kim tra hot ng
thch hp ca u ra Overflow.
4. M Compilation Report ca Quartus II v kim tra kt qu bo co ca Analyzer Timing. Tn s
hot ng ti a, fmax, ca mch bn va thit k l bao nhiu? Con ng di nht trong cc
mch trn phng din tr c di l bao nhiu?

Phn II

Sa i mch ca bn t phn I n c th thc hin c hai chc nng cng v tr s 8bit. S

dng cng tc SW16 xc nh xem php cng hay php tr c thc hin. Kt ni cc cng
tc, n, v LED 7 thanh nh m t trong Phn I.
1. M phng mch b cng / b tr mch cho thy rng n hot ng chnh xc, sau np vo
Kit DE2 v kim tra n bng cch gt cc cng tc cho cc trng hp khc nhau.
2. M Compilation Report ca Quartus II v kim tra kt qu bo co ca Analyzer Timing. Tn s
hot ng ti a, fmax, ca mch bn va thit k l bao nhiu? Con ng di nht trong cc
mch trn phng din tr c di l bao nhiu?

Phn III

Lp li phn I bng cch s dng mch b cng nh ngha sn gi l lpm_add_sub, thay v cu

trc b cng c nh t hnh 1. Mun lpm_add_sub ph th c tm thy trong th vin module
tham s ha (LPMs), c cung cp lm phn trong h thng Quartus II ca Altera. Cch s dng
cc mun nh ngha sn trong Quartus II d n c m t trong hng dn S dng cc
Module Th vin trong Thit k Verilog, trong c sn trn a CD DE2 System v phn Chng
trnh i hc trn trang web ca Altera.

1. Cu hnh mun lpm_add_sub n ch thc hin php cng, nhm so snh vi Phn I. Lu li
cu hnh ca mun lpm_add_sub trong tp tin lpm_add8.v. Sau khi thm mun ny vo trong
m Verilog ca bn, bin dch d n v s dng cng c Chip Editor ca Quartus II kim tra
mt s cc chi tit ca mch va thc hin.
Mt cch kim tra cc mch ph ca b cng bng cch s dng cng c Chip Editor c minh
ha trong hnh 2. Trong ca s Project Navigator ca Quartus II, click chut phi vo phn ca h
thng phn cp mch ca bn i din cho mch ph lpm_add8, v chn lnh Locate > Locate in
Chip Editor. Vic ny s m ra ca s Chip Editor th hin trong hnh 3. Cc phn t logic trong
FPGA Cyclone II c s dng thc hin b cng c nh du mu xanh da tri trong cng
c Chip Editor. a con tr chut ca bn ti bt k phn t logic no v nhp p m ca s
Resource Property Editor c biu din trong hnh 4. Trong hp thoi Node, bn c th chn bt
k mt trong s chn phn t logic thc hin mun b cng. Resource Property Editor cho php
bn kim tra cc thnh phn ca mt phn t logic v xem mt phn t logic kt ni vi nhng
phn t khc nh th no.

Hnh 2. Xc nh v tr ca b cng 8bit trong cng c Chip Editor

Hnh 3. Cc phn t logic c nh du cho b cng 8bit.

S dng cc cng c m t trn, v tham kho cc thng tin trong datasheet ca FPGA Cyclone
II, m t mch thc hin b cng 8bit vi mun lpm_add_sub.

Hnh 4. Kim tra cc chi tit trong mt phn t logic bng cch s dng Resource Property Editor.

2. M Quartus II Compilation Report v so snh fmax ca mch b cng ca bn vi thit k trong

phn I. Tho lun bt k s khc bit no v hiu sut c quan st.

Phn IV
Lp li phn II bng cch s dng mch b cng n ngha sn lpm_add_sub, thay v mch b cng
tr ca bn da trn hnh 1.
Bnh lun ngn gn v cu trc mch thu c bng cch s dng cc mun LPM, v so snh
fmax ca mch ny vi thit k t Phn II. M t cc mun lpm_add_sub x l tn hiu trn
Overflow nh th no.

Phn V

Hnh 5a a ra mt v d v php nhn giy v bt ch truyn thng P = A B, vi A = 12 v B =

11. Chng ta cn thm hai php nhn vi phin bn nh phn ca A to thnh tch P = 132. Phn
b ca hnh 5 biu din cng mt v d, nhng s dng cc s nh phn 4bit. V mi ch s trong B
l 0 hoc 1, cc tch ph s l phin bn nh phn ca A hoc 0000. Hnh 5c cho thy lm th no
mi tch ph c th c hnh thnh bng cch s dng ton t AND Boolean trn A vi cc bit
thch hp trong B.

a) Thp phn

b) Nh phn

c) Cch tnh

Hnh 5. Php nhn cc s nh phn.

A fourbit circuit that implements P = A B is illustrated in Figure 6. Because of its regular
structure, this type of multiplier circuit is usually called an array multiplier. The shaded areas in the
circuit correspond to the shaded columns in Figure 5c. In each row of the multiplier AND gates are
used to produce the summands, and full b cng modules are used to generate the required sums.
Mt mch bn bit thc hin php nhn P = A B c minh ha trong hnh 6. Do cu trc thng
thng ca n, loi mch nhn ny thng c gi l b nhn ma trn. Cc khu vc c t m
trong mch tng ng vi cc ct c t m trn hnh 5c. Trong mi hng ca s nhn cc cng
AND c s dng to ra cc tch ph, v cc mun b cng y c s dng to ra
tng cn tnh cn thit.

Hnh 6. Mt mch nhn ma trn.

S dng cc bc sau thc hin mch nhn ma trn:
1. To mt d n Quartus II mi c s dng thc hin cc mch mong mun trn Kit DE2 ca
Altera.
2. To ra file Verilog cn thit, thm vo trong d n ca bn, v bin dch mch.
3. S dng m phng chc nng xc minh rng m ca bn l chnh xc.
4. Ci thin thit k ca bn s dng cc cng tc SW118 i din cho s A v cc cng tc
SW30 i din cho s B. Cc gi tr thp lc phn ca A v B s c hin th trn cc LED 7
thanh HEX6 v HEX4 tng ng. Kt qu P = A B s c hin th trn HEX1 v HEX0.
5. Gn chn trn FPGA kt ni vi cc cng tc v LED 7 thanh, nh c ch ra n trong
Hng dn S dng cho Kit DE2.
6. Bin dch li mch v np n vo chip FPGA.
7. Kim tra cc chc nng ca thit k bn va thc hin bng cch gt cc cng tc v quan st
cc LED 7 thanh.

Phn VI

M rng b nhn ca bn nhn s 8bit v to ra mt tch 16bit. S dng cc cng tc SW158

i din cho s A v cc cng tc SW70 i din cho s B. Cc gi tr thp lc phn ca A v
B s c hin th trn LED 7 thanh HEX76 v HEX54 tng ng. Kt qu P = A B s c
hin th trn HEX30.
Thm cc thanh ghi vo mch ca bn lu tr cc gi tr ca A, B, v P sn phm, bng cch s
dng mt cu trc tng t nh b cng c thanh ghi trong hnh 1.
Sau khi bin dch v th nghim thnh cng mch nhn ca bn, kim tra kt qu sn xut bi
Quartus II Timing Analyzer xc nh fmax trong mch ca bn. Con ng di nht, xt trn
phng din tr, gia cc thanh ghi l bao nhiu?

Phn VII

Thay i Verilog m ca bn thc hin b nhn 8 x 8 nhn bng cch s dng mun
lpm_mult t th vin cc module tham s ha trong h thng Quartus II. Hon tt cc bc thit k
trn. So snh kt qu trn phng din s lng cc phn t logic (LEs) cn thit v fmax ca
mch.

Phn VIII

Nhiu ng dng ca cc mch k thut s rt hu ch c th thc hin mt s lng cc php

nhn v sau to ra mt tng cc kt qu. i vi phn ny ca bi tp, bn s thit k mt mch
thc hin php tnh
S = (A B) + (C D)
Cc u vo A, B, C, v D l s 8bit khng du, v S cung cp mt kt qu 16bit. Mch ca bn
cng s cung cp mt tn hiu c nh, Cout. Tt c cc yu t u vo v u ra ca cc mch phi
c a vo thanh ghi, tng t nh cu trc th hin trong Hnh 1b.
1. To mt d n Quartus II mi s c s dng thc hin cc mch mong mun trn Kit DE2
Altera.
S dng cc mun lpm_mult and lpm_add_sub lm b nhn v b cng trong thit k ca bn.
2. Kt ni u vo A v C vi cc cng tc SW158 v kt ni u vo B v D vi cc cng tc
SW70. S dng cng tc SW16 la chn gia hai b cc u vo: A, B hoc C, D. Ngoi ra, s
dng cng tc SW17 nh u vo kch hot ghi (WE). Thit lp WE mc 1 s cho php d liu
c np vo thanh ghi u vo khi c mt xung ng h xy ra, trong khi thit lp WE mc 0 s
ngn vic np vo ca cc thanh ghi ny.
3. S dng KEY0 lm u vo Reset ng b mc thp, v s dng Key1 lm u vo ng h
iu khin bng tay.

4. Hin th gi tr thp lc phn ca A hoc C, c la chn bng SW16, trn LED 7 thanh
HEX76 v hin th hoc B hoc D trn HEX54. Tng S s c hin th trn HEX30, v tn
hiu Cout s xut hin trn LEDG8.
5. Bin dch m ca bn v s dng cng c m phng chc nng hoc thi gian xc minh rng
mch ca bn lm vic ng.
Sau np mch vo Kit DE2 v kim tra hot ng ca n.
6. Thng th vic m bo rng mt mch k thut s c th p ng yu cu tc nht nh,
chng hn lm tn s ca mt tn hiu c p dng cho mt u vo xung ng h l rt cn thit.
Cc yu cu ny c cung cp mt h thng CAD di hnh thc hn ch v thi gian. Cc bc
thc hin s dng hn ch thi gian trong h thng CAD ca Quartus II c m t trong hng
dn Hn ch Thi gian vi Thit k Da trn Verilog, c sn trn a CD DE2 System v phn
Chng trnh i hc trn trang web ca Altera.
i vi bi tp ny, chng ta ang s dng mt ng h iu khin bng tay c thc hin bng
cng tc bm, do , khng c yu cu v thi gian thc. Nhng minh hoc cc vn v thit
k lin quan, hy coi mch ca bn c yu cu hot ng vi mt tn s ng h 220 MHz.
Nhp tn s ny lm hn ch thi gian trong phn mm Quartus II, v bin dch li d n ca bn.
Timing Analyzer s bo co rng vic p ng yu cu thi gian do di khc nhau ca cc
ng dn t thanh ghi n thanh ghi l khng th. Kim tra bo co phn tch thi gian v m t
ngn gn v s vi phm thi gian c quan st.
7. Mt cch tng tc hot ng ca mt mch nht nh l chn cc thanh ghi vo cc
mch theo cch rt ngn di ca ng dn di nht. K thut ny c gi l k thut ng
ng, v cc thanh ghi c chn vo thng c gi l thanh ghi ng ng. Chn cc thanh ghi
ng ng vo thit k ca bn gia cc b nhn v b cng. Bin dch li d n ca bn v tho
lun v cc kt qu thu c.

Phn IX

Phn mm Quartus II bao gm mt module thit k trc c gi altmult_add c th thc hin cc

tnh ton ca biu thc S = (A B) + (C D). Lp li Phn VIII bng cch s dng mun ny
thay v cc mun lpm_mult v lpm_add_sub. Kim tra mch ca bn bng cch s dng c hai
m phng v bng cch np mch ln Kit DE2.
M t ngn gn cch thc hin va ri c khc g so vi vic s dng cc mun altmult_add.
Kim tra hiu sut ca n c khi c v khng c cc thanh ghi ng ng tho lun trong Phn
VIII.

Bi th nghim 7
My trng thi hu hn
y l bi th nghim s dng cc my trng thi hu hn.

Phn I

Chng ta mun thc hin mt my trng thi hu hn (FSM) xc lp hai trnh t c th ca cc k

hiu u vo c a vo, c th l 4 s 1 lin tip hoc bn s 0 lin tip. C mt u vo w v
u ra z. Bt c khi no w = 1 hoc w = 0 trong bn xung ng h lin tip gi tr ca z l 1; nu
khng, z = 0. Phi hp chng cho c cho php, do nu w = 1 trong nm xung ng h lin
tip u ra z s bng 1 sau khi cc xung th t v th nm. Hnh 1 minh ha mi quan h cn thit
gia w v z.

Hnh 1. Yu cu thi gian cho cc u ra z.

Mt s trng thi FSM ny c th hin trong hnh 2. i vi phn ny, bn l t to ra mt
mch FSM thc hin s trng thi trn, bao gm cc biu thc logic cung cp cho mi flipflops
trng thi. thc hin FSM, s dng 9 flipflops trng thi c gi l Y8, , Y0 v bng m
trng thi c a ra trong Bng 1.

Bng 1. M trng thi cho FSM.

Hnh 2. Mt s trng thi cho FSM.

Thit k v thc hin mch ca bn trn Kit DE2 nh sau.

1. To mt d n Quartus II mi cho mch FSM. Chn chip mc tiu l Cyclone II
EP2C35F672C6, l chip FPGA trn Kit DE2 ca Altera.
2. Vit mt tp tin Verilog bao gm chn flipflops trong mch v xc nh cc biu thc logic iu
khin cc cng vo flipflop. Ch s dng cu lnh gn n gin trong m Verilog ca bn xc
nh mc logic a vo cc flipflops. Lu rng m trng thi cho php bn ly ra c nhng
biu thc ny thng qua vic theo di. S dng cng tc SW0 trn Kit DE2 ca Altera lm u vo
Reset mc thp cho FSM, s dng SW1 lm u vo w, v nt bm KEY0 lm u vo ng h
iu khin bng tay. S dng n LED mu xanh LEDG0 lm u ra z, v gn cc u ra flipflop
trng thi cc n LED mu LEDR8 LEDR0.
3. Thm tp tin Verilog vo trong d n ca bn, v gn chn trn FPGA kt ni vi cc cng
tc v cc n LED, nh c ch ra trong Hng dn S dng cho Kit DE2. Bin dch mch.
4. M phng hnh vi ca mch.
5. Khi bn t tin rng mch hot ng ng theo nh kt qu m phng ca bn, np mch vo
trong chip FPGA. Kim tra chc nng ca thit k bn va thc hin bng cch a cc chui u
vo v quan st cc n LED u ra. Hy chc chn rng FSM th hin ng qu trnh chuyn i
gia cc trng thi nh hin th trn cc n LED mu , v n to ra gi tr u ra chnh xc trn
LEDG0.
6. Cui cng, hy xem xt mt sa i ca m trng thi c a ra trong Bng 1. Khi mt FSM
c thc hin trong mt FPGA, mch thng c th c n gin ha nu tt c cc u ra flip
flop l 0 khi FSM trong trng thi reset. Cch tip cn ny l mt li th v cc flipflop ca FPGA

thng bao gm mt cng u vo r rng, c th c s dng mt cch thun tin xc nhn

trng thi reset, nhng cc flipflop thng khng bao gm mt cng u vo thit lp.
Bng 2 cho thy mt bng m trng thi thay i sao cho trng thi reset, A, s dng tt c cc s
0. iu ny c thc hin bng cch o ngc bin trng thi y0. To mt phin bn sa i ca
m Verilog bn vit s thc hin vic gn trng thi ny. (Gi : bn s cn phi thay i rt t trn
cc biu thc logic trong mch ca bn thc hin cc m sa i). Bin dch mch mi ca bn
v th nghim n thng qua m phng v bng cch np n vo Kit DE2.

Bng 2. M trng thi FSM thay i.

Phn II
Trong phn ny, bn s vit mt m Verilog cho FSM trong hnh 2 theo mt phong cch khc.
Trong phin bn ny ca m bn s khng ly bng tay cc biu thc logic cn thit cho mi flip
flop trng thi. Thay vo , m t cc bng trng thi cho FSM bng cch s dng biu thc case
Verilog trong mt khi always v s dng mt khi always khc khi to cc flipflop trng
thi. Bn c th s dng mt biu thc always th ba cc php gn n gin xc nh u ra z.
thc hin cc FSM, s dng bn flipflop trng thi y3, , y0 v cc m nh phn, nh th hin
trong Bng 3.

Bng 3. M nh phn cho FSM.

Mt b khung xng gi ca m Verilog c a ra trong hnh 3.
module part2 ();

 define input and output ports

define signals
reg [3:0] y_Q, Y_D; // y_Q represents current state, Y_D represents next state
parameter A = 4b0000, B = 4b0001, C = 4b0010, D = 4b0011, E = 4b0100,
F = 4b0101, G = 4b0110, H = 4b0111, I = 4b1000;
always @ (w, y_Q)
begin: state_table
case (y_Q)
A: if (!w) Y_D = B;
else Y_D = F;
remainder of state table
default: Y_D = 4bxxxx;
endcase
end // state_table
always @(posedge Clock)
begin: state_FFs

end // state_FFS
assignments for output z and the LEDs
endmodule
Hnh 3. Khung xng m Verilog cho FSM.
Thc hin mch ca bn nh sau.
1. To mt d n mi cho FSM. Chn chip mc tiu l Cyclone II EP2C35F672C6.
2. Thm vo trong d n ca bn tp tin Verilog s dng phong cch m trong hnh 3. S dng
cng tc SW0 trn Kit DE2 ca Altera lm u vo Reset ng b mc thp cho FSM, s dng
SW1 lm u vo w, v nt bm KEY0 lm u vo ng h iu khin bng tay. S dng n
LED mu xanh LEDG0 nh u ra z, v gn cc u ra flipflop trng thi vo cc n LED mu
LEDR3 LEDR0. Gn cc chn trn FPGA kt ni vi cc cng tc v cc n LED, nh
c ch ra trong Hng dn S dng cho Kit DE2.
3. Trc khi bin dch m ca bn, vic thng bo mt cch r rng cho cng c Synthesis trong
Quartus II rng, bn mun c cc my trng thi hu hn c thc hin bng cch s dng cc
php gn trng thi quy nh trong m Verilog ca bn, l rt cn thit. Nu bn khng a ra cc
thit lp ny mt cch r rng cho Quartus II, cng c Synthesis s t ng s dng mt php gn
trng thi theo cch la chn ca ring n, v n s b qua cc m trng thi c quy nh trong

m Verilog ca bn. thc hin cc thit lp ny, chn Assignments > Settings trong Quartus II,
v sau nhp vo mc Analysis and Synthesis pha bn tri ca ca s. Nh c ch ra trong
hnh 4, hy thay i tham s State Machine Processing thit lp UserEncoded.
4. kim tra mch c to ra bi Quartus II, m cng c RTL Viewer. Click p vo hp hin
th trong mch i din cho my trng thi hu hn, v xc nh xem s trng thi no m t
ng vi my trng thi trong hnh 2. xem cc m trng thi c s dng cho FSM ca bn,
m Compilation Report, chn phn Analysis and Synthesis bo co, v bm vo my trng thi.
5. M phng cc hnh vi ca mch ca bn.
6. Khi bn t tin rng mch hot ng ng nh kt qu m phng ca bn, np mch vo chip
FPGA. Kim tra chc nng ca thit k ca bn bng cch a cc chui u vo v quan st cc
n LED u ra. Hy chc chn rng cc FSM thc hin ng qu trnh chuyn i gia cc
trng thi nh hin th trn cc n LED mu , v to thnh gi tr u ra chnh xc trn LEDG0.
7. Trong bc 3, bn s hng dn cng c tng hp ca Quartus II s dng cc php gn trng
thi c a ra trong m Verilog ca bn. xem kt qu ca vic loi b cc ci t ny, m li
ca s ci t Quartus II bng cch chn Assignments > Settings, v bm vo mc Analysis and
Synthesis. Thay i cc thit lp cho State Machine Processing from UserEncoded sang OneHot.
Bin dch li mch v sau m tp tin bo co, chn phn Analysis and Synthesis ca bo co, v
bm vo State Machines. So snh vi cc m trng thi c a ra trong Bng 2, v tho lun v
bt k s khc bit no m bn quan st.

Hnh 4. Xc nh phng php gn trng thi trong Quartus II.

Phn III

i vi phn ny, bn s thc hin FSM pht hin tun t bng cch s dng cc thanh ghi dch,
thay v s dng cc phng php tip cn chnh thc m t trn. To m Verilog bao gm hai
thanh ghi dch 4bit, mt pht hin mt chui bn s 0, v mt pht hin chui bn s 1.
Thm biu thc logic thch hp vo trong thit k ca bn to thnh cc u ra z. To mt d n
Quartus II cho thit k ca bn v thc hin cc mch trn Kit DE2. S dng cc cng tc v n
LED trn Kit mt cch tng t nh Phn I v II v quan st hnh vi ca cc thanh ghi dch v u
ra z. Tr li cc cu hi sau y: bn c th s dng ch mt thanh ghi dch 4bit, thay v hai
khng? Gii thch cu tr li ca bn.

Phn IV

Chng ta mun thit k mt mch b m m un 10 hot ng nh sau: Mch c ti lp v mc

0 bng u vo Reset. Mch c hai u vo, w1 v w0, kim sot hot ng m ca n. Nu
w1w0 = 00, bin m c gi nguyn. Nu w1w0 = 01, bin m c tng thm 1. Nu w1w0 =
10, bin m c tng ln 2. Nu w1w0 = 11, bin m c gim i 1. Mi thay i s din ra
trn sn dng ca u vo xung ng h. S dng cc cng tc SW2 v SW1 cho u vo w1 v
w0. S dng chuyn i SW0 lm u vo Reset ng b mc thp, v s dng nt bm KEY0
lm u vo ng h iu khin bng tay. Hin th gi tr thp phn ca b m vo LED 7 thanh
HEX0.
1. To mt d n mi c s dng thc hin cc mch trn Kit DE2.
2. Vit mt tp tin Verilog nh ngha mch. S dng kiu m c ch ra trong Hnh 3 cho FSM
ca bn.
3. Thm tp tin Verilog vo trong d n ca bn v bin dch mch.
4. M phng hnh vi cho mch ca bn.
5. Gn chn trn FPGA kt ni vi cc cng tc v LED 7 thanh.
6. Bin dch li mch v np n vo chip FPGA.
7. Kim tra chc nng ca thit k ca bn bng cch a mt s gi tr u vo v quan st u ra.

Phn V

i vi phn ny, bn s thit k mt mch cho Kit DE2 c th cun t "HELLO" theo kiu ticker
tape trn 8 LED 7 thanh HEX7 0. Cc ch s di chuyn t phi sang tri mi khi c mt xung
ng h c iu khin bng tay. Sau khi t "HELLO" cun ra khi pha bn tri ca mn hnh,
n s bt u mt ln na pha bn phi.

Thit k mch ca bn bng cch s dng 8 thanh ghi 7bit ghp ni theo kiu ging nh hng i,
tc l kt qu u ra ca thanh ghi th nht s c cp cho u vo ca thanh ghi th hai, thanh
ghi th hai li cp cho thanh ghi th ba, v v.v... Loi kt ni gia thanh ghi nh th ny thng
c gi l mt ng ng. Cc kt qu u ra ca thanh ghi s c a trc tip LED 7 thanh.
Bn s thit k mt my hu hn trng thi kim sot cc ng ng theo hai cch:
1. i vi 8 xung ng h u tin sau khi h thng c thit lp li, FSM s chn ng cc k t
(H, E, L, L, 0,,,) vo thanh ghi 7bit u tin trong ng ng.
2. Sau khi hon tt bc 1, FSM thit lp cc ng ng dn vo trong mt vng lp kt ni thanh
ghi cui vi thanh ghi u tin, cc k t tip tc cun v thi hn.
Vit m Verilog cho mch tickertape v to ra mt d n Quartus II mi cho thit k ca bn. S
dng KEY0 trn Kit DE2 nh thi cho FSM v cc thanh ghi ng ng v s dng SW0 lm
mt u vo Reset ng b mc thp. Vit m Verilog theo phong cch trong hnh 3 cho my
trng thi hu hn ca bn.
Bin dch m Verilog ca bn, np vo Kit DE2 v kim tra mch.

Phn VI

i vi phn ny, bn s sa i mch t Phn V n khng cn phi c xung ng h iu

khin bng tay.
Mch ca bn s cun t "HELLO" sao cho cc ch di chuyn t phi sang tri trong khong thi
gian chng mt giy. Vic cun ch ny s din ra v thi hn, sau khi ch "HELLO" cun ra pha
bn tri ca mn hnh n s bt u mt ln na pha bn phi.
Vit Verilog m cho cc mch tickertape v to mi mt d n Quartus II cho thit k ca bn. S
dng tn hiu ng h 50MHz, CLOCK_50, trn Kit DE2 nh thi cho FSM v cc thanh ghi
ng ng, ng thi s dng KEY0 lm u vo Reset ng b mc thp. Vit m Verilog theo
phong cch trong hnh 3 cho my trng thi hu hn ca bn, v m bo rng tt c cc flipflops
trong mch c nh thi trc tip bng u vo CLOCK_50. ng s dng bt k tn hiu ng
h khc trong mch ca bn.
Bin dch m Verilog ca bn, np vo Kit DE2 v kim tra mch.

Phn VII

Ci thin thit k ca bn t Phn VI di s kim sot ca cc nt bm KEY2 v KEY1 sao cho

tc cc ch di chuyn t phi sang tri c th c thay i. Nu KEY1 c nhn, cc ch ci
s di chuyn nhanh gp 2 ln. Nu KEY2 c nhn, tc ny s c gim 2 ln.
Lu rng cc cng tc KEY2 v KEY1 c c nh v s to ra chnh xc mt xung mc thp
khi bm.

Tuy nhin, khng c cch no bit bao lu mt cng tc c th c gi mc thp, c ngha l

rng xung c th c ty tin. Mt cch tip cn tt thit k mch ny l thm mt FSM
th hai vo trong m Verilog sao cho n p ng ng vi cc phm bm. Cc kt qu u ra
ca FSM ny c th thay i mt cch thch hp khi mt phm c bm, v FSM c th ch i
cho mi phm bm kt thc trc khi tip tc. Cc kt qu u ra c to ra bi FSM th hai
c th c s dng nh mt phn ca chng trnh to ra mt khong thi gian bin thin
trong mch ca bn. Lu rng KEY 2 v KEY1 l cc u vo khng ng b trong mch, v vy
hy chc chn rng bn s ng b ha cc tn hiu ng h trc khi s dng nhng tn hiu u
ny trong my trng thi hu hn ca bn.
Cc bng ticker s hot ng nh sau. Khi mch c thit lp li, s di chuyn xy ra trong
khong 4 giy. Nhn KEY1 lp i lp li, nhm lm cho tc di chuyn tng gp i ln ti a l
16 ch ci trong mt giy.
Nhn KEY2 lp i lp li lm cho tc di chuyn chm li n mc ti thiu l mt ch ci trong
mot giy.
Thc hin mch ca bn trn Kit DE2 v chng minh rng n hot ng ng.

Bi th nghim 8
Cc b nh
Trong cc h thng my tnh, chng ta cn cung cp mt s lng ng k cc b nh. Nu h
thng c thc hin bng cch s dng cng ngh FPGA, chng ta c th cung cp mt s lng
cc b nh bng cch s dng cc ngun ti nguyn c sn trong cc thit b FPGA. Nu cn b
nh b sung, chng ta cn thc hin bng cch kt ni cc chip nh bn ngoi vi FPGA. Trong bi
th nghim ny, chng ta s xem xt cc vn chung lin quan n vic trin khai thc hin kiu
b nh trn.
Mt s ca mun b nh truy cp ngu nhin (RAM) chng ta s thc hin c th hin
trong Hnh 1a. N cha 32 s 8bit (hng), c truy cp bng cch s dng mt cng adress 5
bit, mt cng data 8bit v mt u vo iu khin write. Chng ta s xem xt hai cch khc nhau
thc hin b nh ny: s dng cc khi b nh chuyn dng trong mt thit b FPGA, v s
dng mt chip b nh ring bit.
FPGA Cyclone II 2C35 i km vi Kit DE2 cung cp ti nguyn b nh ring c gi l khi
M4K. Mi khi M4K cha 4096 bit b nh, c th c cu hnh thc hin nhng cc b nh
vi cc kch c khc nhau. Mt thut ng thng c s dng xc nh kch thc ca b nh
k trn l t s khun dng ca n, gm di ca s v rng bit (depth length). Mt s t s
khun dng c h tr bi khi M4K l 4K 1, 2K 2, 1K 4, v 512 8. Chng ta s s dng
kiu 512 8 trong bi th nghim ny, v ch s dng 32 t u tin trong b nh. Chng ta cng
nn ch n nhiu phng thc hot ng khc c h tr trong mt khi M4K, nhng chng ta
s khng tho lun v chng y.

(a) Cu trc RAM

(b) Thc hin RAM

Hnh 1. Mt mun RAM 32 8

C hai tnh nng quan trng ca khi M4K cn c ch ra n. u tin, n bao gm cc thanh
ghi c th c s dng ng b ha tt c cc tn hiu u vo v u ra theo mt u vo xung
ng h. Th hai, khi M4K c cc cng ring bit cho d liu c ghi vo trong b nh v d
liu c c ra t b nh. Mt yu cu khi s dng 1 khi M4K l mt trong hai cng, u vo v
u ra ca n, hoc c hai, phi c ng b vi mt u vo xung ng h. Vi cc yu cu ny,
chng ta s thc hin mt mun RAM 32 8 c th hin trong Hnh 1b. N bao gm cc
thanh ghi cho a ch address, nhp d liu data input, v cc cng ghi write, v s dng mt cng
d liu u ra data output ring bit khng phi l thanh ghi.
Phn I
Cc cu trc logic thng c s dng, chng hn nh cc b cng, cc thanh ghi, b m v cc
b nh c th c thc hin trong mt chip FPGA bng cch s dng cc mun LPM t Th
vin cc Module Tham s ha ca Quartus II. Altera khuyn co rng mt module b nh RAM
c thc hin bng cch s dng LPM altsyncram. Trong bi th nghim ny, bn s s dng
LPM ni trn thc hin cc mun b nh trong Hnh 1b.
1. To mt d n Quartus II thc hin cc mun b nh. Chn chip mc tiu l Cyclone II
EP2C35F672C6, l chip FPGA trn Kit DE2 ca Altera.
2. Bn c th tm hiu xem lm th no Plugin MegaWizard Manager c s dng to ra mt
mun LPM mong mun bng cch c hng dn S dng Cc Module c sn trong Th vin
trong Thit k Verilog. Hng dn ny c cung cp trong phn Chng trnh i hc trn trang
web ca Altera. Trong mn hnh u tin ca MegaWizard Plugin Manager, chn LPM
altsyncram, c tm thy trong mc storage. Nh c ch ra trong hnh 2, chn Verilog HDL l
loi tp tin u ra, v t tn cho n l ramlpm.v. Trn trang tip theo ca Wizard, ch nh kch
thc b nh ca 32 t 8bit, v chn M4K l loi RAM. Tin ti trang tip theo v chp nhn cc
thit lp mc nh s dng mt xung ng h duy nht cho cc thanh ghi ca RAM, sau tin
mt ln na thy trang c biu din trong hnh 3. trang ny, b chn thit lp c gi l
Read output port(s) trong mc Which ports should be registered? Thit lp ny to ra mt module
RAM ph hp vi cu trc trong Hnh 1b, vi cc cng u vo l thanh ghi v cc cng u ra
khng phi l thanh ghi. Chp nhn cc gi tr mc nh cho cc phn cn li ca cc thit lp trong
trnh thut s, v sau khi to trong tp tin Verilog cp cao nht ca bn module c to ra
trong ramlpm.v. Thm cc u vo v cc tn hiu u ra thch hp vo trong m Verilog ca bn
cho cc cng b nh c cho trong Hnh 1b.

Hnh 2. Chn LPM altsyncram.

Hnh 3. Cu hnh cc cng u vo v u ra trn LPM altsyncram.

3. Bin dch mch. Quan st trong Compilation Report ca Quartus II rng n s dng 256 bit mt
lc trong cc khi b nh M4K thc hin cc mch RAM.
4. M phng cc hnh vi ca mch ca bn v m bo rng bn c th c v ghi d liu trong b
nh.
Phn II
By gi, chng ta mun thc hin cc mch b nh trong FPGA trn Kit DE2, v s dng cc cng
tc gt ti mt s d liu vo b nh c to ra. Chng ta cng mun hin th cc ni dung ca
RAM trn cc LED 7 thanh.
1. Thc hin mt d n Quartus II mi s c s dng thc hin cc mch mong mun trn Kit
DE2.
2. To mt file Verilog bao gm module ramlpm, cc u vo v cc chn u ra yu cu trn Kit
DE2. S dng cc cng tc SW70 nhp vo mt byte d liu vo v tr RAM c xc nh
bng mt a ch 5bit quy nh vi cc cng tc SW1511. S dng SW17 lm tn hiu Write v
s dng KEY0 lm u vo Clock. Hin th gi tr ca tn hiu Write ln LEDG0. Hin th cc gi
tr a ch trn cc LED 7 thanh HEX7 v HEX6, hin th cc d liu u vo a n b nh trn
HEX5 v HEX4, v hin th cc d liu c ra ca b nh trn HEX1 v HEX0.
3. Kim tra mch ca bn v m bo rng tt c 32 a ch u c th c np ng cch.
Phn III
Thay v trc tip s dng module LPM, chng ta c th thc hin b nh cn thit bng cch xc
nh cu trc ca n trong m Verilog. Trong mt thit k Verilog xc nh, chng ta c th nh
ngha b nh nh l mt mng a chiu. Mt mng 32 8, trong c 32 s vi 8 bit cho mi s,
c th c khai bo bng cch biu thc
reg [7:0] memory_array [31:0];
Trong FPGA Cyclone II, mt mng nh vy c th c thc hin hoc bng cch s dng cc
flipflops m mi phn t logic u c cha, hoc hiu qu hn, bng cch s dng cc khi M4K.
C hai cch m bo rng cc khi M4K s c s dng. Mt l s dng mt mun LPM t
Th vin cc Module Tham s ha, nh chng ta thy trong phn I. Cc khc l xc nh yu
cu b nh bng cch s dng mt kiu m Verilog ph hp t cc trnh bin dch Quartus II
c th suy ra rng mt khi b nh s c s dng. Phn Tr gip ca Quartus II s cho cc bn
thy lm th no iu ny c th c thc hin vi cc v d v m Verilog (tm kim trong Tr
gip vi t kha " Inferred memory").
Thc hin cc bc sau y:
1. To mt d n mi s c s dng thc hin cc mch mong mun trn Kit DE2.
2. Vit mt tp tin Verilog cung cp cc chc nng cn thit, bao gm kh nng ti b nh RAM
v c ni dung ca n nh thc hin Phn II.
3. Gn cc chn trn FPGA kt ni vi cc cng tc v cc LED 7 thanh.
4. Bin dch mch v np n vo chip FPGA.
5. Kim tra chc nng ca thit k ca bn bng cch to ra mt s u vo v quan st u ra. M
t bt k s khc bit no bn quan st c so vi mch t Phn II.

Phn IV
Kit DE2 bao gm mt chip SRAM, c gi l IS61LV25616AL10, l mt b nh RAM tnh
c dung lng 256K s 16bit. Giao din SRAM bao gm mt cng a ch 18bit, A170, v mt
cng d liu hai chiu 16bit, I/O150. N cng c mt s u vo iu khin, CE, OE, WE, UB, v
LB, c m t trong Bng 1.
Tn
CE
OE
WE
UB
LB

Mc ch
Chip Enabled mc thp trong sut qu trnh hot ng ca SRAM
Output Enable c th mc thp ch trong sut qu trnh c, hoc tt c cc qu trnh
Write Enable mc thp trong sut qu trnh ghi
Upper Byte mc thp khi c hoc ghi cc byte cao ca mt a ch
Lower Byte mc thp khi c hoc ghi cc byte thp ca mt a ch
Bng 1. Cc u vo iu khin ca SRAM

Cc hot ng ca chip IS61LV25616AL c m t trong datasheet ca n, c sn trong CD DE2

System i km vi Kit DE2, hoc tm kim trn Internet. Datasheet m t mt s phng thc hot
ng ca b nh v lit k cc thng s thi gian lin quan n vic s dng ca n. i vi mc
ch ca bi th nghim ny, mt ch hot ng n gin, l lun lun t mc thp (thit
lp v 0) cc u vo iu khin CE, OE, UB, v LB, v sau l iu khin vic c v ghi ca b
nh bng cch ch s dng u vo WE. Biu thi gian n gin ha tng ng vi ch ny
c a ra trong hnh 4. Phn (a) cho thy mt chu k c, bt u t khi mt a ch hp l xut
hin trn A170 v u vo WE cha mc thp. B nh t d liu hp l trn cc cng I/O150
sau tr truy cp a ch (address access delay), tAA. Khi kt thc chu k c, do s thay i
trong gi tr a ch, d liu u ra vn cn gi tr trong thi gian lu gi u ra (output hold time),
tOHA.

(A) Chu k c ca SRAM

(B) Chu k ghi ca SRAM

Hnh 4. Chu k c v ghi ca SRAM.

Hnh 4b a ra thi gian cho mt chu k ghi. N bt u khi WE c thit lp l 0, v n kt thc

khi WE c thit lp tr li 1. a ch ny cn phi c gi tr trong thi gian thit lp a ch
(address setup time), tAW, v cc d liu c ghi cn phi c gi tr trong khong thi gian thit
lp d liu (data setup time), tSD, trc sn ln ca WE. Bng 2 lit k cc gi tr ti thiu v ti
a ca tt c cc thng s thi gian th hin trong hnh 4.
Thng s
tAA
tOHA
tAW
tSD
tHA
tSA
tHD

Gi tr
Min Max
10 ns
3 ns

8 ns

6 ns

Bng 2. SRAM thi gian tham s gi tr.

Bn ang thc hin b nh 32 8 trong Hnh 1a bng cch s dng chip SRAM. Vic thm vo
trong thit k ca bn cc thanh ghi c hin th trong Hnh 1b l mt cch tip cn tt, thng qua
vic s dng cc thanh ghi trong chip FPGA. Hy cn thn s dng ng cc cng d liu hai
chiu kt ni vi b nh.
1. To mt d n Quartus II mi cho mch ca bn. Vit mt tp tin Verilog cung cp cc chc
nng cn thit, bao gm kh nng ti cc b nh v c ni dung ca n. S dng cc cng tc, n
LED, v LED 7 thanh trn Kit DE2 tng t nh phn II v III, ng thi s dng cc tn chn ca
SRAM c hin th trong Bng 3 giao tip mch ca bn vi chip IS61LV25616AL (cc tn
chn ca SRAM cng c a ra trong Hng dn S dng DE2).
Lu rng bn s khng s dng tt c cc cng a ch v d liu trn chip IS61LV25616AL cho
b nh ca 32 8 ca bn, kt ni cc cng khng cn thit vi 0 trong module Verilog ca bn.
Tn cng SRAM
A170
I/O150
CE
OE
WE
UB
LB

Tn chn trn DE2

SRAM_ADDR170
SRAM_DQ150
SRAM_CE_N
SRAM_OE_N
SRAM_WE_N
SRAM_UB_N
SRAM_LB_N

Bng 3. DE2 tn pin cho cc chip SRAM.

2. Bin dch mch v np vo chip FPGA.
3. Kim tra cc chc nng ca thit k ca bn bng cch c v ghi cc gi tr cho mt s v tr
khc nhau trong b nh.
Phn V
Khi SRAM trong hnh 1 c mt cng duy nht cung cp a ch cho c c v ghi. Trong phn
ny, bn s to ra mt loi khc nhau ca cc mun b nh, trong c mt cng cung cp
a ch cho mt hot ng c, v mt cng ring bit m cung cp cho cc a ch cho mt hot
ng ghi. Thc hin cc bc sau y.

1. To mt d n Quartus II mi cho mch ca bn. to ra cc mun b nh mong mun, m

MegaWizard PlugManager v chn li LPM altsyncram trong mc Storage. Trong trang 1 ca
Wizard, chn thit lpWith one read port and one write port (simple dualport mode) trong mc
How will you be using the altsyncram?. Tip tc t trang 2 n 5 v thip lp cc la chn tng t
nh trong phn II. Trang 6, chn thit lp I don't care trong mc Mixed Port ReadDuringWrite
for Single Input Clock RAM. Thit lp ny xc nh rng khng quan trng xem d liu u ra mi
c ghi vo hay d liu c c lu tr t trc , trong trng hp ny, cc a ch ghi v c
u ging nhau.
Trang 7 ca Wizard c biu din trong hnh 5. N s s dng mt tnh nng cho php mun
b nh c np vi cc d liu ban u khi mch c lp trnh vo chip FPGA. Nh biu din
trn hnh, chn thit lp Yes, use this file for the memory content data v ch nh tn tp tin l
ramlpm.mif.
tm hiu v nh dng ca mt tp tin khi to b nh (MIF memory initialization file), xem
Tr gip ca Quartus II. Bn s cn phi to ra tp tin ny v ch nh mt s gi tr d liu c
lu tr trong b nh. Kt thc Wizard v sau kim tra cc mun b nh c to ra trong tp
tin ramlpm.v.

Hnh 5. Ch nh mt tp tin khi to b nh (MIF).

2. Vit mt tp tin Verilog thc thi b nh dualport ca bn. xem ni dung ca RAM, thm
vo thit k ca bn kh nng hin th ni dung ca mi byte ( nh dng thp lc phn) trn LED
7 thanh HEX1 v HEX0. Di chuyn qua cc v tr b nh bng cch hin th mi byte trong khong
mt giy. Trong lc mi byte ang c hin th, hy hin th a ch ca n (di dng thp lc
phn) trn LED 7 thanh HEX3 v HEX2. S dng ng h 50 MHz, CLOCK_50, trn Kit DE2, v
s dng KEY0 lm u vo Reset. i vi a ch ghi v d liu tng ng, s dng cc cng tc,
n LED, v LED 7 thanh tng t nh trong cc phn trc ca bi th nghim ny. Hy chc
chn rng bn ng b ha ng cc cng tc u vo vi tn hiu ng h 50 MHz.
3. Kim tra mch ca bn v xc minh rng cc ni dung ban u ca b nh ph hp vi tp tin
ramlpm.mif. Hy chc chn rng bn c th ghi d liu mt cch c lp n bt k a ch no
bng cch s dng cc cng tc.

Phn VI
Cc b nh dualport c to ra trong Phn V cho php ng thi cc hot ng c v ghi xy
ra, bi n c hai cng a ch. Trong phn ny ca bi th nghim, bn s to ra kh nng tng t,
nhng bng cch s dng mt b nh RAM mt cng.
V s c ch c mt a ch cng, bn s cn phi ghp knh chn mt a ch c hoc ghi ti
bt k mt thi gian c th no. Thc hin cc bc sau y.
1. To mt d n Quartus II mi cho mch ca bn, v s dng MegaWizard Plugin Manager
to ra mt phin bn singleport cho LPM altsyncram. T trang 1 ti 6 ca Wizard, s dng cc
thit lp tng t nh Phn I. Trong Page 7, biu din trong hnh 6, xc nh tp tin ramlpm.mif
bn to ra trong phn V, song chn thm thit lp Allow InSystem Memory Content Editor to
capture and update content independently of the system clock. Ty chn ny cho php bn s dng
mt tnh nng ca h thng CAD ca Quartus II c gi l InSystem Memory Content Editor
xem v thao tc trn cc ni dung ca module b nh RAM c to ra. Khi s dng cng c ny,
bn c th ch nh 'Instances ID' gm bn k t vi cng dng nh mt ci tn cho b nh. Trong
hnh 7, chng ta a ra tn cho mun b nh RAM l 32x8. Hon tt cc bc cui cng
trong Wizard.

Hnh 6. Cu hnh altsyncram s dng vi cc bin tp ni dung b nh trong h thng.

2. Vit mt tp tin Verilog thc thi module b nh ca bn. Thm vo trong thit k ca bn kh
nng di chuyn qua cc v tr b nh nh trong Phn V. S dng cc cng tc, n LED, LED 7
thanh tng t nh bn lm trc y.
3. Trc khi bn c th s dng cng c InSystem Memory Content Editor, thm mt thit lp
c thc hin. Trong phn mm Quartus II, chn Assignments > Settings m ca s trong hnh
7, v sau m Default Parameters trong Analysis and Synthesis Settings. Nh biu din trong
hnh, g tn tham s CYCLONEII_SAFE_WRITE v ch nh gi tr RESTRUCTURE. Tham s
ny cho php cc cng c tng hp ca Quartus II sa i b nh RAM singleport theo yu cu
nhm cho php hot ng c v ghi ca b nh bng cng c InSystem Memory Content Editor.
Click vo OK thot khi ca s Settings.

Hnh 7. Thit lp tham s CYCLONEII_SAFE_WRITE.

4. Bin dch m ca bn v np vo Kit DE2. Kim tra hot ng ca mch v chc chn rng cc
qu trnh c v ghi cc din ra ng cch. M t bt k s khc bit no bn quan st c t cc
hnh vi ca mch so vi Phn V.
5. Chn Tools > InSystem Memory Content Editor, m ca s trong hnh 8. xc nh cc kt
ni vi Kit DE2 ca bn, nhp chut vo nt Setup pha trn bn phi ca mn hnh. Trong ca
s trong hnh 9, chn phn cng USBBlaster, v sau ng hp thoi Hardware Setup.

Hnh 8. Ca s InSystem Memory Content Editor

Hnh 9. Ca s Hardware Setup

Hng dn cho vic s dng cng c InSystem Memory Content Editor c th c tm thy
trong Tr gip Quartus II Help.
Th nghim bng cch thay i mt s gi tr b nh v quan st xem d liu c c hin th ng
trn c 2 LED 7 thanh ca Kit DE2 v trong ca s b nh trong ca s InSystem Memory
Content Editor khng.

Hnh 10. S dng cng c InSystem Memory Content Editor.

Bi th nghim 9
Mt b x l n gin
Hnh 1 biu din mt h thng s c cha mt s lng thanh ghi 16bit, mt b ghp knh, mt
khi cng / tr, mt b m mt, v mt khi iu khin. D liu l u vo cho h thng ny
thng qua cc u vo DIN 16bit. D liu ny c th c ti thng qua cc b ghp knh rng
16bit vo cc thanh ghi khc nhau, chng hn nh R0,, R7 v A. B ghp knh cng cho php
d liu c chuyn t thanh ghi ny sang thanh ghi khc. Dy u ra ca b ghp knh c gi
l bus trong hnh bi thut ng ny thng c s dng cho cc dy cho php d liu c truyn
i t v tr ny sang v tr khc trong h thng.
Php cng hoc tr c thc hin bng cch s dng b ghp knh. u tin mt s 16bit c
a ln bus v sau c np vo thanh ghi A. Sau khi iu ny c thc hin, s 16bit th hai
c a ln bus, khi cng / tr s thc hin cc php ton theo yu cu cn thit, v kt qu c
np vo thanh ghi G. Cc d liu trong G sau c th c chuyn ti mt thanh ghi khc theo
yu cu.

Hnh 1. Mt h thng s.
H thng c th thc hin cc hot ng khc nhau trong mi chu k ng h, chi phi bi khi
iu khin. Khi ny xc nh khi no cc d liu c th c t vo bus v iu khin thanh ghi
no c np d liu ny. V d, nu khi iu khin xc lp tn hiu R0out v Ain, b ghp knh

s a ni dung ca thanh ghi R0 ln bus v d liu ny s c np vo thanh ghi A bi sn ln

ca xung ng h tip theo.
Mt h thng nh th ny thng c gi l mt b x l. N thc hin cc hot ng xc nh
theo kiu cc cu lnh.
Bng 1 lit k cc cu lnh b x l h tr cho bi th nghim ny ny. Ct bn tri biu din tn
ca mt ton t v ton hng ca n. ngha ca c php RX [RY] l cc ni dung ca thanh
ghi RY c np vo thanh ghi RX. Cu lnh mv (move) cho php d liu c sao chp t thanh
ghi ny sang thanh ghi khc. i vi cu lnh mvi (move immediate), biu thc RX D ch ra
rng hng s 16bit D lin tc c np vo thanh ghi RX.
Ton t

Chc nng thc hin

mv Rx, Ry Rx [Ry]
mvi Rx, #D

Rx D

add Rx, Ry

Rx [Rx] + [Ry]

sub Rx, Ry

Rx [Rx] [Ry]

Bng 1. Cc cu lnh c thc hin trong b x l.

Each instruction can be encoded and stored in the IR register using the 9bit format IIIXXXYYY,
where III represents the instruction, XXX gives the RX register, and YYY gives the RY register.
Although only two bits are needed to encode our four instructions, we are using three bits because
other instructions will be added to the processor in later parts of this exercise. Hence IR has to be
connected to nine bits of the 16bit DIN input, as indicated in Figure 1. For the mvi instruction the
YYY field has no meaning, and the immediate data #D has to be supplied on the 16bit DIN input
after the mvi instruction word is stored into IR.
Mi cu lnh c th c m ha v c lu tr trong thanh ghi IR bng cch s dng nh dng
9bit IIIXXXYYY, III i din cho cc cu lnh, XXX cho thanh ghi RX, v YYY cho thanh ghi
RY. Mc d ch c hai bit cn thit m ha 4 cu lnh, song chng ta ang s dng ba bit bi
cc cu lnh khc s c thm vo b x l trong cc phn sau ca bi tp ny. Do IR c kt
ni vi chn bit ca u vo DIN 16bit, nh c ch ra trong hnh 1. i vi cu lnh mvi, on
YYY khng c ngha, v d liu tc thi #D s c cp trn u vo DIN 16bit sau khi t cu
lnh mvi c lu tr vo IR.
Mt s cu lnh, chng hn nh mt cng hoc tr, mt nhiu hn mt chu k xung ng h
hon thnh, v nhiu qu trnh vn chuyn phi c thc hin thng qua bus. B iu khin s
dng b m haibit biu din hin trong hnh 1 nhm cho php n "bc qua" cc cu lnh nh
vy. B x l bt u thc hin cc cu lnh trn u vo DIN khi c tn hiu Run v b x l xc
lp u ra Done khi cu lnh thc hin xong. Bng 2 cho thy cc tn hiu iu khin c th c
xc lp trong mi chu k thi gian thc hin cc cu lnh trong Bng 1. Lu rng tn hiu iu
khin duy nht xc lp trong chu k thi gian 0 l IRin, do , chu k thi gian ny khng c
hin th trong bng.

Bng 2. Tn hiu iu khin xc lp trong tng cu lnh / chu k thi gian.

Phn I
Thit k v thc hin cc b x l c biu din trong hnh 1 s dng m Verilog nh sau:
1. To mt d n Quartus II mi cho bi th nghim ny.
2. To ra cc file Verilog cn thit, thm vo trong d n ca bn, v bin dch mch. Mt b
xng ngh ca m Verilog c biu din trn hnh 2a, v mt s mun mch ph c th
c s dng trong m ny xut hin trong hnh 2b.
3. S dng m phng chc nng xc minh rng m ca bn chnh xc. Mt v d v u ra c
to bi mt m phng chc nng cho mt mch c thit k chnh xc c a ra trong hnh 3.
N cho thy gi tr (2000) 16 c np vo IR t DIN lc 30 ns. M hnh ny i din cho cu lnh
mvi R0, #D, ni gi tr D = 5 c np vo R0 trn sn xung ng h ti 50 ns. M phng sau
s biu din cu lnh mv R1, R0 90 ns, add R0, R1 110 ns, v sub R0, R0 190 ns. Lu rng
u ra ca m phng cho thy DIN di dng s thp lc phn 4ch s, v n cho thy ni dung
ca IR nh mt s bt phn 3ch s.
4. To mt d n Quartus II mi c s dng thc hin mch trn Kit DE2 ca Altera. D n
ny bao gm mt mun cp cao nht c cha cc cng u vo v u ra ph hp cho Kit DE2.
Khi to b x l ca bn trong mun cp cao nht ny. S dng cc cng tc SW 150 iu
khin cng u vo DIN ca b x l v s dng cng tc SW17 iu khin u vo Run. Ngoi
ra, s dng nt bm KEY0 cho Resetn v KEY1 cho Clock. Kt ni cc bus ca b x l n
LEDR150 v kt ni tn hiu Done n LEDR17.
5. Thm vo d n ca bn cc php gn chn cn thit cho Ban DE2. Bin dch mch v np n
vo chip FPGA.
6. Kim tra chc nng ca thit k bn va to bng cch gt cc cng tc v quan st cc n
LED. Do u vo xung ng h ca b x l c iu khin bi mt cng tc bm, vic thc hin
cc cu lnh v quan st hnh vi ca mch s rt d dng.
module proc (DIN, Resetn, Clock, Run, Done, BusWires);
input [15:0] DIN;
input Resetn, Clock, Run;
output Done;
output [15:0] BusWires;
declare variables

wire Clear =
upcount Tstep (Clear, Clock, Tstep_Q);
assign I = IR[1:3];
dec3to8 decX (IR[4:6], 1b1, Xreg);
dec3to8 decY (IR[7:9], 1b1, Yreg);
always @(Tstep_Q or I or Xreg or Yreg)
begin
specify initial values
case (Tstep_Q)
2b00: // store DIN in IR in time step 0
begin
IRin = 1b1;
end
2b01: //define signals in time step 1
case (I)

endcase
2b10: //define signals in time step 2
case (I)

endcase
2b11: //define signals in time step 3
case (I)

endcase
endcase
end
regn reg_0 (BusWires, Rin[0], Clock, R0);
instantiate other registers and the adder/subtracter unit
define the bus
endmodule
Hnh 2a. Khung xng m Verilog cho b x l
module upcount(Clear, Clock, Q);
input Clear, Clock;
output [1:0] Q;
reg [1:0] Q;
always @(posedge Clock)

if (Clear)
Q <= 2b0;
else
Q <= Q + 1b1;
endmodule
module dec3to8(W, En, Y);
input [2:0]W;
input En;
output [0:7] Y;
reg [0:7] Y;
always @(W or En)
begin
if (En == 1)
case (W)
3b000: Y = 8b10000000;
3b001: Y = 8b01000000;
3b010: Y = 8b00100000;
3b011: Y = 8b00010000;
3b100: Y = 8b00001000;
3b101: Y = 8b00000100;
3b110: Y = 8b00000010;
3b111: Y = 8b00000001;
endcase
else
Y = 8b00000000;
end
endmodule
module regn(R, Rin, Clock, Q);
parameter n = 16;
input [n1:0] R;
input Rin, Clock;
output [n1:0] Q;
reg [n1:0] Q;
always @(posedge Clock)
if (Rin)

Q <= R;
endmodule
Hnh 2b. Cc mun mch ph c s dng trong b x l

Figure 3. Simulation of the processor.

Phn II

Trong phn ny, bn s thit k mch c m t trong hnh 4, trong c mt module b nh v

b m c kt ni vi cc b x l t phn I. Phn b m c s dng c ni dung trong
cc a ch lin tip ca b nh, v d liu ny c cung cp ti b x l nh mt lung cc cu
lnh. n gin ha vic thit k v th nghim ca mch ny, chng ta s dng tn hiu ng
h ring bit, PClock v MClock, cho b x l v b nh.

Hnh 4. Kt ni b x l vi b nh v b m.
1. To mt d n Quartus II mi c s dng kim tra mch ca bn.

2. To ra mt tp tin Verilog cp cao nht thc thi cc b x l, b nh, v b m. S dng cng

c MegaWizard PlugIn Manager ca Quartus II to ra cc mun b nh t Th vin M
un Tham s ha (LPMs) ca Altera. LPM cn thit c tm thy trong mc Storage v c gi
l ALTSYNCRAM. i theo cc cu lnh c cung cp bi Wizard to ra mt b nh c mt
cng c d liu rng 16bit v cha c 32 s. Mn hnh u tin ca Wizard c biu din
trong hnh 5. Do b nh ny ch c mt cng c, v khng c cng ghi, n c gi l b nh ch
c ng b (ROM ng b). Lu rng b nh bao gm mt thanh ghi cho vic ti cc a ch
ng b. Thanh ghi ny l cn thit do thit k ca cc ngun ti nguyn b nh trn FPGA
Cyclone II, tnh ton cho vic nh thi ca thanh ghi a ch ny trong thit k ca bn.
t cu lnh ca b x l vo b nh, bn cn phi xc nh gi tr khi to s c lu tr
trong b nh mt khi mch ca bn c lp trnh vo chip FPGA. iu ny c th c thc
hin bng cch thit lp Wizard nhm khi to b nh bng cch s dng ni dung ca mt tp tin
khi to b nh (MIF). Mn hnh thch hp ca cng c MegaWizard PlugIn Manager c minh
ha trong hnh 6. Chng ta xc nh mt tp tin c tn l inst_mem.mif, tp tin ny sau cn
c to ra trong th mc c cha d n Quartus II. S dng Quartus II online Help tm hiu
nh dng ca file MIF v to ra mt tp tin c cc cu lnh x l kim tra mch ca bn.
3. S dng m phng chc nng kim tra mch. m bo rng d liu c c ra t ROM v
c thc thi bi b x l mt cch chnh xc.
4. Hy chc chn rng d n ca bn bao gm cc tn cng v cc php gn chn cn thit thc
hin mch trn Kit DE2. S dng cng tc SW17 iu khin u vo Run ca b x l, s dng
KEY0 cho Resetn, s dng KEY1 cho MClock, v s dng KEY2 cho PClock. Kt ni cc bus ca
b x l n LEDR150 v kt ni tn hiu Done n LEDR17.
5. Bin dch mch v np vo chip FPGA.
6. Kim tra cc chc nng ca thit k ca bn bng cch gt cc cng tc v quan st cc n
LED. Do cc u vo ng h ca mch c iu khin bng cc cng tc bm, vic thc hin cc
cu lnh v quan st hnh vi ca cc mch s rt d dng.

Hnh 5. Cu hnh ALTSYNCRAM.

Hnh 6. Ch nh mt tp tin khi to b nh (MIF).

B x l nng cao
Chng ta hon ton c th nng cao kh nng ca b x l sao cho b m trong Hnh 4 khng cn
cn thit na, v do b x l c th c v ghi bng cch s dng cc b nh hoc thit b khc.
Nhng ci tin lin quan n vic thm cc cu lnh mi cho cc b x l v cc chng trnh sao
cho b x l c th thc hin do s phc tp hn. Do cc bc ny vt qu phm vi ca mt s
kha hc thit k logic, chng s c m t trong bi th nghim tip theo c sn t Altera.

Bi th nghim 10
B x l nng cao
Trong Bi th nghim 9, chng ta m t mt b x l n gin. phn I ca bi th nghim
trc, b x l c thit k, v trong phn II b x l c kt ni vi mt b m bn ngoi
v mt khi b nh. Bi th nghim ny m t cc phn tip theo ca vic thit k b x l. Lu
rng vic nh s cc hnh nh v bng biu trong bi tp ny c tip tc t Phn I v II ca bi
th nghim trc .
Phn III
Trong phn ny, bn s m rng kh nng ca b x l b m bn ngoi khng cn cn thit
na, v b x l c kh nng c v ghi bng cch s dng b nh hoc cc thit b khc. Bn s
thm 3 tp lnh mi cho b x l, nh biu din trong Bng 3. Cu lnh ld (load) ti d liu vo
thanh ghi RX t b nh bn ngoi c quy nh qua a ch cung cp t trong thanh ghi RY. Cu
lnh st (store) lu tr cc d liu cha trong thanh ghi RX vo b nh ngoi qua a ch c tm
thy trong thanh ghi RY. Cui cng, lnh mvnz (move if not zero) cho php mt lnh mv c
thc hin ch khi no ni dung hin thi ca thanh ghi G khng phi l bng 0.
Ton t
ld Rx, [Ry]

Chc nng thc hin

Rx [[Ry]]

st Rx, [Ry] [Ry] [Rx]

mvnz Rx, Ry if G != 0, Rx [Ry]
Bng 1. Cc cu lnh mi c thc hin trong b x l
Mt s mch ca b x l nng cao c a ra trong hnh 7. Trong hnh ny, cc thanh ghi t
R0 n R6 ging nh trong hnh 1 ca Bi th nghim 9, nhng thanh ghi R7 c i thnh mt
b m. B m ny c s dng cung cp cc a ch trong b nh, t cc cu lnh ca
b x l c c ra; trong bi th nghim trc, mt b m ngoi c s dng cho mc ch
ny. Chng ta s tham chiu R7 lm b m chng trnh ca b x l (PC), bi v thut ng ny
c dng chung cho cc b x l c sn trong ngnh cng nghip thc s. Khi b x l c thit
lp li, PC c thit lp v a ch 0. Ti im bt u ca mi lnh (trong chu k thi gian 0), ni
dung ca PC c s dng nh mt a ch c mt lnh t b nh. Cu lnh c lu trong IR
v PC s t ng tng ln tr n lnh k tip (trong trng hp ca mvi, PC cung cp a ch
ca d liu tc thi v sau li tng ln mt ln na).
Khi iu khin ca b x l tng PC bng cch s dng tn hiu incr_PC, y ch l mt tn hiu
kch hot trn b m ny.
Chng ta cng c th trc tip ti mt a ch vo PC (R7) bng cch yu cu b x l thc hin
mt cu lnh mv hoc mvi trong thanh ghi ch c quy nh l R7. Trong trng hp ny,
khi kim sot s dng tn hiu R7in thc hin qu trnh ti song song ca b m. Bng cch
ny, cc b x l c th thc hin cu lnh ti bt k a ch no trong b nh, tri ngc vi cch
ch c th thc hin c cc cu lnh c lu tr trong cc a ch lin tip. Tng t nh vy,
ni dung hin thi ca PC c th c sao chp vo thanh ghi khc bng cch s dng mt cu
lnh mv. Mt v d v m c s dng cc thanh ghi PC thc hin mt vng lp c biu din
di y, ti cc on vn bn sau du % trn mi dng ch l li nhn xt. Cc cu lnh mv
R5, R7 t vo R5 a ch trong b nh ca cu lnh sub R4, R2. Sau , cu lnh mvnz R7, R5

khin cu lnh sub s c thc hin lin tc cho n khi R4 cn bng 0. Loi vng lp ny c th
c s dng trong mt chng trnh ln nh l mt cch to ra tr.
mvi R2, #1
mvi R4, #10000000 % binary delay value
mv R5, R7

% save address of next instruction

sub R4, R2

% decrement delay count

mvnz R7, R5

% continue subtracting until delay count gets to 0

Hnh 7. Phin bn nng cao ca b x l.

Hnh 7 biu din hai thanh ghi trong b x l c s dng truyn d liu. Thanh ghi ADDR
c s dng gi a ch n mt thit b bn ngoi, chng hn nh l mt module b nh, v
thanh ghi DOUT c s dng bi b x l cung cp d liu c th c lu tr bn ngoi b
x l. Mt cng dng ca thanh ghi ADDR l c, hoc ly, cc lnh t b nh, khi b x l mun
ly mt cu lnh, ni dung ca PC (R7) c a ln bus v np vo ADDR. a ch ny c
cung cp cho b nh. Ngoi vic ly ra cc cu lnh, cc b x l c th c d liu ti bt k a
ch no bng cch s dng thanh ghi ADDR. C d liu v cc cu lnh c c vo b x l trn
cng u vo DIN. B x l c th ghi d liu cho vic lu tr ti mt a ch bn ngoi bng cch
t a ch ny vo thanh ghi ADDR, t cc d liu c lu tr vo thanh ghi DOUT ca n, v
xc lp u ra ca flopflip W (write) v 1.
Hnh 8 minh ha cch b x l nng cao c kt ni vi b nh v cc thit b khc. Cc khi b
nh trong hnh h tr c hai qu trnh c v ghi, do n c c cc u vo a ch v d liu,
cng nh mt u vo cho php vit. B nh cng c mt u vo xung ng h, bi a ch, d
liu, v u cho php vit vo phi c np vo b nh trn sn dng ca xung ng h. Kiu
b nh ny thng c gi l b nh truy cp ngu nhin mt cch ng b (RAM ng b).
Hnh 8 cng bao gm mt thanh ghi 16bit c th c s dng lu tr d liu t b x l,
thanh ghi ny c th c kt ni vi mt b n LED cho php hin th d liu trn Kit DE2.
cho php b x l la chn mt trong hai khi b nh hoc thanh ghi khi thc hin mt qu trnh
vit, mch s bao gm mt s cng logic thc hin vic gii m a ch: nu cc dng a ch trn l
A15A14A13A12 = 0000, sau mun b nh s c vit ti a ch cho trn cc dng a ch
thp hn. Hnh 8 cho thy n dng a ch thp c kt ni vi b nh, trong bi tp ny mt b
nh vi 128 l tng i , vi ng rng n = 7 v cng a ch b nh c iu khin bi A6
A0. i vi cc a ch trong A15A14A13A12 = 0001, cc d liu c vit ca b x l
c np vo thanh ghi c kt qu u ra c gi l LEDs trong hnh 8.

Hnh 8. Kt ni cc b x l nng cao ti mt b nh v thanh ghi u ra.

1. To mt d n Quartus II mi cho phin bn nng cao ca b x l.
2. Vit m Verilog cho b x l v kim tra mch ca bn bng cch s dng m phng chc nng:
p dng cc cu lnh cho cng DIN v quan st cc tn hiu trong ca b x l khi cc cu lnh
c thc hin. Ch n vic nh thi ca cc tn hiu gia b x l v b nh bn ngoi; nh
ton trong thc t khi b nh c cc cng u vo l thanh ghi, nh tho lun trong Hnh 8.
3. To mt d n Quartus II khc khi to cc b x l, mun b nh, v thanh ghi biu din
trong hnh 8. S dng cng c MegaWizard PlugIn Manager ca Quartus II to ra mun b
nh ALTSYNCRAM.
i theo cc cu lnh c cung cp bi Wizard to ra mt b nh c mt cng c / ghi d liu
rng 16bit v di 128 s. S dng mt tp tin MIF lu tr cc cu lnh trong b nh c thc
hin bi b x l ca bn.
5. Include in your project the necessary pin assignments to implement your circuit on the DE2
board. Use switch SW17 to drive the processors Run input, use KEY0 for Resetn, and use the
boards 50 MHz clock signal as the Clock input. Since the circuit needs to run properly at 50 MHz,
make sure that a timing constraint is set in Quartus II to constrain the circuits clock to this
frequency. Read the Report produced by the Quartus II Timing Analyzer to ensure that your circuit
operates at this speed; if not, use the Quartus II tools to analyze your circuit and modify your
Verilog code to make a more efficient design that meets the 50MHz speed requirement. Also note
that the Run input is asynchronous to the clock signal, so make sure to synchronize this input using
flipflops. Connect the LEDs register in Figure 8 to LEDR150 so that you can observe the output
produced by the processor.
4. S dng m phng chc nng kim tra mch. m bo rng d liu c c t b nh RAM
v thc hin bi b x l mt cch chnh xc.
5. Thm vo trong d n ca bn cc php gn chn pin cn thit thc hin mch ca bn trn
Kit DE2. S dng cng tc SW17 iu khin u vo Run ca b x l, s dng KEY0 cho
Resetn, v s dng tn hiu xung ng h 50 MHz ca Kit lm u vo xung ng h. Do mch cn
phi chy ng 50 MHz, hy chc chn rng mt hn ch thi gian c thit lp trong Quartus
II nhm hn ch xung ng h ca mch tn s ny. c Bo co to ra bi Timing Analyzer ca
Quartus II m bo rng mch ca bn hot ng tc ny, nu khng, s dng cc cng c
ca Quartus II phn tch mch ca bn v sa i m Verilog ca bn to ra mt thit k hiu
qu hn p ng c tc 50MHz theo yu cu. Cng lu rng u vo Run khng ng
b vi tn hiu xung ng h, do hy chc chn bn s ng b ha u vo bng cch s dng
cc flipflop. Kt ni cc thanh ghi LEDs trong hnh 8 n cc LEDR150 bn c th quan st
cc u ra c to thnh bi b x l.
6. Bin dch mch v np n vo chip FPGA.
7. Kim tra chc nng ca thit k trn bng cch thc thi m t b nh RAM v quan st cc
LED.
Phn IV
Trong phn ny, bn s kt ni mt module I/O b sung cho mch ca bn t Phn III v vit m
c thc hin bi b x l ca bn.
Thm mt module gi l seg7_scroll vo mch ca bn. Module ny s cha mt thanh ghi cho mi
LED 7 thanh trn Kit DE2. Mi thanh ghi trc tip iu khin mi on cho LED 7 thanh, do ,

b x l c th vit cc k t vo cc LED 7 thanh ny. To ra cc qu trnh gii m a ch cn

thit cho php b x l ghi vo thanh ghi trong module seg7_scroll.
1. To mt d n Quartus II cho mch ca bn v vit m Verilog bao gm cc mch t Hnh 8
cng vi module seg7_scroll k trn.
2. S dng m phng chc nng kim tra mch.
3. Thm hn ch thi gian v cc php gn chn thch hp vo d n ca bn, ng thi vit mt
tp tin MIF cho php b x l vit cc k t cho LED 7 thanh. Mt chng trnh n gin s vit
mt t hin th v sau chm dt, nhng mt chng trnh th v hn c th di chuyn mt tin
nhn trn cc mn hnh, hoc di chuyn mt t trn mn hnh t bn tri, phi, hoc c hai hng.
4. Kim tra chc nng ca thit k ca bn bng cch thc thi m t RAM v quan st LED 7
thanh.
Phn V
Thm vo mch ca bn t Phn IV mt mun, gi l port_n, cho php b x l c trng thi
ca mt s cng tc trn Kit. Cc gi tr ca cng tc phi c lu tr vo thanh ghi, v b x l
s c th c thanh ghi ny bng cch s dng mt lnh ld. Bn s phi s dng gii m a ch v
cc b ghp knh nhm cho php b x l c t RAM hoc khi port_n khi, da theo a ch
c s dng.
1. V mt s mch cho thy cch cc khi port_n c tch hp vo h thng.
2. To mt d n Quartus II cho mch ca bn, vit m Verilog, v vit mt tp tin MIF minh ha
vic s dng cc mun port_n. Mt ng dng th v l c b x l di chuyn mt tin nhn trn
LED 7 thanh v s dng cc gi tr c t module port_n thay i tc di chuyn ca n.
3. Kim tra mch ca bn bng cch s dng m phng chc nng, ng thi bng cch np v
thc thi m x l ca bn trn Kit DE2.
Cc phn b sung c ngh
Di y l mt vi b sung c ngh cho bi th nghim ny:
1. S dng cc cng c Quartus II xc nh cc ng dn quan trng trong mch x l. Sa i
cc thit k x l cc mch s hot ng tn s ng h cao nht m bn c th t c.
2. M rng cc cu lnh h tr bi b x l ca bn lm cho n linh hot hn. Mt s loi cu
lnh c ngh l cc cu lnh logic (AND, OR, ...), cc cu lnh dch, v cc cu lnh r nhnh.
Bn cng c th thm cc h tr cho cc iu kin logic ngoi "khc khng", nh c h tr bi
mvnz, v tng t.
3. Vit mt chng trnh Assembler cho b x l ca bn. N s t ng to ra mt tp tin MIF t
m hp ng.