K. S.

RANGASAMY COLLEGE OF TECHNOLOGY, TIRUCHENGODE 637 215

(An Autonomous Institution)
Programme

M.E. VLSI Design

Year/Sem

I/II

Course Code & Name

10 PVL 204 & ASIC DESIGN

Max.Marks

50

ASSIGNMENT - II
Date of Issue: 14.03.2014

S.No
1.

a.

Date of Submission: 24.03.2014

Questions (Answer all questions)

Marks

With neat diagram explain Xilinx LCA interconnect and components of interconnect delay

(10)

in a Xilinx LCA array.

2.

a.

Find the Elmore time constant for the four antifuse Actel routing model.

(04)

b.

Give example for the following low level design language statements

(06)

(i)

3.

4.

5.

ABEL (ii) CUPL (iii) PALASM

a.

Describe logic synthesis and its importance.

(02)

b.

Write an EDIF description for an inverter.

(06)

d.

Compare serial, parallel and concurrent fault simulation.

(02)

a.

Design four bit shift register using blocking assignments in Verilog.

(06)

b.

Draw the logic diagram and write Verilog code for 4:16 decoder with three state output.

(04)

a.

Design serial in parallel out and parallel in serial out shift register using Verilog
HDL.Synthesize design using Xilinx ISE and draw the schematic of XNF netlist and LCA
netlist.

(06)

b.

With neat diagram explain logic cell architecture of Atmel AT40K FPGA.

(04)

Course Instructor

Module- Coordinator

Mr.C.Paramasivam

ASIC Design assignment answers page numbers

HOD/ECE

1. a) pg no 298
2. a) pg no 294
b) pg no 360
3. a) pg no 572
b) pg no 374
c) pg no 761
5. b) http://books.google.co.in/books?
id=2Vsvwyq7BREC&pg=PA49&dq=logic+cell+architecture+of+Atmel+AT40K+FPGA&hl=en&sa=X&e
i=lP0kU5fQBIuErAexrYDgBQ&ved=0CEMQ6AEwAg#v=onepage&q=logic%20cell%20architecture
%20of%20Atmel%20AT40K%20FPGA&f=false