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Tom Tat Verilog
Tom Tat Verilog
I. Gii thiu
// tn chng trnh
1. Khong trng
Khong trng ngn nhng t v c th cha khong cch, khong
di, dng mi v dng ng dn. Do , mt lnh c th a ra nhiu
dng phc tp hn m khng c nhng c tnh c bit.
2. Ch gii
Nhng ch gii c th ch nh bng hai cch: (ging trong C/C++).
Ch gii c vit sau hai du gch xin (//). c vit trn cng
mt dng.
c vit gia /* */, khi vit nhiu dng ch gii.
3. Ch s
Lu tr s c nh ngha nh l mt con s ca cc bit, gi tr c
th l: s nh phn, bt phn, thp phn, hoc thp lc phn.
V d: 3b001, 5d30 = 5b11110,
16h5ED4 = 16d24276 = 16b0101111011010100
4. T nh danh
T nh danh do ngi dng quy nh cho bin s, tn hm, tn
mun, tn khi v tn trng hp. T nh danh bt u bng mt mu t
hoc ng gch di _ ( khng bt u bng mt con s hoc $ ) v k
c mi ch s ca mu t, nhng con s v ng gch di, t nh danh
trong Verilog phn bit dng ch.
5. C php
K hiu cho php:
ABDCEabcdef1234567890_$
Khng cho php: cc k hiu khc -, &, #, @
6. Ton t
Ton t l mt, hai, hoc ba k t dng thc hin cc ton hng trn bin.
Cc ton t bao gm >, +, &, !=.
7. T khaVerilog
.II.
I. t gi tr
Verilog bao gm 4 gi tr c bn. Hu ht cc dng d liu Verilog
cha cc gi tr sau:
0: mc logic 0, hoc iu kin sai.
1: mc logic 1, hoc iu kin ng.
X: mc logic tu nh
Z: trng thi tng tr cao.
X v Z dng c gii hn trong tng hp (synthesis)
II. Wire
M t vt liu ng dy dn trong mt mch in v c dng
kt ni cc cng hay cc module. Gi tr ca Wire c th c, nhng khng
c gn trong hm (function) hoc khi (block). Wire khng lu tr gi tr
ca n nhng va?n phi c thc thi bi 1 lnh gn k tip hay bi s kt
ni Wire vi u ra ca 1 cng hoc 1 module. Nhng dng c bit khc
ca Wire:
Wand(wired_and): gi tr ph thuc vo mc logic And ton b b iu
khin kt ni n Wire.
Wor (wired_or): gi tr ph thuc vo mc logic Or ton b b iu
khin kt ni n Wire.
Tri(three_state): tt c b iu khin kt ni n 1 tri phi trng
thi tng tr cao.
1. C php
Wire [msb:lsb] tn bin wire.
Wand [msb:lsb] tn bin wand.
Wor [msb:lsb] tn bin wor.
Tri [msb:lsb] tn bin tri.
2. V d
Wire c;
Wand d;
Assign d= a;
Assign d= b;// gi tr d l mc logic ca php And a v b.
Wire [9:0] A; // vect A c 10 wire.
III. Reg
Reg (register) l i tng d liu m n cha c gi tr t mt th
tc gn k tip. Reg ch c dng trong hm v khi th tc. Reg l mt
loi bin Verilog v khng nht thit l thanh ghi t nhin. Trong thanh ghi
ChngV- TON T
I. Ton t s hc
Nhng ton t ny thc hin cc php tnh s hc. Du + v - c th
c s dng mt trong hai ton t n (-z) hoc kp (x - y).
1. Ton t:
+, -, *, /, %.
2. V d:
parameter n = 4;
Reg[3:0] a, c, f, g, count;
f= a +c;
g= c n;
count = (count +1) % 16; // c th m t 0 n 15.
II. Ton t quan h
Ton t quan h so snh hai ton hng v tr v mt n bit l 0
hoc 1. Nhng ton t ny tng hp vo dng c so snh. Bin Wire v Reg
l nhng bin dng. V th, (-3b001) = (3b111) v (-3b001) > ( 3b110)
nhng nu l s nguyn th -1< 6.
1. Cc ton t quan h:
<, <=, >, >=, = =, !=.
2. V d:
If (x= =y) e =1;
Else e= 0;
// so snh hai vector a, b
reg [3:0] a, b;
if (a[3] = =b [3]) a[2:0] >b[2:0];
else b[3];
III. Ton t bit_wire
So snh tng bit hai ton ton hng.
1. Cc ton t:
~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwire XOR), ~^
hoc, ^~ (bitwire XNOR).
2. V d:
Module and2(a, b, c);
Input [1:0] a, b;
Output [1:0] c;
Assign c = a & b;
Endmodule
IV. Ton t logic
Ton t logic tr v 1 bit n 0 hoc 1. chng ging nh ton t
bitwire ch l nhng ton hng n bit. Chng c th lm vic trn biu
thc, s nguyn hoc nhm bit, v coi nhu tt c cc gi tr khng bng 0 l
1. Ton t logic c dng nhiu trong lnh iu kin (if else), khi
chng lm vic trn biu thc.
1. Ton t:
!(NOT), && (AND), || (OR)
2. V d:
Wire [7:0] x, y, z;
Reg a;
1. Ton t
<< ( dch tri), >> (dch phi).
2. V d:
assign c = a<<2; c = a dch tri 2 bit cc ch trng c in vi
nhng s 0.
VII. Ton t dch
Ghp hai hoc nhiu ton hng thnh mt vect ln.
1. Ton t:
{} (concatenation)
2. V d:
Wire [1:0] a, b;
Wire [2:0] x;
Wire [3:0] y, Z;
Assign x = {1b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0].
Assign y = {a, b}; // y[3]= a[1], y[2] = a[0], y[1] = b[1], y[0] = b[0].
VIII. Ton t th bn
To ra nhiu bn sao ca mt mc chn.
1. Ton t:
{n{ mc chn }} n nhm th bn trong mt mc chn.
2. V d:
Wire [1:0] a, b;
Wire [3:0] x;
Assign x = {2{1b0},a}; // x= {0, 0, a}.
IX. Ton t iu kin
Ging nh C/C++. Chng nh gi mt trong hai biu thc c bn
trong mt iu kin. N s tng hp thnh b a cng (MUX).
1. Ton t :
(iu kin)? kt qu khi iu kin ng : kt qu khi iu kin sai.
2. V d:
assign a = (g) ? x : y;
Assign a = ( inc = =2) ? a+1: a-1;
X. Th t ton t
Nhng ton t trong mc ging nhau nh gi t tri sang phi
Ton t
[]
()
!, ~
&, |, ~&, ~|, ^,
~^
+, {}
{{ }}
*, /, %
+, <<, >>
<, <=, >, >=
= =, !=
&
^, ~^
|
&&, ||
?:
Tn
Chn bit, chn phn
Phn trong ngoc n
Mc logic v bit_wire NOT
Bin i: AND, OR, NAND, NOT, XOR,
XNOR.
Du ch s m s dng.
Ghp ni { 3b101,3b110} = 6b101110
Th bn {3{3b101 }}=9b101101101
Nhn, chia, phn trm.
Cng tr nh phn.
Dch tri, phi.
Du so snh. Bin Reg v wire c ly bng
nhng s dng.
Bng v khng bng trong ton t logic.
Bit_wire AND, and tt c cc bit vi nhau.
Bit_wire XOR, Bit_wire XNOR.
Bit_wire OR.
Ton t logic AND, OR.
x = ( iu kin ) T:F
I. Khai bo modules:
Mt module l bn thit k ch yu tn ti trong Verilog. Dng u
tin ca khai bo module ch r danh sch tn v port (cc i s). Cc
dng k tip ch r dng I/O (input/output, hoc inout) v chiu rng ca
mi port. Mc nh rng port l 1 bit. Sau , cc bin port phi c
khai bo wire, wand, , reg (mc nh l wire). Cc u vo l dng wire
khi d liu c cht bn ngoi module. Cc u ra l dng reg nu cc
t/hiu ca chng c cha trong khi always hoc initial.
1. C php:
Module tn module (danh sch port);
Input [msb:lsb] danh sch port u vo;
Output [msb:lsb] danh sch port u ra;
Inout [ msb:lsb ] danh sch port vo_ ra;
cc lnh
endmodule
2. V d:
Module add_sub(add, in1, in2, out);
Wire, reg, v tham s:
Input[7:0 ] in1, in2;
Wire in1, in2;
Output [7:0] out;
Reg out;
cc lnh khc
Endmodule
II. Ch nh lin tip:
Cc ch nh lin tip c dng gn mt gi tr ln trn mt wire
trong mt module; bn ngoi khi always hoc khi initial. Cc ch nh
lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s ch
nh mt gi tr n mt wire trong lc khai bo. Lu , cc lnh ch nh
lin tip th tn ti v c chy lin tc trong sut qu trnh m phng.
Th t cc lnh gn khng quan trng. Mi thayi bn phi ca bt c u vo s
lp tc thayi bn tri ca ccu ra.
1. C php:
Wire bin wire = gi tr?;
Assign bin wire = biu thc;
2. V d:
Wire [ 1:0 ] a = 2b 01;
Assign b = c &d;
Assign d = x | y;
III. Module instantiations:
Cc khai bo module phi theo mu t cc i tng thc t
(instantiation). Cc module n bn trong cc module khc, v mi dn
chng to mt i tng c nht t khun mu. Ngoi tr l module
mc trn l nhng dn chng t chnh chng.
Cc port ca module v d phi tha nhng nh ngha trong khun
mu. y l mt l thuyt: bng tn, s dng du chm(.) .tn port khun
mu (tn ca wire kt ni n port). Bng v tr, t nhng port nhng
v tr ging nhau trong danh sch port ca c khun mu ln instance.
1. C php:
Tn instance1 (danh sch kt ni port );
Tn instance2(danh sch kt ni port);
2. V d:
// nh ngha module
module and4(a,b,c);
input [3:0]a,b;
output [3:0]c;
assign c = a&b;
endmodule
// module instantiations
wire [3:0] in1, in2;
wire [3:0] o1, o2;
// t v tr
and4 C1(in1, in2,o1);
// tn
and4 C2(.c(o2), .a(in1), .b(in2));
1. C php:
For (bin m = gi tr 1; bin m </ <=/ >/ >= gi tr 2;
bin m = bin m +/- gi tr?)
begin
lnh
end
2. V d:
For (j = 0; j<=7; j = j+1)
Begin
c[j] = a[j] & b[j];
d[j] = a[j] | b[j];
end
VI. Vng lp while
Vng lp while thc hin nhiu ln mt lnh hoc khi lnh cho n khi
biu thc trong lnh while nh gi l sai.
1. C php:
While (biu thc)
Begin
cc lnh
end
2. V d:
While (!overflow)
@(posedge clk);
a = a +1;
end
VII. Khi lnh if else if else
Thc hin mt lnh hoc mt khi lnh ph thuc vo kt qu ca
biu thc theo sau mnh if.
C php
If (biu thc)
Begin
cc lnh
end
else if (biu thc)
Begin
cc lnh
end
else
Begin
cc lnh
end
VIII. Case
Lnh case cho php la chn trng hp. Cc lng trong khi default thc
thi khi khng c trng hp la chn so snh ging nhau. Nu khng c s
so snh, bao gm c default, l ng, s tng hp s to ra cht khng
mong mun.
1. C php:
Case (biu thc)
Case 1:
Begin
cc lnh
end
Case 2:
Begin
cc lnh
end
Case 3:
Begin
cc lnh
end
default:
begin
cc lnh
end
endcase
2. V d:
Case (alu_clk)
2b00: aluout = a + b;
2b01: aluout = a - b;
2b10: aluout = a & b;
default:
aluout = 1bx;
endcase
I. Khi always:
L cu trc chnh trong khun mu RTL (Register Transfer Level).
Khi always c th c dng trong cht, flip flop hay cc kt ni logic.
Tt c cc khi always trong mt module thc thi mt cch lin tc. Nu
cc lnh ca khi always nm trong phm vi khi begin end th c
thc thi lin tc, nu nm trong khi fork join, chng c thc thi ng
thi (ch trong m phng). Khi always thc hin bng mc, cnh ln/xung
ca mt or nhiu tn hiu (cc tn hiu cch nhau bi t kha OR).
C php:
Always @(s kin 1 or s kin 2 or)
Begin
cc lnh
end
Always @(s kin 1 or s kin 2 or)
Begin: tn khi
cc lnh
end
II. Khi initial
Tng t khi always nhng khi initial ch thc thi mt ln t lc
bt u ca qu trnh m phng. Khi ny l tiu biu bin khi chy v
ch nh dng sng tn hiu trong lc m phng.
1. C php:
Initial
Begin
cc lnh
end
2. V d:
Initial
Begin
Clr = 0;
Clk = 1;
End
Initial
Begin
a = 2b00;
#50 a = 2b01;
#50 a = 2b10; end
Chng X- HM
2. V d:
Module simple_processor (instruction, outp);
Input [31:0] instruction;
Output [7:0] outp;
Reg [7:0] outp;// c th c gn trong khi always.
Reg func;
Reg [7:0] opr1, opr2;
Function[16:0] decode add(instr)
Input [31:0] instr;
Reg add_func;
Reg [7:0] opcode, opr1, opr2;
Begin
Opcode = instr[31:24];
Opr1 = instr[7:0];
Case (opcode)
8b 10001000:
begin
add_func = 1;
opr2 = instr[15:8];
end
8b 10001001:
begin
add_func = 0;
opr2 = instr[15:8];
end
8b 10001010: begin
add_func = 1;
opr2 = 8b 00000001;
end
default: begin
add_func = 0;
opr2 = 8b00000001;
end
endcase
decode_add =
add_func, opr2, opr1
;
end
endfunction
always @(intruction) begin
Chng XI
CHC NNG LINH KIN
Chng XII - MT S V D
2. V d 2:
a. Chng trnh cng hai bin bn bit
module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0]sum_out;
input [3:0]ina, inb;
output carry_out;
input carry_in;
wire carry_out, carry_in;
wire[3:0] sum_out, ina, inb;
assign
Endmodule
b. M phng
wire en;
always @(w or en)
begin
if(en==1'b1)
begin
case(w)
2'b00: y<=4'b1000;
2'b01: y<=4'b0100;
2'b10: y<=4'b0010;
default:y<=4'b0001;
endcase
end
else
end
y<= 4'b0000;
endmodule
b. M phng
3. V d 3:
a. Chng trnh gii m 2 sang 4
module dec2to4 (w, en, y);
input [1:0] w;
input en;
output[3:0] y;
wire[1:0]w;
reg[3:0]y;
4. V d 4:
a. B dn knh 2 sang 1
module mux12(w0, w1, s, y);
input w0, w1;
input s;
output y;
wire w0, w1, s;
reg y;
always @(w0 or w1 or s)
begin
if(s==1)
y = w0;
else
y = w1;
end
endmodule
b. M phng
5. V d 5:
a. Chng trnh dn knh 4 sang 1
module mux14(w0, w1, w2, w3, s, y);
6. V d 6:
a. Chng trnh i BCD sang by on
Module mp_led(bcd,led);
input [3:0] bcd;
output [7:0] led;
7. V d 7:
a. Chng trnh gim t 9 xung 0, hin th ra led 7 on
module bcd (clock, rst, s1, led, digit1);
input clock, s1, rst;
output [7:0] led;
output digit1;
reg [7:0] led;
reg [3:0] bcd;
wire digit1;
assign digit1 = 1'b1;
always @(posedge clock )
begin
if (rst == 1'b1) bcd <= 4'b1001;
else if (s1 == 1'b1) bcd <= bcd - 1'b1;
if (bcd == 4'b0) bcd <= 4'b1001;
end
always @(posedge clock)
begin
case(bcd)
4'b0000: led = 8'b11111100;
4'b0001: led = 8'b01100000;
4'b0010: led = 8'b11011010;
4'b0011: led = 8'b11110010;
4'b0100: led = 8'b01100110;
4'b0101: led = 8'b10110110;
4'b0110: led = 8'b10111110;
4'b0111: led = 8'b11100000;
4'b1000: led = 8'b11111110;
4'b1001: led = 8'b11100110;
default: led = 8'b11111111;
endcase
end
endmodule
b. M phng
8. V d 8:
a. Chng trnh tng t 0 n 9, hin th ra led 7 on
module bcdtang (clock, rst, s1, led, digit1);
input clock, s1, rst;
output [7:0] led;
output digit1;
endmodule
b. M phng