AREA-EFFICIENT PARALLEL FIR DIGITAL FILTER

STRUCTURES FOR SYMMETRIC CONVOLUTIONS BASED

ON FAST FIR ALGORITHM

ABSTRACT:
In this paper proposes new parallel FIR filter structures, which are beneficial to
symmetric coefficients in terms of the hardware cost, under the condition that the number of taps
is a multiple of 2 or 3. The proposed parallel FIR structures exploit the inherent nature of
symmetric coefficients reducing half the number of multipliers in sub filter section at the expense
of additional adders in preprocessing and post processing blocks. Exchanging multipliers adders
is advantageous because adders weigh less than multipliers in terms of silicon area; in addition,
the overhead from the additional adders in preprocessing and post processing blocks stay fixed
and do not increase along with the length of the FIR filter, whereas the number of reduced
multipliers increases along with the length of the FIR filter.

EXISTING SYSTEM:
Traditional FIR filter structure and FFA based FIR filter structure and symmetric
convolution based FFA FIR filter is designed for 2-parallel filter (2*2). These entire filter
structures are designed based on Carry Save Adder (CSA) and Ripple Carry Adder (RCA)

EXISTING SYSTEM ALGORITHM:

FFA Algorithm

EXISTING SYSTEM DRAWBACKS:

Compare to Hardware consumption is more

Power will be high

PROPOSED SYSTEM:
In this proposed system, we provide new parallel FIR filter structures based on FFA
consisting of advantageous poly phase decompositions, which can reduce amounts of
multiplications in the sub filter section by exploiting the inherent nature of the symmetric
coefficients, compared to the existing FFA fast parallel FIR filter structure.

PROPOSED SYSTEM BLOCK DIAGRAM:

Fig: Proposed Three-parallel FIR filter implementation

PROPOSED SYSTEM ALGORITHM:

Parallel Fast FIR Algorithm

PROPOSED SYSTEM ADVANTAGES:

Lower hardware consumption

SOFTWARE REQUIREMENTS:

ModelSim 6.4c

Xilinx 9.1/13.2

Matlab 7.14(R2012a)

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

Video processing

High throughput with a low-power circuit such as multiple- input multiple-output

(MIMO) systems used in cellular wireless Communication

FUTURE ENHANCEMENT:
Two sets of the ideal low-pass FIR filter symmetric coefficients of length 24 are
generated by MATLAB using Remez Exchange algorithm and will be verified by system verilog
language.