EFFICIENT INTEGER DCT ARCHITECTURES FOR HEVC

ABSTRACT:
We present area- and power-efficient architectures for the implementation of integer
discrete cosine transform (DCT) of different lengths to be used in High Efficiency Video Coding
(HEVC).We show that an efficient constant matrix multiplication scheme can be used to derive
parallel architectures for 1-D integer DCT of different lengths. We also show that the proposed
structure could be reusable for DCT of lengths 4, 8, 16, and 32 with a throughput of 32 DCT
coefficients per cycle irrespective of the transform size. Moreover, the proposed architecture
could be pruned to reduce the complexity of implementation substantially with only a marginal
affect on the coding performance. From the synthesis result, it is found that the proposed
architecture involves less

area -delay product (ADP) and less energy per sample (EPS)

compared to the direct implementation of the reference algorithm.

EXISTING SYSTEM:
The existing designs for conventional DCT based on constant matrix multiplication
(CMM) and MCM can provide optimal solutions for the computation of any of these lengths, but
they are not reusable for any length to support the same throughput processing DCT of different
transform lengths.
EXISTING TECHNIQUE:

Conventional DCT Constant matrix multiplication (CMM) and MCM.

DRAWBACKS:

They are not reusable for any length

High area , More delay

PROPOSED SYSTEM:
Designed scalable and reusable architectures for 1-D and 2-D integer DCTs for HEVC
that could be reused for any of the prescribed lengths with the same throughput of processing
irrespective of transform size. We present algorithms for hardware implementation of the HEVC
integer DCTs of different lengths 4, 8, 16, and 32.
PROPOSED TECHNIQUE:
The Scalable and reusable architectures for 1-D and 2-D integer DCTs for HEVC. That
could be reused for any of the prescribed lengths with the same throughput of processing
irrespective of transform size.

BLOCK DIAGRAM:

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3.

APPLICATION:

Mobile Multimedia Devices.

Digital Cameras & HDTV.

ADVANTAGES:

Reused for any of the prescribed lengths.

Less area-delay

FUTURE ENHANCEMENT:
We will modify the proposed system by reducing the Area and delay of the design in
future.

ALTERNATE TITLES:

Efficient Integer DCT Architectures for High Efficiency Video Coding.

High Efficiency Video Coding Efficient Integer DCT Architectures using Verilog HDL.

An FPGA Implementation of Efficient Integer DCT Architectures

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification).