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RRUS 01 1 log

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[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.708] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.708] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.712] trDcProc dlCtrl.cc:228 INFO:Carrier id 780, FilterBran
ch id 0 is added into reEnabledCarrierFBList
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 08:04:21.712] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 08:04:21.712] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:21.712] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 08:04:21.712] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097

[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev


= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, t
xFreq: 0, state: OFF;
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 08:04:21.712] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:21.720] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 08:04:21.796] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.800] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 08:04:21.800] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:21.800] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 08:04:21.800] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-13.01[-42.55 -8.00], DpdPma:-16.09[-16.51 -15.51], Pmb:-13.00, TorPm
b:-13.00[-48.00 -8.00] dB)
[2015-01-13 08:04:21.800] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 08:04:21.804] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 08:04:21.804] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 08:04:21.804] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 08:04:21.804] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 08:04:21.804] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 08:04:21.804] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :8
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:

dev = 7, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state RAMPING
, de off, ga on; dev: 1, txFreq: 953400, state: IN
IT; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, t
xFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF; dev: 6, txFreq: 0, sta
te: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, tx
Freq: 0, state: OFF;
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.848] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.864] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-33.43[-61.50 -8.00] dB)
[2015-01-13 08:04:21.916] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 8
[2015-01-13 08:04:21.916] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :8
[2015-01-13 08:04:21.916] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 08:04:21.972] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 08:04:21.972] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 08:04:21.972] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 08:04:21.976] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 08:04:21.980] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :1024
[2015-01-13 08:04:21.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
70 [0.1ns]
[2015-01-13 08:04:21.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1254), hardDelay:(834)

[2015-01-13 08:04:21.984] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2


81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 08:04:21.984] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298994 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3670 + DpdDelay:1749
[2015-01-13 08:04:21.984] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :128
[2015-01-13 08:04:21.988] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 08:04:21.988] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
70 [0.1ns]
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1254), hardDelay:(834)
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
70 [0.1ns]
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1254), hardDelay:(834)
[2015-01-13 08:04:21.988] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 08:04:21.988] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298994 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3670 + DpdDelay:1749
[2015-01-13 08:04:21.992] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30439[ns] = salCarrierReportedDelay:298994 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 08:04:21.992] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 256 ns
[2015-01-13 08:04:22.004] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:21, clientId:102

[2015-01-13 08:04:22.020] trxEvtProc eventHandler.cc:1028 INFO:Event already sub


scribed,eventId=0x80, txId=0
[2015-01-13 08:04:22.024] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:22.024] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 783
[2015-01-13 08:04:22.024] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:22.032] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500
, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:22.032] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:22.032] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:22.032] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 08:04:22.032] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 08:04:22.032] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 08:04:22.032] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 783
[2015-01-13 08:04:22.036] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:15, clientId:102
[2015-01-13 08:04:22.048] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:22.048] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:22.048] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 786
[2015-01-13 08:04:22.048] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:22.048] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev

= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:22.048] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:22.052] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:22.052] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 08:04:22.052] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 08:04:22.052] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 08:04:22.052] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 08:04:22.052] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 786
[2015-01-13 08:04:22.056] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:18, clientId:102
[2015-01-13 08:04:22.068] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:22.068] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:22.068] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 789
[2015-01-13 08:04:22.068] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:22.068] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OF
F; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:22.068] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId

1 already unblocked.
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 08:04:22.072] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 08:04:22.072] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 08:04:22.072] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 08:04:22.072] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 789
[2015-01-13 08:04:22.076] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 08:04:22.076] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:21, clientId:102
[2015-01-13 08:04:22.212] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f861f7 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
c3ca0 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb10
c5ac pa1Adj 0x4779
[2015-01-13 08:04:22.456] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.131801, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.48[-61.50 -8.00] dB)
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x84140008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24786

[2015-01-13 08:04:22.680] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed


peak phase calibration in 29199 us.
[2015-01-13 08:04:22.680] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 08:04:22.704] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24400 us. IntegerDelay: 0x1d3 FracDela
y: 0x2a
[2015-01-13 08:04:22.704] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
f8
[2015-01-13 08:04:22.704] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2755, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.708] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.712] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298931 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3676 + DpdDelay:1721
[2015-01-13 08:04:22.712] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298931 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.712] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns

[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3676 [0.1ns]
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.724] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298972 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3676 + DpdDelay:1721
[2015-01-13 08:04:22.728] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298972 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.728] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)

[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.740] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298972 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3676 + DpdDelay:1721
[2015-01-13 08:04:22.744] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298972 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.744] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3676 [0.1ns]
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.756] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298972 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3676 + DpdDelay:1721
[2015-01-13 08:04:22.760] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298972 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.760] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns

[2015-01-13 08:04:22.772] dlCtrlProc dlCtrl.cc:312 INFO:DlCtrl::removeReEnableCa


rrierFBIfReceived: remove the filterBranchId = 0 from the reEnabedCarrierFBList
list upon receipt of TRX_TX_ON_IND
[2015-01-13 08:04:22.772] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 08:04:22.772] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 08:04:22.772] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 08:04:22.772] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 08:04:23.012] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0005c C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
7c0eb C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0b
2aaf pa1Adj 0x4779
[2015-01-13 08:04:24.016] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f01942 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
cf86b C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb11
b09f pa1Adj 0x4779
[2015-01-13 08:04:25.020] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef7084 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
a3cbe C1 0x10e2685 C2 0x0 C3 0x0, pa0C0Adj 0x1f96
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1
0xc529bec pa1Adj 0x4779
[2015-01-13 08:04:26.024] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x203d8fb C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
e8a97 C1 0x16a84b9 C2 0x0 C3 0x0, pa0C0Adj 0x1f96
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1
0xcc7c9b3 pa1Adj 0x4779
[2015-01-13 08:04:27.028] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec2794 C1 0x19a9d3 C2 0x0 C3 0x0, pmPa0C0
0x8d8d2f1 C1 0x3edda72 C2 0x0 C3 0x0, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xfcf7a52 pa1Adj 0x4779
[2015-01-13 08:04:28.028] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ecd582 C1 0x12e738c C2 0x0 C3 0x0, pmPa0C
0 0x8dde598 C1 0x24211e9 C2 0x0 C3 0x0, pa0C0Adj 0
x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xddba932 pa1Adj 0x4779
[2015-01-13 08:04:29.032] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ebb8d9 C1 0x11eea88 C2 0x0 C3 0x0, pmPa0C
0 0x8db47cb C1 0x32a1b82 C2 0x0 C3 0x0, pa0C0Adj 0
x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xede2e26 pa1Adj 0x4779
[2015-01-13 08:04:30.036] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ecaa53 C1 0x1e8ddbd C2 0x0 C3 0x0, pmPa0C

0 0x8da5a32 C1 0x1c382cf C2 0x0 C3 0x0, pa0C0Adj 0


x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xd2f623f pa1Adj 0x4779
[2015-01-13 08:04:31.040] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef1bd8 C1 0xc79bc C2 0x0 C3 0x0, pmPa0C0
0x8dce506 C1 0x1e7e81a C2 0x0 C3 0x0, pa0C0Adj 0x1
f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, p
mPa1 0xd6aab59 pa1Adj 0x4779
[2015-01-13 08:04:32.044] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eef6ae C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
dc9d8 C1 0x23815ce C2 0x0 C3 0x0, pa0C0Adj 0x1f96
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1
0xdccbd8e pa1Adj 0x4779
[2015-01-13 08:04:33.048] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef02fc C1 0x1dbafc C2 0x0 C3 0x0, pmPa0C0
0x8dc4a89 C1 0x2f2a519 C2 0x0 C3 0x0, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xea390b3 pa1Adj 0x4779
[2015-01-13 08:04:33.860] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2063850 C1 0x2068850 C2 0x0 C3 0x0, pmPa0C
0 0x8d6a3aa C1 0x2adc2c7 C2 0x0 C3 0x0, pa0C0Adj 0
x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xe3d1892 pa1Adj 0x4779
[2015-01-13 08:04:34.864] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0607c C1 0x181a71a C2 0x0 C3 0x0, pmPa0C
0 0x8dc46fa C1 0x4cb7528 C2 0x0 C3 0x0, pa0C0Adj 0
x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0x10f85dc1 pa1Adj 0x4779
[2015-01-13 08:04:35.868] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f023d4 C1 0x10b0dc4 C2 0x0 C3 0x0, pmPa0C
0 0x8d93c41 C1 0x30a4688 C2 0x0 C3 0x0, pa0C0Adj 0
x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xeb74795 pa1Adj 0x4779
[2015-01-13 08:04:36.872] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f01568 C1 0x1a3ed4 C2 0x0 C3 0x0, pmPa0C0
0x8da3186 C1 0x14ac6f3 C2 0x0 C3 0x0, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xca2f02e pa1Adj 0x4779
[2015-01-13 08:04:37.876] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f05002 C1 0x5f8f7 C2 0x0 C3 0x0, pmPa0C0
0x8d8db1c C1 0x2ed739d C2 0x0 C3 0x0, pa0C0Adj 0x1
f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, p
mPa1 0xe91cb9f pa1Adj 0x4779
[2015-01-13 08:04:38.880] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec2026 C1 0x462734 C2 0x0 C3 0x0, pmPa0C0
0x8dcc4fc C1 0x114d2ce C2 0x0 C3 0x0, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xc5efa2e pa1Adj 0x4779
[2015-01-13 08:04:39.884] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec43f6 C1 0x0 C2 0x0 C3 0x182bc67, pmPa0C

0 0x8daf9e9 C1 0x269cb91 C2 0x0 C3 0x10cb14e, pa0C


0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0
x8008, pmPa1 0xf48377c pa1Adj 0x4779
[2015-01-13 08:04:40.888] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2046bbf C1 0xce23b8 C2 0x0 C3 0x0, pmPa0C0
0x8dd0887 C1 0x2fa1b50 C2 0x0 C3 0x5c222e, pa0C0A
dj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8
008, pmPa1 0xf24e524 pa1Adj 0x4779
[2015-01-13 10:02:10.924] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:10.928] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0xf
[2015-01-13 10:02:10.928] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ea2e57 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
ad2a9 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0f
0397 pa1Adj 0x4779
[2015-01-13 10:02:10.936] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 3; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 953400, state:
ON; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: ON; dev: 8
, txFreq: 0, state: OFF;
[2015-01-13 10:02:10.936] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 783
[2015-01-13 10:02:10.940] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = 0 (gainOffset:0 + gainMargin:122)
[2015-01-13 10:02:10.940] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:10.940] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:15, clientId:102
[2015-01-13 10:02:10.944] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:02:10.944] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:10.944] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:02:10.944] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:02:10.944] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:02:10.944] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri

erUpdateEvent successful for carrier: 783 event :4


[2015-01-13 10:02:10.948] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 3, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 953400, state: ON; dev: 2, txFreq: 0, state: O
FF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, t
xFreq: 955500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500,
state: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:10.948] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:02:11.016] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:11.016] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:11.016] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80100008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:11.016] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24874
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 30799 us.
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:02:11.072] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24533 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:02:11.072] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fc
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]

[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela

y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor


tDelay:(80)
[2015-01-13 10:02:11.096] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:02:11.100] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.100] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.112] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:02:11.116] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.116] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:02:11.128] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520, (result: true)

[2015-01-13 10:02:11.192] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr


ierUpdateEvent successful for carrier: 783, event: 4
[2015-01-13 10:02:11.192] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :4
[2015-01-13 10:02:11.192] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:11.244] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:02:11.244] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(1), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:11.244] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:11.244] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.248] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:02:11.256] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.256] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:15, clientId:102
[2015-01-13 10:02:11.256] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:15
[2015-01-13 10:02:11.256] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 784
[2015-01-13 10:02:11.256] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:16, clientId:102
[2015-01-13 10:02:11.264] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:02:11.264] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.264] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.264] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=784, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.264] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:11.268] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:02:11.268] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:16, clientId:102

[2015-01-13 10:02:11.268] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli


entId:102 carrierId:16
[2015-01-13 10:02:11.272] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:11.272] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:02:11.272] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 5; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 953400, state:
ON; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: O
FF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: ON; dev: 8, tx
Freq: 0, state: OFF;
[2015-01-13 10:02:11.272] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 786
[2015-01-13 10:02:11.276] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.276] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:02:11.276] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:02:11.276] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:11.276] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:02:11.280] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:02:11.280] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 786 event :4
[2015-01-13 10:02:11.280] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 5, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 953400, state: ON; dev: 2, txFreq: 0, state: O
FF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq
: 955500, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, sta
te: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:11.280] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:02:11.348] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:11.348] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq

= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x


718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:11.348] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80100008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:11.348] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:11.028] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 10:02:11.028] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 10:02:11.028] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24861
[2015-01-13 10:02:11.032] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29733 us.
[2015-01-13 10:02:11.032] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:02:11.056] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24400 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:02:11.056] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fd
[2015-01-13 10:02:11.056] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.076] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns

[2015-01-13 10:02:11.092] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr


lAtRelease antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520, (result: true)
[2015-01-13 10:02:11.144] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 786, event: 4
[2015-01-13 10:02:11.144] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :4
[2015-01-13 10:02:11.144] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:11.192] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:02:11.192] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(2), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:11.192] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:11.192] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.196] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:02:11.200] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.200] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:18, clientId:102
[2015-01-13 10:02:11.200] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:18
[2015-01-13 10:02:11.200] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 787
[2015-01-13 10:02:11.200] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:19, clientId:102
[2015-01-13 10:02:11.208] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:02:11.208] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.208] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.208] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=787, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.208] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:11.212] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000

[2015-01-13 10:02:11.212] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f


or carrierId:19, clientId:102
[2015-01-13 10:02:11.212] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:19
[2015-01-13 10:02:11.212] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 785
[2015-01-13 10:02:11.212] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:17, clientId:102
[2015-01-13 10:02:11.216] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:02:11.220] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.220] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.220] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=785, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.220] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:11.220] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:02:11.224] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:17, clientId:102
[2015-01-13 10:02:11.224] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:17
[2015-01-13 10:02:11.224] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 788
[2015-01-13 10:02:11.224] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:20, clientId:102
[2015-01-13 10:02:11.228] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:02:11.228] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.228] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.228] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=788, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.232] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:11.232] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000

[2015-01-13 10:02:11.232] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f


or carrierId:20, clientId:102
[2015-01-13 10:02:11.232] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:20
[2015-01-13 10:02:11.808] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x1ecbdf0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x92
0a94d C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb73e77c pa1Adj
0x47a4
[2015-01-13 10:02:12.860] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x1ecb853 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x92
03ea6 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb736186 pa1Adj
0x47a4
[2015-01-13 10:02:13.864] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x1efd701 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x91
e1c83 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb70b3fd pa1Adj
0x47a4
[2015-01-13 10:02:14.868] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x1efd205 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x92
0cf5e C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb741724 pa1Adj
0x47a4
[2015-01-13 10:02:15.872] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x1ef7ef2 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x91
d9e08 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb7014f0 pa1Adj
0x47a4
[2015-01-13 10:02:16.876] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0xc, fabForce 0x6, mplPwrC0 0x2063164 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x91
c1337 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x200c C1 0x0
C2 0x0 C3 0x2014, ncoC0 0x8350 C1 0x0 C2 0x0 C3 0x8008, pmPa1 0xb6e25ad pa1Adj
0x47a4
[2015-01-13 10:02:17.852] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:17.852] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:02:17.856] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 7; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 953400, state:
ON; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF; dev: 8, txFreq
: 0, state: OFF;
[2015-01-13 10:02:17.856] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 789

[2015-01-13 10:02:17.856] trDcProc paConfig.cc:136 INFO:Not allowed to turn off


PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:17.856] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:21, clientId:102
[2015-01-13 10:02:17.856] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:02:17.856] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:17.856] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:02:17.860] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :4
[2015-01-13 10:02:17.860] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95340
0 (kHz), compensatedFreq = 953440 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:02:17.868] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=789
[2015-01-13 10:02:17.868] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:17.900] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:02:17.908] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 7, txLo: 953440, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 953400, state: ON; dev: 2, txFreq: 0, state: O
FF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq
: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: O
FF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:17.908] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 953400, LoFreq = 953400
[2015-01-13 10:02:17.972] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:17.976] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:17.976] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80100008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:17.976] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:18.004] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib

rate_result_phase status ok: step 0: 58 deg


[2015-01-13 10:02:18.004] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 10:02:18.004] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 23801
[2015-01-13 10:02:18.004] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 28933 us.
[2015-01-13 10:02:18.004] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 28533 us. IntegerDelay: 0x1d3 FracDela
y: 0x15
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x000020
00
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2776, currentDpdDelay[1]=1735 (0.1 ns)
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:18.036] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298944 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3675 + DpdDelay:1735
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30434[ns] = salCarrierReportedDelay:298944 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT

oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.


1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:18.040] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 261 ns
[2015-01-13 10:02:18.056] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 953440, (result: true)
[2015-01-13 10:02:18.092] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 4
[2015-01-13 10:02:18.092] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :4
[2015-01-13 10:02:18.092] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(3), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:18.092] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:18.092] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.096] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:02:18.104] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:02:18.116] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:02:18.116] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:18.120] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:18.120] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:18.120] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:18.136] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3675 [0.1ns]
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:18.140] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298958 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3675 + DpdDelay:1749
[2015-01-13 10:02:18.144] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30436[ns] = salCarrierReportedDelay:298958 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:18.144] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 259 ns
[2015-01-13 10:02:18.152] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x2045 C1 0x0 C2 0x0 C3 0
x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:18.220] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:02:18.220] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:02:18.220] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:02:18.244] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:02:18.244] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:02:18.244] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:02:18.244] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:02:18.244] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:02:18.276] timeOutSrv channelSupervision.cc:490 INFO:"IDpa0" chan
nel supervision. Read value (1) below exceptional low limit (100).

[2015-01-13 10:02:18.288] timeOutSrv channelSupervision.cc:490 INFO:"IMpa0" chan


nel supervision. Read value (0) below exceptional low limit (500).
[2015-01-13 10:02:18.448] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 953400, txLo: 953440, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:18.448] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:02:18.448] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 953400
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:18.452] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 953440 (result: true)
[2015-01-13 10:02:18.452] trDcProc dlCtrl.cc:228 INFO:Carrier id 780, FilterBran
ch id 0 is added into reEnabledCarrierFBList
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:02:18.452] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:02:18.452] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:02:18.452] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 10:02:18.452] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:18.452] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal

led with newState = paOnEvent. Current state is paOnPendEvent


[2015-01-13 10:02:18.452] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:02:18.464] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:02:18.540] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:02:18.544] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:02:18.544] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:02:18.544] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:02:18.544] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-14.15[-42.55 -8.00], DpdPma:-16.63[-17.65 -16.65], Pmb:-14.06, TorPm
b:-14.06[-49.06 -8.00] dB)
[2015-01-13 10:02:18.544] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:02:18.544] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:18.544] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:21, clientId:102
[2015-01-13 10:02:18.544] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:21
[2015-01-13 10:02:18.544] trDcProc dlCtrl.cc:261 INFO:DlCtrl::carrierUpdateEvent
: remove the filter branch id 0 from the reEnabledCarrierFBList upon receipt of
event CR_SUBSCRIPTION_EVENT_CARRIER_DISABLED
[2015-01-13 10:02:18.544] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 790
[2015-01-13 10:02:18.544] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:22, clientId:102
[2015-01-13 10:02:18.548] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:02:18.552] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:18.552] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.552] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=790, carrierConf.carrierRfPort=B

[2015-01-13 10:02:18.552] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=60


00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:18.552] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:02:18.552] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:22, clientId:102
[2015-01-13 10:02:18.552] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:22
[2015-01-13 10:02:18.560] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 791
[2015-01-13 10:02:18.560] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:23, clientId:102
[2015-01-13 10:02:18.564] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:02:18.564] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:18.564] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.564] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=791, carrierConf.carrierRfPort=B
[2015-01-13 10:02:18.564] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:02:18.568] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:02:18.568] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:23, clientId:102
[2015-01-13 10:02:18.568] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:23
[2015-01-13 10:02:18.592] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 781
[2015-01-13 10:02:18.592] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:13, clientId:102
[2015-01-13 10:02:18.596] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:02:18.596] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:18.596] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.596] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=781, carrierConf.carrierRfPort=B

[2015-01-13 10:02:18.596] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20


0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:02:18.596] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:02:18.596] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:13, clientId:102
[2015-01-13 10:02:18.600] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:13
[2015-01-13 10:02:18.608] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 782
[2015-01-13 10:02:18.608] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:14, clientId:102
[2015-01-13 10:02:18.608] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=782
[2015-01-13 10:02:18.608] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:02:18.612] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:18.612] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.612] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=782, carrierConf.carrierRfPort=B
[2015-01-13 10:02:18.612] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:02:18.612] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:02:18.612] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:14, clientId:102
[2015-01-13 10:02:18.612] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:14
[2015-01-13 10:02:18.616] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-34.59[-61.50 -8.00] dB)
[2015-01-13 10:02:18.620] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:18.620] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:02:18.620] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent

[2015-01-13 10:02:18.620] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta


te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:18.624] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:18.624] trxCtrlDpdProc_0 dpdController.cc:2808 INFO:Since TX-o
n the DPD has restarted 0 times.
[2015-01-13 10:02:18.624] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFre
q: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF;
dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:02:18.624] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 780
[2015-01-13 10:02:18.628] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 0
[2015-01-13 10:02:18.628] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOnPendEvent
[2015-01-13 10:02:18.628] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:18.632] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:18.632] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:02:18.632] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 0
[2015-01-13 10:02:18.632] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:18.632] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 780 event :4
[2015-01-13 10:02:18.636] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 94250
0 (kHz), compensatedFreq = 942480 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:02:18.640] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 1, txLo: 942480, Status: dpd off, state OFF, de off, ga on; dev: 1, txFr
eq: 953400, state: OFF; dev: 2, txFreq: 0, state:
OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFre
q: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:18.640] trxCtrlDpdProc_0 dpdController.cc:2564 INFO:TX_RELEASE
resets TxRealSynthFreq
[2015-01-13 10:02:18.640] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 942480, (result: true)

[2015-01-13 10:02:18.652] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr


ierUpdateEvent successful for carrier: 780, event: 4
[2015-01-13 10:02:18.652] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :4
[2015-01-13 10:02:18.652] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(0), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:18.652] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:18.652] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:18.656] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:02:18.676] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:02:18.740] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:02:18.740] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:02:18.740] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:02:18.764] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:02:18.764] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:02:18.764] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:02:18.764] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:02:18.764] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 3, paIdInternal: 0
[2015-01-13 10:02:18.968] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOffEvent
[2015-01-13 10:02:18.968] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:02:18.968] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:12, clientId:102
[2015-01-13 10:02:18.968] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:12
[2015-01-13 10:02:18.976] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING

[2015-01-13 10:02:18.976] ledProc erciMmi.cc:221 INFO:Vii: 0x00000010


[2015-01-13 10:02:19.212] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:20.216] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:21.176] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:22.188] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:23.192] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:24.196] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:25.200] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:26.204] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:27.208] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:28.212] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:29.216] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:30.220] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,

ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4


[2015-01-13 10:02:31.024] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:32.032] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:33.036] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:34.048] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:35.052] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:17:32.736] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING END
[2015-01-13 10:17:32.736] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:17:32.736] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:17:32.736] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY
[2015-01-13 10:17:32.736] ledProc erciMmi.cc:221 INFO:Vii: 0x00000004
[2015-01-13 10:18:41.556] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:41.556] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=781
[2015-01-13 10:18:41.560] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:41.560] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:41.564] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=781, carrierConf.carrierRfPort=B
[2015-01-13 10:18:41.564] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:18:41.564] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000

[2015-01-13 10:18:41.564] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm


a =5330
[2015-01-13 10:18:41.568] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:41.568] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30d tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:41.568] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.568] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.568] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:41.568] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
1 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:41.568] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:41.572] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:41.572] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30d tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:41.572] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
1 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:41.572] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.572] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.572] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:41.572] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:3):calc_tArpToTrp:-140017[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:850 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:41.572] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14002,filterBranch:3

[2015-01-13 10:18:41.576] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0


), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:41.576] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:41.576] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:41.576] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:18:41.576] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:18:41.576] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 3, value 438
[2015-01-13 10:18:41.576] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:3 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:41.576] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2087 ns
[2015-01-13 10:18:41.576] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:41.604] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:18:41.604] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 3, CPRI port 0
[2015-01-13 10:18:41.604] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:13, clientId:102
[2015-01-13 10:18:41.612] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:41.616] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:41.616] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:18:41.628] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:41.628] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:41.644] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:18:41.716] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:18:41.716] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0

[2015-01-13 10:18:41.716] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub


scribed for faultId=0x37,txId=0
[2015-01-13 10:18:41.736] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:18:41.736] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:18:41.736] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:18:41.736] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:18:41.740] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 1, paIdInternal: 0
[2015-01-13 10:18:41.816] timeOutSrv channelSupervision.cc:490 INFO:"Vdd" channe
l supervision. Read value (19899) below exceptional low limit (26100).
[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x0 C3 0x0
[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x0 C3 0x0
[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
0
[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x84000000, C1 0x81000000, C2 0x84000000, C3 0x91000001, C4 0x88000000, C5
0x82000000, C6 0x88000000, C7 0x82000000
[2015-01-13 10:18:41.896] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:18:41.940] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4780 (closest actual 4780)
[2015-01-13 10:18:41.940] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:41.940] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 0
[2015-01-13 10:18:41.940] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:18:41.940] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:41.940] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 780 event :8

[2015-01-13 10:18:41.944] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95340


0 (kHz), compensatedFreq = 953440 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:18:41.952] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=780
[2015-01-13 10:18:41.952] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 953400, txLo: 953440, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:41.952] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:18:41.952] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 953400
[2015-01-13 10:18:41.952] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:41.952] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 953440 (result: true)
[2015-01-13 10:18:41.976] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 780, event: 8
[2015-01-13 10:18:41.976] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :8
[2015-01-13 10:18:41.976] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:41.976] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:41.980] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:41.980] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :1024
[2015-01-13 10:18:41.980] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.980] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.980] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:18:41.980] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte


dDelayDl:298956 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInternalBfnDe
lay:3673 + DpdDelay:1749
[2015-01-13 10:18:41.984] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :128
[2015-01-13 10:18:41.984] trDcProc dlDelayEventSubscriber.cc:783 INFO:isBfnAdvan
cerSetAtFirstCarrier: ON, rfPort 1
[2015-01-13 10:18:41.984] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.984] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:41.988] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:41.988] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:41.988] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:41.988] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298956 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInternalBfnDe
lay:3673 + DpdDelay:1749
[2015-01-13 10:18:41.988] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:0)tTrpToArp:30436[ns] = salCarrierReportedDelay:298956 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set

BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:41.988] trDcProc platformXDlDelayAdjust.cc:104 INFO:BFN_ADVANC
E bfnAdvanceAdjustedDelay[0] = 30436.197917
[2015-01-13 10:18:41.988] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 259 ns
[2015-01-13 10:18:42.004] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:18:42.016] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:42.020] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:42.020] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.024] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=782, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.024] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:18:42.024] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30e tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.028] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
2 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:42.032] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.032] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0

[2015-01-13 10:18:42.032] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30e tR


uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:42.032] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
2 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.032] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:7):calc_tArpToTrp:-139857[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:690 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.036] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13986,filterBranch:7
[2015-01-13 10:18:42.036] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.036] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.036] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.036] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:18:42.036] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:18:42.036] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 7, value 438
[2015-01-13 10:18:42.036] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:7 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.036] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2103 ns
[2015-01-13 10:18:42.036] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.064] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:18:42.064] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 7, CPRI port 0
[2015-01-13 10:18:42.064] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:14, clientId:102
[2015-01-13 10:18:42.092] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 781
[2015-01-13 10:18:42.092] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:13, clientId:102
[2015-01-13 10:18:42.096] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB

LED successful for carrier 782


[2015-01-13 10:18:42.096] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:14, clientId:102
[2015-01-13 10:18:42.100] - fault_manager.cc:1910 INFO:Set event PA_ON_EVENT to
time: 20000[ms], from 0x10097
[2015-01-13 10:18:42.100] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOffEvent
[2015-01-13 10:18:42.100] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:18:42.104] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:18:42.104] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:42.104] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:18:42.104] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 10:18:42.104] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:18:42.104] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:18:42.104] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:42.104] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:18:42.112] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:18:42.188] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:42.192] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:18:42.192] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:42.192] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)

[2015-01-13 10:18:42.192] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for


data. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPm
b:-34.59[-61.50 -8.00] dB)
[2015-01-13 10:18:42.192] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 780 ENABLE ev
ent
[2015-01-13 10:18:42.192] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 780 ENABLE ev
ent
[2015-01-13 10:18:42.192] trDcProc commonCsc.cc:130 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:18:42.192] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 780
[2015-01-13 10:18:42.196] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 750
[2015-01-13 10:18:42.196] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:12, clientId:102
[2015-01-13 10:18:42.196] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY END
[2015-01-13 10:18:42.200] ledProc erciMmi.cc:221 INFO:Vii: 0x00040000
[2015-01-13 10:18:42.200] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:18:42.300] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-35.06[-61.50 -8.00] dB)
[2015-01-13 10:18:42.352] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xe, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x250d C1 0x0 C2 0x0 C3 0
x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x0 C3 0x10000
[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x0 C3 0x10000
[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
88
[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x84000000, C1 0x81000000, C2 0x84000000, C3 0x91000001, C4 0x88000000, C5
0x82000000, C6 0x88000000, C7 0x92000001

[2015-01-13 10:18:42.660] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace


[2015-01-13 10:18:42.924] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.100451, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:18:43.100] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.47[-61.50 -8.00] dB)
[2015-01-13 10:18:43.100] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:43.100] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04140008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:18:43.100] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:18:43.128] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 59 deg
[2015-01-13 10:18:43.128] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 59 deg
[2015-01-13 10:18:43.128] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25649
[2015-01-13 10:18:43.132] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29199 us.
[2015-01-13 10:18:43.132] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 4 deg.
[2015-01-13 10:18:43.172] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 40533 us. IntegerDelay: 0x1d3 FracDela
y: 0x14
[2015-01-13 10:18:43.172] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x000020
00
[2015-01-13 10:18:43.172] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:43.176] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2777, currentDpdDelay[1]=1735 (0.1 ns)
[2015-01-13 10:18:43.176] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:43.180] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration

[2015-01-13 10:18:43.180] trDcProc warp17UlFreqHopBlock.cc:36 INFO:


ierId, id=(16), fb=(2), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.180] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.180] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.184] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=784, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.188] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.188] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.188] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.192] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.192] trDcProc delayCommHandler.cc:312 INFO:carrier:0x310 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.192] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:43.192] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.192] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:43.192] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:43.192] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.192] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.192] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
4 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.192] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.196] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67

0
[2015-01-13 10:18:43.196] trDcProc delayCommHandler.cc:312 INFO:carrier:0x310 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.196] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
4 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.196] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.196] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:2
[2015-01-13 10:18:43.200] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns
[2015-01-13 10:18:43.200] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298942 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter

nalBfnDelay:3673 + DpdDelay:1735
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30434[ns] = salCarrierReportedDelay:298942 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 261 ns
[2015-01-13 10:18:43.216] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:18:43.228] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:43.228] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:18:43.228] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:16, clientId:102
[2015-01-13 10:18:43.248] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.248] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:43.252] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:43.252] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(17), fb=(6), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.252] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.252] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.256] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=785, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.260] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.260] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.260] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.264] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.264] trDcProc delayCommHandler.cc:312 INFO:carrier:0x311 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390

[2015-01-13 10:18:43.264] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36


73 [0.1ns]
[2015-01-13 10:18:43.264] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.264] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.264] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
5 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.264] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.264] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.264] trDcProc delayCommHandler.cc:312 INFO:carrier:0x311 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.268] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
5 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.268] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:6):calc_tArpToTrp:-139937[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.268] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13994,filterBranch:6
[2015-01-13 10:18:43.272] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.272] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.272] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.272] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:18:43.272] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:18:43.272] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 6, value 438
[2015-01-13 10:18:43.272] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:6 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.272] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s

et tVldbUl to 2095 ns
[2015-01-13 10:18:43.272] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.300] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:18:43.300] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 6, CPRI port 0
[2015-01-13 10:18:43.300] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:17, clientId:102
[2015-01-13 10:18:43.324] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 784
[2015-01-13 10:18:43.324] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:16, clientId:102
[2015-01-13 10:18:43.328] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 785
[2015-01-13 10:18:43.328] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:17, clientId:102
[2015-01-13 10:18:43.388] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=1
[2015-01-13 10:18:43.392] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.396] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(19), fb=(1), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.396] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.396] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.400] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=787, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.400] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.400] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.404] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.404] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.404] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.404] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36

73 [0.1ns]
[2015-01-13 10:18:43.404] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.404] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.404] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
7 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.404] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.408] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.408] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.408] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
7 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.408] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:1):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.408] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:1
[2015-01-13 10:18:43.412] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 1, value 438
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:1 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns

[2015-01-13 10:18:43.412] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg


Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.440] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:18:43.440] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 1, CPRI port 0
[2015-01-13 10:18:43.440] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:19, clientId:102
[2015-01-13 10:18:43.456] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=3
[2015-01-13 10:18:43.460] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.460] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(20), fb=(5), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.460] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.460] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.468] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=788, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.468] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.468] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.468] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.472] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.472] trDcProc delayCommHandler.cc:312 INFO:carrier:0x314 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.472] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:43.472] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.472] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.472] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78

8 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673


[2015-01-13 10:18:43.472] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.476] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.476] trDcProc delayCommHandler.cc:312 INFO:carrier:0x314 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.476] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
8 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.476] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:5):calc_tArpToTrp:-139937[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.476] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13994,filterBranch:5
[2015-01-13 10:18:43.480] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.480] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.480] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.480] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:18:43.480] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:18:43.480] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 5, value 438
[2015-01-13 10:18:43.480] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:5 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.480] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2095 ns
[2015-01-13 10:18:43.480] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.508] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:18:43.508] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 5, CPRI port 0
[2015-01-13 10:18:43.508] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:20, clientId:102

[2015-01-13 10:18:43.532] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB


LED successful for carrier 787
[2015-01-13 10:18:43.532] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:19, clientId:102
[2015-01-13 10:18:43.536] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 788
[2015-01-13 10:18:43.536] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:20, clientId:102
[2015-01-13 10:18:43.552] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xe, mplPwrC0 0x1f015ab C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0xc3
04740 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x250d C1 0x0
C2 0x0 C3 0x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0xf4d5afa pa1Adj 0x47a4
[2015-01-13 10:18:43.576] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=0
[2015-01-13 10:18:43.580] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.584] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(22), fb=(0), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.584] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.584] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.588] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=790, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.588] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.588] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.592] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.592] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.592] trDcProc delayCommHandler.cc:312 INFO:carrier:0x316 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.592] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:43.592] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.592] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(

80)
[2015-01-13 10:18:43.592] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
0 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:312 INFO:carrier:0x316 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.596] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
0 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.596] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:0):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.600] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:0
[2015-01-13 10:18:43.600] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 0, value 438
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:0 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.604] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns
[2015-01-13 10:18:43.604] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:43.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 0, CPRI port 0

[2015-01-13 10:18:43.632] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE


ACTIVATE for carrierId:22, clientId:102
[2015-01-13 10:18:43.648] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=2
[2015-01-13 10:18:43.652] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.656] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(23), fb=(4), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:43.656] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:43.656] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:43.660] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=791, carrierConf.carrierRfPort=B
[2015-01-13 10:18:43.660] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:18:43.660] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:43.664] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.664] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.664] trDcProc delayCommHandler.cc:312 INFO:carrier:0x317 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.668] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:43.668] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.668] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.668] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
1 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.668] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.668] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:43.668] trDcProc delayCommHandler.cc:312 INFO:carrier:0x317 tR

uUl:125390[0.1 ns] = tRuInternalUlDb:125390


[2015-01-13 10:18:43.668] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
1 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.672] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:4):calc_tArpToTrp:-139937[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.672] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13994,filterBranch:4
[2015-01-13 10:18:43.672] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.676] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.676] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.676] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:18:43.676] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:18:43.676] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 4, value 438
[2015-01-13 10:18:43.676] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:4 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.676] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2095 ns
[2015-01-13 10:18:43.676] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.704] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:18:43.704] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 4, CPRI port 0
[2015-01-13 10:18:43.704] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:23, clientId:102
[2015-01-13 10:18:43.728] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 790
[2015-01-13 10:18:43.728] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:22, clientId:102
[2015-01-13 10:18:43.732] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 791

[2015-01-13 10:18:43.732] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC


TIVATE for carrierId:23, clientId:102
[2015-01-13 10:18:44.556] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xe, mplPwrC0 0x1efe72c C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0xc3
35f2c C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x250d C1 0x0
C2 0x0 C3 0x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0xf513df7 pa1Adj 0x47a4
[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
ff
[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x94000002, C1 0x91000002, C2 0x94000001, C3 0x91000001, C4 0x98000002, C5
0x92000002, C6 0x98000001, C7 0x92000001
[2015-01-13 10:18:44.628] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:18:45.560] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xe, mplPwrC0 0x1eefadc C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0xc3
05f06 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x250d C1 0x0
C2 0x0 C3 0x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0xf4d78ca pa1Adj 0x47a4
[2015-01-13 10:18:46.564] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x3,
fabEnCd 0x0, fabForce 0xe, mplPwrC0 0x1ef80a4 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0xc2
c4472 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x250d C1 0x0
C2 0x0 C3 0x0, ncoC0 0x8010 C1 0x0 C2 0x0 C3 0x0, pmPa1 0xf4852a8 pa1Adj 0x47a4
[2015-01-13 10:18:48.244] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:48.248] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:48.248] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 1
[2015-01-13 10:18:48.248] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:18:48.248] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:48.248] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:18:48.252] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 783 event :8

[2015-01-13 10:18:48.252] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT


to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.256] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95550
0 (kHz), compensatedFreq = 955520 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:18:48.264] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=783
[2015-01-13 10:18:48.264] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:48.308] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:48.312] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955500, txLo: 955520, Status: dpd on, state TUNED, d
e on, ga on; dev: 1, txFreq: 953400, state: ON; de
v: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, s
tate: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7,
txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:18:48.312] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:18:48.312] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:18:48.312] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:18:48.312] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.380] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.380] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.380] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80100008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:18:48.380] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib

rate_result_phase: 58 deg
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25780
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29866 us.
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 30399 us. IntegerDelay: 0x1d3 FracDela
y: 0x2c
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fa
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2753, currentDpdDelay[1]=1720 (0.1 ns)
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298927 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1720
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298927 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0

[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se


tTotalDelay set vldb to 262 ns
[2015-01-13 10:18:48.464] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:48.512] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 783, event: 8
[2015-01-13 10:18:48.512] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :8
[2015-01-13 10:18:48.512] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:48.552] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:48.556] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:48.556] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:48.560] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:18:48.560] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :1024
[2015-01-13 10:18:48.564] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:48.564] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.564] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.564] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298968 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1720
[2015-01-13 10:18:48.568] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :128
[2015-01-13 10:18:48.568] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a3c, rfPort 1
[2015-01-13 10:18:48.568] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]

[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37


), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.568] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.572] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298968 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1720
[2015-01-13 10:18:48.572] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298968 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:48.572] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 258 ns
[2015-01-13 10:18:48.584] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:15, clientId:102
[2015-01-13 10:18:48.592] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:48.600] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:48.600] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 2
[2015-01-13 10:18:48.600] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:18:48.600] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:48.600] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:18:48.600] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri

erUpdateEvent successful for carrier: 786 event :8


[2015-01-13 10:18:48.604] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.608] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd on, state TUNED, d
e on, ga on; dev: 1, txFreq: 953400, state: ON; de
v: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq:
0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; de
v: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, st
ate: OFF;
[2015-01-13 10:18:48.608] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:18:48.608] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:18:48.608] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:18:48.608] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.676] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.676] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:48.676] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80100008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:18:48.676] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:18:48.708] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 57 deg
[2015-01-13 10:18:48.708] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 57 deg
[2015-01-13 10:18:48.708] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25646
[2015-01-13 10:18:48.708] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 33066 us.
[2015-01-13 10:18:48.708] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.

[2015-01-13 10:18:48.736] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed


Delay estimation with training signal in 24266 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:18:48.736] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
f5
[2015-01-13 10:18:48.736] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.740] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.744] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:48.744] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.744] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.756] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:48.760] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.760] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:18:48.772] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:48.844] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 786, event: 8
[2015-01-13 10:18:48.844] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :8
[2015-01-13 10:18:48.844] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:48.892] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:48.892] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:48.892] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:48.896] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:18:48.900] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :1024

[2015-01-13 10:18:48.900] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36


73 [0.1ns]
[2015-01-13 10:18:48.900] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.900] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.904] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1721
[2015-01-13 10:18:48.904] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :128
[2015-01-13 10:18:48.904] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a3c, rfPort 1
[2015-01-13 10:18:48.904] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:48.904] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:48.904] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.904] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.908] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:48.908] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.908] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.908] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1721
[2015-01-13 10:18:48.912] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set

BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:48.912] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 258 ns
[2015-01-13 10:18:48.924] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:18:48.932] trDcProc powerClassCtrl.cc:487 INFO:totGsmCarrierPwrDb
m :4892 is higher than selected higherPowerClass:4780, maxPowerClass:4900 will b
e set
[2015-01-13 10:18:48.932] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4900
[2015-01-13 10:18:48.940] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.948] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:18:48.960] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:18:48.960] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.980] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.988] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298956 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1749
[2015-01-13 10:18:48.988] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30436[ns] = salCarrierReportedDelay:298956 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.988] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 259 ns
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:49.000] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298997 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1749
[2015-01-13 10:18:49.004] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30440[ns] = salCarrierReportedDelay:298997 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:49.004] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 255 ns

[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3673 [0.1ns]
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:49.016] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298997 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1749
[2015-01-13 10:18:49.020] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30440[ns] = salCarrierReportedDelay:298997 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:49.020] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 255 ns
[2015-01-13 10:18:49.100] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:18:49.100] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:18:49.100] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:18:49.120] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:18:49.124] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:18:49.124] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:18:49.124] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO

[2015-01-13 10:18:49.124] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get


ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:18:49.332] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 953400, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.332] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:18:49.332] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 953400
[2015-01-13 10:18:49.332] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:49.332] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:49.336] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of

configured carriers: tx: 2, rx: 0


[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:18:49.336] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:49.336] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:49.340] trDcProc dlCtrl.cc:228 INFO:Carrier id 780, FilterBran
ch id 0 is added into reEnabledCarrierFBList
[2015-01-13 10:18:49.340] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:18:49.340] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:18:49.340] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:18:49.340] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:18:49.340] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 10:18:49.340] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.340] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, t
xFreq: 0, state: OFF;
[2015-01-13 10:18:49.340] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:49.340] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:18:49.340] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.348] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:18:49.428] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x

718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak


New = 0x729ACD00.
[2015-01-13 10:18:49.428] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:18:49.428] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.432] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:18:49.432] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-12.98[-42.55 -8.00], DpdPma:-16.07[-16.48 -15.48], Pmb:-12.98, TorPm
b:-12.98[-47.98 -8.00] dB)
[2015-01-13 10:18:49.432] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:18:49.432] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:49.432] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 10:18:49.432] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 10:18:49.432] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:49.436] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:18:49.436] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :8
[2015-01-13 10:18:49.440] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 7, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state WAIT_FO
R_DATA, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev
: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF; dev: 6, txFreq:
0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev:
8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.440] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 10:18:49.440] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 10:18:49.440] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:18:49.440] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.

[2015-01-13 10:18:49.440] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr


lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955520 (result: true)
[2015-01-13 10:18:49.472] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0xe, mplPwrC0 0x1f47aaf C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0xbd
3bbb2 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x2487 C1 0x2
4d5 C2 0x24d5 C3 0x0, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xed7073
5 pa1Adj 0x47a4
[2015-01-13 10:18:49.496] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-33.48[-61.50 -8.00] dB)
[2015-01-13 10:18:49.548] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 8
[2015-01-13 10:18:49.548] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :8
[2015-01-13 10:18:49.548] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:49.604] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:49.608] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:49.608] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:49.612] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:18:49.612] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :1024
[2015-01-13 10:18:49.616] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:49.616] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.616] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.616] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298997 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1749
[2015-01-13 10:18:49.620] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :128
[2015-01-13 10:18:49.620] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a1e, rfPort 1

[2015-01-13 10:18:49.620] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan


cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:49.620] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:49.620] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.620] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.624] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:49.624] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:49.624] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.624] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298997 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3673 + DpdDelay:1749
[2015-01-13 10:18:49.624] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30440[ns] = salCarrierReportedDelay:298997 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:49.624] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 255 ns
[2015-01-13 10:18:49.640] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:21, clientId:102
[2015-01-13 10:18:49.660] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.660] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:18:49.660] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 783
[2015-01-13 10:18:49.660] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097

[2015-01-13 10:18:49.668] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev


= 3; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500
, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.668] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.668] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.668] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 10:18:49.668] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 10:18:49.668] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:18:49.668] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 783
[2015-01-13 10:18:49.672] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:15, clientId:102
[2015-01-13 10:18:49.684] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.684] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:18:49.684] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 786
[2015-01-13 10:18:49.684] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.684] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.684] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.688] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.688] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.

[2015-01-13 10:18:49.688] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt


rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 10:18:49.688] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 10:18:49.688] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:18:49.688] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 786
[2015-01-13 10:18:49.692] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:18, clientId:102
[2015-01-13 10:18:49.704] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.704] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 10:18:49.704] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 789
[2015-01-13 10:18:49.704] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.704] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OF
F; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.704] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.708] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.708] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:18:49.708] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 10:18:49.708] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 10:18:49.708] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 10:18:49.708] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.

[2015-01-13 10:18:49.708] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB


LED successful for carrier 789
[2015-01-13 10:18:49.712] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 10:18:49.712] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:21, clientId:102
[2015-01-13 10:18:50.108] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.092089, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:18:50.284] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.46[-61.50 -8.00] dB)
[2015-01-13 10:18:50.284] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:18:50.284] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04140008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:18:50.284] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:18:50.312] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 10:18:50.316] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 10:18:50.316] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24773
[2015-01-13 10:18:50.316] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29733 us.
[2015-01-13 10:18:50.316] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:18:50.340] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24800 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:18:50.340] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fc
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga

Delay:3673 [0.1ns]
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.380] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga

Delay:3673 [0.1ns]
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:18:50.412] dlCtrlProc dlCtrl.cc:312 INFO:DlCtrl::removeReEnableCa
rrierFBIfReceived: remove the filterBranchId = 0 from the reEnabedCarrierFBList
list upon receipt of TRX_TX_ON_IND
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 10:18:50.476] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eea18b C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
a255a C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0e
281d pa1Adj 0x4779

[2015-01-13 10:18:51.480] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,


fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efbc49 C1 0x12136d2 C2 0xcbe84b C3 0x0, p
mPa0C0 0x8dbb674 C1 0x3b0be9c C2 0x10ca065 C3 0x0,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x10dba5a7 pa1Adj 0x4779
[2015-01-13 10:18:52.488] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effe42 C1 0x0 C2 0x1f0a3ad C3 0x0, pmPa0C
0 0x8de0c36 C1 0x38623e4 C2 0x5fb2ce6 C3 0x0, pa0C
0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0
x8008, pmPa1 0x16be9fb3 pa1Adj 0x4779
[2015-01-13 10:18:53.500] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effcd5 C1 0x0 C2 0x5fb7c C3 0x0, pmPa0C0
0x8d9e82a C1 0x3547698 C2 0x5f7fa34 C3 0x0, pa0C0A
dj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8
008, pmPa1 0x16721976 pa1Adj 0x4779
[2015-01-13 10:18:54.504] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2045ab4 C1 0x146ae49 C2 0x0 C3 0x0, pmPa0C
0 0x8dde32a C1 0x44b7def C2 0x3ac1c80 C3 0x0, pa0C
0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0
x8008, pmPa1 0x14ce704d pa1Adj 0x4779
[2015-01-13 10:18:55.508] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0a4a2 C1 0x16eb30c C2 0x1eefa51 C3 0x0,
pmPa0C0 0x8dae95e C1 0x3e8aebd C2 0x3dd2443 C3 0x1
0bfaa5, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2
0x8008 C3 0x8008, pmPa1 0x15c81eab pa1Adj 0x4779
[2015-01-13 10:18:56.516] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f00515 C1 0x0 C2 0xcb0d0 C3 0x0, pmPa0C0
0x8dc272a C1 0x2b261cf C2 0x29a702d C3 0x21a152e,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x140a88c6 pa1Adj 0x4779
[2015-01-13 10:18:57.556] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ebb7dc C1 0x0 C2 0x162b6d C3 0x0, pmPa0C0
0x8da886d C1 0x1d46990 C2 0x20b9701 C3 0x194f3a2,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x11aacaaf pa1Adj 0x4779
[2015-01-13 10:18:58.420] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effb50 C1 0xcccab4 C2 0x93f66f C3 0x51b56
1, pmPa0C0 0x8dcab1c C1 0x216c340 C2 0x25c67a2 C3
0x1a67ed0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008
C2 0x8008 C3 0x8008, pmPa1 0x127eb7f4 pa1Adj 0x4779
[2015-01-13 10:18:59.424] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0a49a C1 0x23816b C2 0x238379 C3 0x0, pm
Pa0C0 0x8d856e5 C1 0x1c2eb7f C2 0x1b8a7e9 C3 0x86c
ffe, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x
8008 C3 0x8008, pmPa1 0xff6fe78 pa1Adj 0x4779
[2015-01-13 10:19:00.428] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f62753 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
94d5d C1 0x11a93d1 C2 0x1d17e61 C3 0x43c51b, pa0C0
Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x
8008, pmPa1 0xeede828 pa1Adj 0x4779

[2015-01-13 10:19:01.432] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,


fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f012bb C1 0x2d566 C2 0xca2b4 C3 0x0, pmPa
0C0 0x8d85f94 C1 0x89e366 C2 0xeb382d C3 0xe0ab4f,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0xde38002 pa1Adj 0x4779
[2015-01-13 10:19:02.484] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef8121 C1 0x291e05 C2 0x1627282 C3 0x0, p
mPa0C0 0x8db29f0 C1 0x11fa290 C2 0x1228d1c C3 0xfb
4de2, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0
x8008 C3 0x8008, pmPa1 0xf00a168 pa1Adj 0x4779
[2015-01-13 10:19:03.496] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec417e C1 0x1c43fa2 C2 0x2d3522 C3 0x4b90
6d, pmPa0C0 0x8d90f82 C1 0x1c7f7bb C2 0x120fc0c C3
0xfbd7c7, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008
C2 0x8008 C3 0x8008, pmPa1 0xfc9a9ea pa1Adj 0x4779
[2015-01-13 10:19:04.500] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ed6a28 C1 0xcb4a8 C2 0xbf6359 C3 0x7f24da
, pmPa0C0 0x8db55cd C1 0x64abc9 C2 0x274cf43 C3 0x
304f41, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2
0x8008 C3 0x8008, pmPa1 0xec65b7e pa1Adj 0x4779
[2015-01-13 10:19:05.504] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f044ac C1 0x10c372 C2 0x0 C3 0x0, pmPa0C0
0x8dc4fda C1 0xc072e2 C2 0x19ab6d5 C3 0x163949d,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0xf9bbde5 pa1Adj 0x4779
[2015-01-13 10:19:06.508] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effab7 C1 0x13b8e9 C2 0x2d0f0b C3 0x4cd3a
5, pmPa0C0 0x8cdb51e C1 0x37acc4 C2 0x144b050 C3 0
xcba16d, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C
2 0x8008 C3 0x8008, pmPa1 0xdc144f6 pa1Adj 0x4779
[2015-01-13 10:19:07.556] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ed5ecb C1 0x38100 C2 0x58ff6 C3 0x6e36f3,
pmPa0C0 0x8d9d4d0 C1 0x3371ee C2 0x1aed85c C3 0x4
5da3d, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2
0x8008 C3 0x8008, pmPa1 0xda9af1d pa1Adj 0x4779
[2015-01-13 10:19:08.364] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef8493 C1 0x2f7ba C2 0xe0e719 C3 0x180d44
b, pmPa0C0 0x8dae1bf C1 0x3daeb4 C2 0x12f59c6 C3 0
xbc4d71, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C
2 0x8008 C3 0x8008, pmPa1 0xdb597a1 pa1Adj 0x4779
[2015-01-13 10:40:31.632] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:31.632] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0xf
[2015-01-13 10:40:31.636] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 1; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFre

q: 955500, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: ON; dev: 8
, txFreq: 0, state: OFF;
[2015-01-13 10:40:31.636] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 780
[2015-01-13 10:40:31.640] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = 0 (gainOffset:0 + gainMargin:122)
[2015-01-13 10:40:31.640] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:31.640] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:40:31.640] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:40:31.644] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 780 event :4
[2015-01-13 10:40:31.644] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x1, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x0 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:31.684] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 1, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 953400, state: OFF; dev: 2, txFreq: 0, state:
OFF; dev: 3, txFreq: 955500, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, t
xFreq: 955500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500,
state: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:31.684] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 955500
[2015-01-13 10:40:31.748] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:31.752] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.

[2015-01-13 10:40:31.752] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced


idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:31.752] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:31.780] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 57 deg
[2015-01-13 10:40:31.780] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 57 deg
[2015-01-13 10:40:31.780] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24945
[2015-01-13 10:40:31.780] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 30533 us.
[2015-01-13 10:40:31.780] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:40:31.808] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24266 us. IntegerDelay: 0x1d3 FracDela
y: 0x2c
[2015-01-13 10:40:31.808] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:40:31.808] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2753, currentDpdDelay[1]=1720 (0.1 ns)
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:40:31.812] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR


uReportedDelayDl:298965 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3670 + DpdDelay:1720
[2015-01-13 10:40:31.816] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298965 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:31.816] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:31.828] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298965 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3670 + DpdDelay:1720
[2015-01-13 10:40:31.832] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298965 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:31.832] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]

[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3670 [0.1ns]
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1254), hardDelay:(834)
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:31.844] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298965 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3670 + DpdDelay:1720
[2015-01-13 10:40:31.848] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298965 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:31.848] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:31.860] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955520, (result: true)
[2015-01-13 10:40:31.924] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 780, event: 4
[2015-01-13 10:40:31.924] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :4
[2015-01-13 10:40:31.924] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:31.976] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:40:31.976] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(0), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:31.976] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:31.976] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1

[2015-01-13 10:40:31.980] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven


t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:31.988] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:31.988] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:12, clientId:102
[2015-01-13 10:40:31.988] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:12
[2015-01-13 10:40:31.988] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 781
[2015-01-13 10:40:31.988] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:13, clientId:102
[2015-01-13 10:40:31.992] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:40:31.996] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:31.996] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:31.996] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=781, carrierConf.carrierRfPort=B
[2015-01-13 10:40:31.996] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:40:32.000] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:32.000] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:13, clientId:102
[2015-01-13 10:40:32.000] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:13
[2015-01-13 10:40:32.012] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 782
[2015-01-13 10:40:32.012] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:14, clientId:102
[2015-01-13 10:40:32.016] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:40:32.020] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:32.020] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:32.020] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=782, carrierConf.carrierRfPort=B

[2015-01-13 10:40:32.020] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20


0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:40:32.020] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:32.020] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:14, clientId:102
[2015-01-13 10:40:32.020] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:14
[2015-01-13 10:40:32.648] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xc,
fabEnCd 0xf, fabForce 0x1, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x2014 C2 0x2014 C
3 0x2014, ncoC0 0x0 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:33.652] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xc,
fabEnCd 0xf, fabForce 0x1, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x2014 C2 0x2014 C
3 0x2014, ncoC0 0x0 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:34.188] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:34.188] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:34.224] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 3; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
5500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state:
ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: ON; dev: 8, tx
Freq: 0, state: OFF;
[2015-01-13 10:40:34.224] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 783
[2015-01-13 10:40:34.228] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.228] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:15, clientId:102
[2015-01-13 10:40:34.228] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:40:34.228] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.228] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:40:34.228] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:40:34.228] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri

erUpdateEvent successful for carrier: 783 event :4


[2015-01-13 10:40:34.232] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 3, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFre
q: 955500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, sta
te: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.232] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 955500
[2015-01-13 10:40:34.296] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.328] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 57 deg
[2015-01-13 10:40:34.328] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 57 deg
[2015-01-13 10:40:34.328] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25085
[2015-01-13 10:40:34.328] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 30399 us.
[2015-01-13 10:40:34.328] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:40:34.356] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24266 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:40:34.356] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:40:34.356] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]

[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.360] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298971 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1721
[2015-01-13 10:40:34.364] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298971 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.364] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela

y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor


tDelay:(80)
[2015-01-13 10:40:34.376] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298971 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1721
[2015-01-13 10:40:34.380] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298971 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.380] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:34.392] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520, (result: true)
[2015-01-13 10:40:34.444] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 783, event: 4
[2015-01-13 10:40:34.444] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :4
[2015-01-13 10:40:34.444] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:34.488] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:40:34.488] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(1), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:34.488] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:34.492] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:34.492] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:34.496] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.496] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:15, clientId:102
[2015-01-13 10:40:34.500] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:15
[2015-01-13 10:40:34.500] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:34.500] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB

3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:34.504] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 7; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0,
state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: ON; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF; dev: 8, txFreq
: 0, state: OFF;
[2015-01-13 10:40:34.504] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 789
[2015-01-13 10:40:34.504] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.504] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:21, clientId:102
[2015-01-13 10:40:34.508] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:40:34.508] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.508] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:40:34.508] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :4
[2015-01-13 10:40:34.508] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 7, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95
5500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: O
FF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.508] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 955500
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib

rate_result_phase status ok: step 0: 57 deg


[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 57 deg
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25097
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29733 us.
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:40:34.632] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24533 us. IntegerDelay: 0x1d3 FracDela
y: 0x2c
[2015-01-13 10:40:34.636] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:40:34.636] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2753, currentDpdDelay[1]=1720 (0.1 ns)
[2015-01-13 10:40:34.636] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.636] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.636] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298970 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1720
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298970 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT

oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.


1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.640] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:40:34.652] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955520, (result: true)
[2015-01-13 10:40:34.688] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 4
[2015-01-13 10:40:34.688] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :4
[2015-01-13 10:40:34.688] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:34.724] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:40:34.724] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(3), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:34.724] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:34.724] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:34.728] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:34.764] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:40:34.776] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:40:34.776] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:40:34.780] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:40:34.780] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:34.780] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:34.796] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD

elay:(37), jbDelay:(1259), hardDelay:(834)


[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.800] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1749
[2015-01-13 10:40:34.804] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30440[ns] = salCarrierReportedDelay:298999 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.804] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 255 ns
[2015-01-13 10:40:34.880] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:40:34.880] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:40:34.880] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:40:34.904] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:40:34.904] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:40:34.904] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:40:34.904] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:40:34.908] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:40:34.940] timeOutSrv channelSupervision.cc:490 INFO:"IDpa2" chan

nel supervision. Read value (3) below exceptional low limit (10).
[2015-01-13 10:40:34.944] timeOutSrv channelSupervision.cc:490 INFO:"IMpa0" chan
nel supervision. Read value (-8) below exceptional low limit (500).
[2015-01-13 10:40:34.948] timeOutSrv channelSupervision.cc:490 INFO:"IDpa0" chan
nel supervision. Read value (1) below exceptional low limit (100).
[2015-01-13 10:40:34.948] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x3, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x2014 C3 0
x0, ncoC0 0x0 C1 0x0 C2 0x8008 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955500
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:35.112] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 10:40:35.112] trDcProc dlCtrl.cc:228 INFO:Carrier id 786, FilterBran
ch id 2 is added into reEnabledCarrierFBList
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:40:35.112] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:40:35.112] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:35.112] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 786
[2015-01-13 10:40:35.112] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;

dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0,


state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.112] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:40:35.124] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:40:35.200] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:35.204] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:40:35.204] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:40:35.204] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:40:35.204] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.45[-i -8.00] d
B)
[2015-01-13 10:40:35.204] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:40:35.204] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:35.204] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:21, clientId:102
[2015-01-13 10:40:35.204] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:21
[2015-01-13 10:40:35.204] trDcProc dlCtrl.cc:261 INFO:DlCtrl::carrierUpdateEvent
: remove the filter branch id 2 from the reEnabledCarrierFBList upon receipt of
event CR_SUBSCRIPTION_EVENT_CARRIER_DISABLED
[2015-01-13 10:40:35.204] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 784
[2015-01-13 10:40:35.204] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:16, clientId:102
[2015-01-13 10:40:35.208] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2

[2015-01-13 10:40:35.212] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:35.212] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.212] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=784, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.212] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:40:35.212] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:40:35.212] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:16, clientId:102
[2015-01-13 10:40:35.212] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:16
[2015-01-13 10:40:35.216] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:35.216] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:35.316] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:40:35.316] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:40:35.320] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:40:35.320] trxCtrlDpdProc_0 dpdController.cc:2808 INFO:Since TX-o
n the DPD has restarted 0 times.
[2015-01-13 10:40:35.320] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 5; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0,
state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF;
dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:40:35.320] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 786
[2015-01-13 10:40:35.320] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 0
[2015-01-13 10:40:35.324] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.324] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0

[2015-01-13 10:40:35.328] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO


STATUS OFF
[2015-01-13 10:40:35.328] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:40:35.328] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 0
[2015-01-13 10:40:35.328] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:35.328] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 786 event :4
[2015-01-13 10:40:35.332] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 94250
0 (kHz), compensatedFreq = 942480 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:40:35.336] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=786
[2015-01-13 10:40:35.336] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:35.368] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:40:35.368] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 5, txLo: 942480, Status: dpd off, state OFF, de off, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95
5500, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:35.368] trxCtrlDpdProc_0 dpdController.cc:2564 INFO:TX_RELEASE
resets TxRealSynthFreq
[2015-01-13 10:40:35.368] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 942480, (result: true)
[2015-01-13 10:40:35.380] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 786, event: 4
[2015-01-13 10:40:35.380] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :4
[2015-01-13 10:40:35.380] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(2), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:35.380] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:35.380] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.384] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.404] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD

delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)


[2015-01-13 10:40:35.472] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:40:35.472] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:40:35.472] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:40:35.496] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:40:35.496] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:40:35.496] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:40:35.496] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:40:35.496] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 3, paIdInternal: 0
[2015-01-13 10:40:35.700] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOffEvent
[2015-01-13 10:40:35.700] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:40:35.700] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:18, clientId:102
[2015-01-13 10:40:35.700] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:18
[2015-01-13 10:40:35.700] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 790
[2015-01-13 10:40:35.700] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:22, clientId:102
[2015-01-13 10:40:35.704] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:40:35.708] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.708] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.708] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=790, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.708] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:40:35.708] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven

t: setting center frequency to 942500 and vector width to 35000


[2015-01-13 10:40:35.708] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:22, clientId:102
[2015-01-13 10:40:35.708] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:22
[2015-01-13 10:40:35.712] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 787
[2015-01-13 10:40:35.712] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:19, clientId:102
[2015-01-13 10:40:35.712] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:40:35.716] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.716] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.716] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=787, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.716] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:40:35.716] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.716] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:19, clientId:102
[2015-01-13 10:40:35.716] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:19
[2015-01-13 10:40:35.716] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 785
[2015-01-13 10:40:35.716] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:17, clientId:102
[2015-01-13 10:40:35.720] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING
[2015-01-13 10:40:35.720] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:40:35.724] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.724] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.724] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=785, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.724] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=60

00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500


[2015-01-13 10:40:35.724] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.724] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:17, clientId:102
[2015-01-13 10:40:35.724] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:17
[2015-01-13 10:40:35.724] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 791
[2015-01-13 10:40:35.724] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:23, clientId:102
[2015-01-13 10:40:35.728] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:40:35.728] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.728] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.728] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=791, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.728] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:40:35.728] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.732] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:23, clientId:102
[2015-01-13 10:40:35.732] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:23
[2015-01-13 10:40:35.732] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 788
[2015-01-13 10:40:35.732] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:20, clientId:102
[2015-01-13 10:40:35.732] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:40:35.736] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.736] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.736] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=788, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.736] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=60

00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500


[2015-01-13 10:40:35.736] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.736] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:20, clientId:102
[2015-01-13 10:40:35.736] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:20
[2015-01-13 10:40:35.736] ledProc erciMmi.cc:221 INFO:Vii: 0x00000010
[2015-01-13 10:40:36.364] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:37.380] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:38.384] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:39.404] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:40.212] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:41.216] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:42.220] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:43.232] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:44.236] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:45.240] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0

C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,


ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:46.244] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:47.248] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:48.252] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:49.256] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:50.064] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:51.068] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:52.072] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:53.076] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:54.080] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:55.080] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:56.084] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:41:19.408] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING END

[2015-01-13 10:41:19.408] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000


[2015-01-13 10:41:19.408] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:41:19.408] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY
[2015-01-13 10:41:19.408] ledProc erciMmi.cc:221 INFO:Vii: 0x00000004
[2015-01-13 10:41:19.968] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:19.972] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=781
[2015-01-13 10:41:19.972] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:19.972] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:19.976] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=781, carrierConf.carrierRfPort=B
[2015-01-13 10:41:19.976] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:41:19.976] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:19.980] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:19.980] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:19.980] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30d tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:19.980] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:19.980] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:19.980] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:19.980] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
1 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:19.980] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:19.984] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67

0
[2015-01-13 10:41:19.984] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30d tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:19.984] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
1 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:19.984] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:3):calc_tArpToTrp:-140012[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:850 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14001,filterBranch:3
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 3, value 438
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:3 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2088 ns
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:20.016] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0

[2015-01-13 10:41:20.016] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin


k, fb 3, CPRI port 0
[2015-01-13 10:41:20.016] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:13, clientId:102
[2015-01-13 10:41:20.032] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:20.032] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:20.032] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:20.040] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=782, carrierConf.carrierRfPort=B
[2015-01-13 10:41:20.040] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:41:20.040] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:20.040] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:20.044] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:20.044] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30e tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:20.044] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:20.044] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:20.044] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:20.044] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
2 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:20.044] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:20.044] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:20.044] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30e tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:20.044] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78

2 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe


layUl:6000
[2015-01-13 10:41:20.048] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:7):calc_tArpToTrp:-139852[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:690 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:20.048] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13985,filterBranch:7
[2015-01-13 10:41:20.052] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:20.052] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:20.052] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:20.052] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:41:20.052] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:41:20.052] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 7, value 438
[2015-01-13 10:41:20.052] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:7 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:20.052] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2104 ns
[2015-01-13 10:41:20.052] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:20.080] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:41:20.080] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 7, CPRI port 0
[2015-01-13 10:41:20.080] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:14, clientId:102
[2015-01-13 10:41:20.104] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 781
[2015-01-13 10:41:20.104] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:13, clientId:102
[2015-01-13 10:41:20.108] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 782
[2015-01-13 10:41:20.108] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:14, clientId:102

[2015-01-13 10:41:20.156] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI


SUAL_INDICATION_CFM: visualized state: O BUSY END
[2015-01-13 10:41:20.164] ledProc erciMmi.cc:221 INFO:Vii: 0x00040000
[2015-01-13 10:41:20.164] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:41:21.196] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:21.200] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:21.204] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:21.204] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(19), fb=(2), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.204] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:21.204] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.208] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=787, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.208] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:21.208] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.212] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.212] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:21.212] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.212] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:21.212] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:21.212] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.212] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
7 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:21.212] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm

a =5330
[2015-01-13 10:41:21.216] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:21.216] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.216] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
7 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.216] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140112[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.216] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14011,filterBranch:2
[2015-01-13 10:41:21.220] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2078 ns
[2015-01-13 10:41:21.220] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.248] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.248] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:41:21.248] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:19, clientId:102
[2015-01-13 10:41:21.264] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097

[2015-01-13 10:41:21.268] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w


ith frequency hopping enabled found
[2015-01-13 10:41:21.272] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:21.272] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(20), fb=(6), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.272] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:21.272] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.276] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=788, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.276] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:21.276] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.280] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.280] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:21.280] trDcProc delayCommHandler.cc:312 INFO:carrier:0x314 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.280] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:21.280] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:21.280] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.280] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
8 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:21.284] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.284] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:21.284] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:21.284] trDcProc delayCommHandler.cc:312 INFO:carrier:0x314 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390

[2015-01-13 10:41:21.284] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78


8 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.284] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:6):calc_tArpToTrp:-139932[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.288] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13993,filterBranch:6
[2015-01-13 10:41:21.288] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.288] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.288] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.288] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:41:21.288] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:41:21.288] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 6, value 438
[2015-01-13 10:41:21.288] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:6 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.288] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2096 ns
[2015-01-13 10:41:21.288] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.316] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:41:21.316] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 6, CPRI port 0
[2015-01-13 10:41:21.316] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:20, clientId:102
[2015-01-13 10:41:21.340] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 787
[2015-01-13 10:41:21.340] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:19, clientId:102
[2015-01-13 10:41:21.344] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 788
[2015-01-13 10:41:21.344] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC

TIVATE for carrierId:20, clientId:102


[2015-01-13 10:41:21.732] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=1
[2015-01-13 10:41:21.736] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:21.736] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(16), fb=(1), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.736] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:21.736] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.744] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=784, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.744] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:21.744] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.744] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.748] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:21.748] trDcProc delayCommHandler.cc:312 INFO:carrier:0x310 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.748] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:21.748] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:21.748] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.748] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
4 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:21.748] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.752] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:21.752] trDcProc delayCommHandler.cc:312 INFO:carrier:0x310 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390

[2015-01-13 10:41:21.752] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78


4 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.752] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:1):calc_tArpToTrp:-140112[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.752] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14011,filterBranch:1
[2015-01-13 10:41:21.756] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.756] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.756] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:41:21.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:41:21.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 1, value 438
[2015-01-13 10:41:21.756] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:1 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.756] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2078 ns
[2015-01-13 10:41:21.756] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.784] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:41:21.784] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 1, CPRI port 0
[2015-01-13 10:41:21.784] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:16, clientId:102
[2015-01-13 10:41:21.800] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=3
[2015-01-13 10:41:21.804] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:21.804] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(17), fb=(5), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.804] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true

[2015-01-13 10:41:21.804] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte


r 1
[2015-01-13 10:41:21.808] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=785, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.812] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:21.812] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.812] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.816] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:21.816] trDcProc delayCommHandler.cc:312 INFO:carrier:0x311 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.816] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:21.816] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:21.816] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.816] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
5 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:21.816] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.816] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:21.816] trDcProc delayCommHandler.cc:312 INFO:carrier:0x311 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.816] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
5 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.820] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:5):calc_tArpToTrp:-139932[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.820] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13993,filterBranch:5

[2015-01-13 10:41:21.824] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0


), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.824] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.824] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:41:21.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:41:21.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 5, value 438
[2015-01-13 10:41:21.824] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:5 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.824] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2096 ns
[2015-01-13 10:41:21.824] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.852] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:41:21.852] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 5, CPRI port 0
[2015-01-13 10:41:21.852] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:17, clientId:102
[2015-01-13 10:41:21.876] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 784
[2015-01-13 10:41:21.876] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:16, clientId:102
[2015-01-13 10:41:21.880] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 785
[2015-01-13 10:41:21.880] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:17, clientId:102
[2015-01-13 10:41:22.324] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=0
[2015-01-13 10:41:22.328] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:22.332] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(22), fb=(0), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.332] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true

[2015-01-13 10:41:22.332] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte


r 1
[2015-01-13 10:41:22.336] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=790, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.336] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:22.336] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:22.340] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.340] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:22.340] trDcProc delayCommHandler.cc:312 INFO:carrier:0x316 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:22.340] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:22.340] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:22.340] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:22.340] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
0 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:22.340] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.344] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:22.344] trDcProc delayCommHandler.cc:312 INFO:carrier:0x316 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:22.344] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
0 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:22.344] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:0):calc_tArpToTrp:-140112[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.348] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14011,filterBranch:0
[2015-01-13 10:41:22.348] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0

), tAdvDiff = (-4), sampleRateInNs = (1041.67)


[2015-01-13 10:41:22.348] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.348] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.348] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:41:22.348] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:41:22.348] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 0, value 438
[2015-01-13 10:41:22.348] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:0 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.348] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2078 ns
[2015-01-13 10:41:22.348] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.376] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:41:22.376] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 0, CPRI port 0
[2015-01-13 10:41:22.376] trDcProc timeOutSrv.cc:49 INFO:TimeOutServer::subscrib
e RxTracerWarp1x is already subscribed
[2015-01-13 10:41:22.376] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:22, clientId:102
[2015-01-13 10:41:22.400] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=2
[2015-01-13 10:41:22.404] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:22.408] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(23), fb=(4), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.408] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:22.408] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:22.412] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=791, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.412] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=60
00, signalBW=200, carrierFreqMin=907500, carrierFreqMax=913500
[2015-01-13 10:41:22.412] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven

t: setting center frequency to 942500 and vector width to 35000


[2015-01-13 10:41:22.416] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.416] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:22.416] trDcProc delayCommHandler.cc:312 INFO:carrier:0x317 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:22.416] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:22.416] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:22.416] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:22.416] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
1 tRuReportedDelayUl:121712[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3678
[2015-01-13 10:41:22.420] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.420] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:41:22.420] trDcProc delayCommHandler.cc:312 INFO:carrier:0x317 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:22.420] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
1 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:22.420] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:4):calc_tArpToTrp:-139932[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:770 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.424] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13993,filterBranch:4
[2015-01-13 10:41:22.424] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:22.424] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.428] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.428] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4

[2015-01-13 10:41:22.428] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna


bled fb 4, data 0
[2015-01-13 10:41:22.428] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 4, value 438
[2015-01-13 10:41:22.428] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:4 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.428] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2096 ns
[2015-01-13 10:41:22.428] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.456] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:41:22.456] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 4, CPRI port 0
[2015-01-13 10:41:22.456] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:23, clientId:102
[2015-01-13 10:41:22.480] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 790
[2015-01-13 10:41:22.480] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:22, clientId:102
[2015-01-13 10:41:22.484] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 791
[2015-01-13 10:41:22.484] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:23, clientId:102
[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
ff
[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x94000002, C1 0x94000001, C2 0x91000002, C3 0x91000001, C4 0x98000002, C5
0x98000001, C6 0x92000002, C7 0x92000001
[2015-01-13 10:41:22.804] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:41:24.316] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780

[2015-01-13 10:41:24.320] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT


to time: 250[ms], from 0x10097
[2015-01-13 10:41:24.320] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:41:24.332] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:24.332] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:24.348] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:41:24.420] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:41:24.420] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:41:24.420] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:41:24.444] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:41:24.444] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:41:24.444] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:41:24.444] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:41:24.444] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 1, paIdInternal: 0
[2015-01-13 10:41:24.648] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4780 (closest actual 4780)
[2015-01-13 10:41:24.648] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.648] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 0
[2015-01-13 10:41:24.652] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:41:24.652] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.652] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 780 event :8
[2015-01-13 10:41:24.656] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95340

0 (kHz), compensatedFreq = 953440 (kHz), rasterkHz = 80 (kHz)


[2015-01-13 10:41:24.660] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=780
[2015-01-13 10:41:24.664] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 953400, txLo: 953440, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:24.664] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:41:24.664] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 953400
[2015-01-13 10:41:24.664] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 953440, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:24.664] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 953440 (result: true)
[2015-01-13 10:41:24.692] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 780, event: 8
[2015-01-13 10:41:24.692] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :8
[2015-01-13 10:41:24.692] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:24.692] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:24.696] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:41:24.696] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :1024
[2015-01-13 10:41:24.700] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.700] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.700] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.700] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298954 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInternalBfnDe

lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.700] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :128
[2015-01-13 10:41:24.704] trDcProc dlDelayEventSubscriber.cc:783 INFO:isBfnAdvan
cerSetAtFirstCarrier: ON, rfPort 1
[2015-01-13 10:41:24.704] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.708] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.708] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298954 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInternalBfnDe
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.708] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298954 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1

[2015-01-13 10:41:24.708] trDcProc platformXDlDelayAdjust.cc:104 INFO:BFN_ADVANC


E bfnAdvanceAdjustedDelay[0] = 30436.197917
[2015-01-13 10:41:24.708] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:41:24.720] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:41:24.728] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.736] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.736] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 1
[2015-01-13 10:41:24.736] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:41:24.736] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.736] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 786 event :8
[2015-01-13 10:41:24.740] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:24.744] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95550
0 (kHz), compensatedFreq = 955520 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:41:24.748] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=786
[2015-01-13 10:41:24.748] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:24.788] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:24.788] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:41:24.788] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:41:24.788] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:41:24.788] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400

[2015-01-13 10:41:24.792] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq


= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:24.792] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 10:41:24.832] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 786, event: 8
[2015-01-13 10:41:24.832] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :8
[2015-01-13 10:41:24.832] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:24.876] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:24.876] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:24.876] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:24.880] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:41:24.880] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :1024
[2015-01-13 10:41:24.884] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.884] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.884] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.884] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298995 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.884] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 312, event :128
[2015-01-13 10:41:24.888] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:41:24.888] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36

71 [0.1ns]
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.892] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298995 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.892] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30440[ns] = salCarrierReportedDelay:298995 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:24.892] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 255 ns
[2015-01-13 10:41:24.904] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:41:24.912] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.920] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.920] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 2
[2015-01-13 10:41:24.920] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:41:24.920] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.920] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :8

[2015-01-13 10:41:24.924] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr


eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:24.924] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:41:24.924] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:41:24.924] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:41:24.924] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:41:24.928] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:24.928] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 10:41:24.980] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 8
[2015-01-13 10:41:24.980] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :8
[2015-01-13 10:41:24.980] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:25.028] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:25.028] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:25.028] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:25.032] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:41:25.032] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :1024
[2015-01-13 10:41:25.036] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.036] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)

[2015-01-13 10:41:25.036] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2


81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.036] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.040] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :128
[2015-01-13 10:41:25.040] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:41:25.040] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.040] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.044] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.044] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:2)tTrpToArp:30440[ns] = salCarrierReportedDelay:298999 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:25.044] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 255 ns
[2015-01-13 10:41:25.056] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE

ACTIVATE for carrierId:21, clientId:102


[2015-01-13 10:41:25.068] trDcProc powerClassCtrl.cc:487 INFO:totGsmCarrierPwrDb
m :4892 is higher than selected higherPowerClass:4780, maxPowerClass:4900 will b
e set
[2015-01-13 10:41:25.068] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4900
[2015-01-13 10:41:25.072] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:25.072] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:41:25.084] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.084] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.100] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.104] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.108] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298958 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.108] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30436[ns] = salCarrierReportedDelay:298958 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0

[2015-01-13 10:41:25.108] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se


tTotalDelay set vldb to 259 ns
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.120] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.124] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30440[ns] = salCarrierReportedDelay:298999 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:25.124] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 255 ns
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3675 [0.1ns]

[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(37), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.136] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.140] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30440[ns] = salCarrierReportedDelay:298999 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:25.140] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 255 ns
[2015-01-13 10:41:25.220] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:41:25.220] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:41:25.220] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:41:25.240] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:41:25.244] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:41:25.244] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:41:25.244] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:41:25.244] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:41:25.452] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 953400, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.452] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:41:25.452] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier

configuration, freqSetup: 953400


[2015-01-13 10:41:25.452] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:25.452] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955520 (result: true)
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:25.456] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:41:25.456] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:25.456] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)

[2015-01-13 10:41:25.460] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o


n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:41:25.460] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:25.460] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 10:41:25.460] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 10:41:25.460] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:25.460] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 783 event :8
[2015-01-13 10:41:25.464] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 7, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF; dev: 6, txFreq: 0, state: O
FF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq:
0, state: OFF;
[2015-01-13 10:41:25.464] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 10:41:25.464] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 10:41:25.464] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 10:41:25.464] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:25.464] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955520 (result: true)
[2015-01-13 10:41:25.536] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 783, event: 8
[2015-01-13 10:41:25.536] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :8
[2015-01-13 10:41:25.536] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:25.588] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:41:25.588] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:25.588] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte

r 1
[2015-01-13 10:41:25.592] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:41:25.596] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :1024
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.600] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :128
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a1e, rfPort 1
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:41:25.604] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte


dDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.604] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30440[ns] = salCarrierReportedDelay:298999 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:25.604] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 255 ns
[2015-01-13 10:41:25.620] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:15, clientId:102
[2015-01-13 10:41:25.644] - fault_manager.cc:1910 INFO:Set event PA_ON_EVENT to
time: 20000[ms], from 0x10097
[2015-01-13 10:41:25.644] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOffEvent
[2015-01-13 10:41:25.644] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:41:25.648] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:41:25.648] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.648] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80040001, dlFbA2Cfg:0x80080001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.648] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 10:41:25.648] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.648] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 953400, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF; dev:
8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.648] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.648] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:41:25.656] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:41:25.736] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq

= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x


718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:25.740] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:41:25.740] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.740] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:41:25.740] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPm
b:-34.58[-61.50 -8.00] dB)
[2015-01-13 10:41:25.740] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 780 ENABLE ev
ent
[2015-01-13 10:41:25.740] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 780 ENABLE ev
ent
[2015-01-13 10:41:25.740] trDcProc commonCsc.cc:130 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:41:25.740] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 780
[2015-01-13 10:41:25.744] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 750
[2015-01-13 10:41:25.744] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:12, clientId:102
[2015-01-13 10:41:25.748] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.748] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80040001, dlFbA2Cfg:0x80080001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.748] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 786
[2015-01-13 10:41:25.748] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.836] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500
, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.836] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled

[2015-01-13 10:41:25.836] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId


0 already unblocked.
[2015-01-13 10:41:25.836] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 10:41:25.836] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 10:41:25.836] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:41:25.836] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 786
[2015-01-13 10:41:25.840] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:18, clientId:102
[2015-01-13 10:41:25.852] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-34.65[-61.50 -8.00] dB)
[2015-01-13 10:41:25.852] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.852] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80040001, dlFbA2Cfg:0x80080001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.852] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 789
[2015-01-13 10:41:25.852] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.852] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.856] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.856] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:41:25.856] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:41:25.856] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 10:41:25.856] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt

rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 789 ENABLE ev


ent
[2015-01-13 10:41:25.856] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:41:25.856] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 789
[2015-01-13 10:41:25.860] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:21, clientId:102
[2015-01-13 10:41:25.868] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x8, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:41:25.872] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.872] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80040001, dlFbA2Cfg:0x80080001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.872] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 783
[2015-01-13 10:41:25.872] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.872] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OF
F; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.872] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.876] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:41:25.876] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:41:25.876] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 10:41:25.876] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 10:41:25.876] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 783 ENABLE ev
ent
[2015-01-13 10:41:25.876] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.

[2015-01-13 10:41:25.876] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB


LED successful for carrier 783
[2015-01-13 10:41:25.880] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 10:41:25.880] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:15, clientId:102
[2015-01-13 10:41:26.452] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.151741, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:41:26.660] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.43[-61.50 -8.00] dB)
[2015-01-13 10:41:26.660] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:41:26.660] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:41:26.660] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:41:26.688] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 57 deg
[2015-01-13 10:41:26.688] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 57 deg
[2015-01-13 10:41:26.688] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25083
[2015-01-13 10:41:26.688] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 28933 us.
[2015-01-13 10:41:26.688] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:41:26.716] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24266 us. IntegerDelay: 0x1d3 FracDela
y: 0x2b
[2015-01-13 10:41:26.716] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
f8
[2015-01-13 10:41:26.716] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2754, currentDpdDelay[1]=1721 (0.1 ns)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga

Delay:3673 [0.1ns]
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.740] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.740] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.752] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.756] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.756] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga

Delay:3673 [0.1ns]
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.772] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.772] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 10:41:26.872] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 10:41:27.876] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x20630a1 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
8c8fd C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0c

77d3 pa1Adj 0x4779


[2015-01-13 10:41:28.880] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effac7 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
ba4ba C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb10
078e pa1Adj 0x4779
[2015-01-13 10:41:29.884] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efe3ee C1 0x0 C2 0x0 C3 0xe4f4cf, pmPa0C0
0x8da6b49 C1 0x0 C2 0x0 C3 0x246cd5c, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xdcc78e2 pa1Adj 0x4779
[2015-01-13 10:41:30.888] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f012a6 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
ce0a4 C1 0x0 C2 0x0 C3 0x21c471d, pa0C0Adj 0x1f96
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1
0xd9fb53f pa1Adj 0x4779
[2015-01-13 10:41:35.692] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eff061 C1 0x0 C2 0x0 C3 0x5fb77, pmPa0C0
0x8da5e48 C1 0x0 C2 0x0 C3 0x3b00455, pa0C0Adj 0x1
f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, p
mPa1 0xf7a6f58 pa1Adj 0x4779
[2015-01-13 10:41:36.696] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f85207 C1 0x0 C2 0x0 C3 0x1f7afef, pmPa0C
0 0x8daf313 C1 0x10d076c C2 0x0 C3 0x4997fcd, pa0C
0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0
x8008, pmPa1 0x120e8d66 pa1Adj 0x4779
[2015-01-13 10:41:37.700] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0083b C1 0x1eecc90 C2 0x0 C3 0x1f100ba,
pmPa0C0 0x8d88440 C1 0x45f50e2 C2 0x0 C3 0x4109c17
, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x800
8 C3 0x8008, pmPa1 0x157017ee pa1Adj 0x4779
[2015-01-13 10:41:38.704] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef93ff C1 0x298d2e C2 0x0 C3 0x298345, pm
Pa0C0 0x8de46e2 C1 0x5c98671 C2 0x0 C3 0x30151d4,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x15cff041 pa1Adj 0x4779
[2015-01-13 10:41:39.712] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f01681 C1 0x0 C2 0x0 C3 0x7ddfd6, pmPa0C0
0x8d9f6f6 C1 0x34e21c0 C2 0x0 C3 0x1ce0804, pa0C0
Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x
8008, pmPa1 0x114d7c34 pa1Adj 0x4779
[2015-01-13 10:41:40.716] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efa522 C1 0x1549a18 C2 0x9aebcf C3 0x9b09
5b, pmPa0C0 0x8de4988 C1 0x23fbd03 C2 0x10ddfee C3
0x44d1e3e, pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x800
8 C2 0x8008 C3 0x8008, pmPa1 0x144d290c pa1Adj 0x4779
[2015-01-13 10:41:41.728] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efc54a C1 0x7c4b16 C2 0x0 C3 0x0, pmPa0C0
0x8de6359 C1 0xf31c00 C2 0x1694a5c C3 0x1f0e3ed,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008

C3 0x8008, pmPa1 0x1054fb89 pa1Adj 0x4779


[2015-01-13 10:41:42.732] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef9187 C1 0x5edbde C2 0x0 C3 0x0, pmPa0C0
0x8da49e2 C1 0xab2f03 C2 0x10e3c3d C3 0x4bc91fa,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x12e84272 pa1Adj 0x4779
[2015-01-13 10:41:43.736] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2062e25 C1 0x0 C2 0x0 C3 0x146dbdc, pmPa0C
0 0x8d675ac C1 0x8cc69a C2 0x6b624e C3 0x23f3014,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0xefd81a1 pa1Adj 0x4779
[2015-01-13 10:41:44.744] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1edebf0 C1 0x3c8f1d C2 0x0 C3 0x0, pmPa0C0
0x8d1a814 C1 0x437cef C2 0x43d58e C3 0x1b82f19, p
a0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C
3 0x8008, pmPa1 0xdbe38fb pa1Adj 0x4779
[2015-01-13 10:41:45.552] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ee18bc C1 0x0 C2 0x2a88b4 C3 0x1666cda, p
mPa0C0 0x8e3de25 C1 0x0 C2 0x14737a6 C3 0x2d05f16,
pa0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008
C3 0x8008, pmPa1 0x102678bb pa1Adj 0x4779
[2015-01-13 10:41:46.564] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ea4020 C1 0x0 C2 0x0 C3 0x104212, pmPa0C0
0x8dd8042 C1 0x6b9f02 C2 0x1f3f99 C3 0x406ef9f, p
a0C0Adj 0x1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C
3 0x8008, pmPa1 0x10ad8f74 pa1Adj 0x4779
[2015-01-13 10:41:47.568] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef2a54 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
57b76 C1 0x0 C2 0x0 C3 0x2b73bab, pa0C0Adj 0x1f96
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1
0xe48692c pa1Adj 0x4779
[2015-01-13 10:41:48.572] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ce2d7e C1 0x0 C2 0x0 C3 0x1c7cbe, pmPa0C0
0x8d96c54 C1 0x0 C2 0x0 C3 0x3437ced, pa0C0Adj 0x
1f96 C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008,
pmPa1 0xf00ccb5 pa1Adj 0x4779
[2015-01-13 11:53:00.328] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 1
[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=170
[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:364 INFO:Setting r
eserved voltage
[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port A au
x power on

[2015-01-13 11:53:00.328] antpServerProc_ currentSv.cc:251 INFO:Current Limits(l


ow,high): [50, 1600] on antenna port A
[2015-01-13 11:53:00.328] antpServerProc_ ANUSupervisionService.cc:900 INFO:AnpT
ot ON and Turned it On
[2015-01-13 11:53:00.328] antpServerProc_ ANUSupervisionService.cc:904 INFO:AnpT
ot ON
[2015-01-13 11:53:00.328] antpServerProc_ lrciAntsysImpl.cc:327 INFO:LRCI: Port
A set power on
[2015-01-13 11:53:00.328] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxSupplyPow
[2015-01-13 11:53:00.328] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port A to
ON
[2015-01-13 11:53:00.332] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:00.332] antpServerProc_ ruAntpDevice.cc:1052 INFO:Current Meas
urement started
[2015-01-13 11:53:00.332] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 1
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=170
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port B au
x power on
[2015-01-13 11:53:00.332] antpServerProc_ currentSv.cc:251 INFO:Current Limits(l
ow,high): [50, 1600] on antenna port B
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:904 INFO:AnpT
ot ON
[2015-01-13 11:53:00.332] antpServerProc_ lrciAntsysImpl.cc:327 INFO:LRCI: Port
B set power on
[2015-01-13 11:53:00.332] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxSupplyPow
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port B to
ON
[2015-01-13 11:53:00.332] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0

[2015-01-13 11:53:00.332] antpServerProc_ ruAntpDevice.cc:1052 INFO:Current Meas


urement started
[2015-01-13 11:53:03.248] currentSvProc currentSv.cc:175 INFO:Current (0) too lo
w detected on port A
[2015-01-13 11:53:03.248] currentSvProc currentSv.cc:175 INFO:Current (0) too lo
w detected on port B
[2015-01-13 11:53:06.448] antpServerProc_ ruAntpDevice.cc:1078 INFO:Current Meas
urement stopped
[2015-01-13 11:53:06.448] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 0
[2015-01-13 11:53:06.448] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:06.448] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port A au
x power off
[2015-01-13 11:53:06.448] antpServerProc_ lrciAntsysImpl.cc:331 INFO:LRCI: Port
A set power off
[2015-01-13 11:53:06.448] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoResistanceSvPow
[2015-01-13 11:53:06.448] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoSupplyPow
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port A to
OFF
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:953 INFO:AnpT
ot OFF
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=0
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:06.452] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:06.452] antpServerProc_ ruAntpDevice.cc:1078 INFO:Current Meas
urement stopped
[2015-01-13 11:53:06.452] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 0
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port B au
x power off

[2015-01-13 11:53:06.452] antpServerProc_ lrciAntsysImpl.cc:331 INFO:LRCI: Port


B set power off
[2015-01-13 11:53:06.452] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoResistanceSvPow
[2015-01-13 11:53:06.452] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoSupplyPow
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port B to
OFF
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:946 INFO:AnpT
ot OFF and Turned it OFF
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:953 INFO:AnpT
ot OFF
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=0
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:06.452] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:06.856] trDcProc dynamicRfSignalCapabilityImpl.cc:121 INFO:noT
xPorts= 1, m_rfSignalId.ordinal()= 1
[2015-01-13 11:53:06.856] trDcProc trDcCapabilities.cc:352 INFO:ABN: No amountFr
eePower for port 1 , capabilityNoTx= 1

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