Cse Digital - Manual

LAB MANUAL
CS 2207
DIGITAL LABORATORY
(Common to CSE & IT)
LIST OF EXPERIMENTS
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1. Verification of Boolean theorems using digital logic gates

2. Design and implementation of combinational circuits using basic gates for
arbitrary functions, code converters, etc.
1. Design and implementation of 4-bit binary adder / subtractor using basic
gates and MSI devices
2. Design and implementation of parity generator / checker using basic
gates and MSI devices
3. Design and implementation of magnitude comparator
4. Design and implementation of application using multiplexers/
Demultiplexers
5. Design and implementation of Shift registers
6. Design and implementation of Synchronous and Asynchronous counters
7. Simulation of combinational circuits using Hardware Description
Language (VHDL/ Verilog HDL software required)
8. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL software
required)
2007-08/Even/IV/ECE/EC1258/DE/LM
Page No.
LIST OF EXPERIMENTS
1. Verification of Boolean Theorems using logic gates.
2. Design and implementation of combinational circuits using basic
gates for the given arbitrary function.
3. Design and implementation of code converters using logic gates
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(ii) Binary to gray and vice-versa
(i) BCD to excess-3 code and voice versa
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4. (a) Design and implementation of Adders and Subtractors using

logic gates.
Design
and
implementation
Magnitude
Comparator
using
ve
logic gates
Design and implementation of parity checker /generator using
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6.
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5.
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(b) Design and implementation of 4 bit binary Adder/ subtractor
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basic gates and MSI devices.
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logic gates
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7. Design and implementation of Multiplexer and De-multiplexer using
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8. Design and implementation of application using Multiplexer.
9. Construction and verification of 4 bit ripple counter and Mod-10 /
Mod-12 Ripple counters

10. Design and implementation of 3-bit synchronous up counter.
11. Implementation of SISO, SIPO, PISO and PIPO shift registers using
Flip- flops.
12. Simulation of combinational circuits using HDL
13. Simulation of sequential circuits using HDL
Page No.
NAME OF THE EXPERIMENT
PAGE
NO
MARKS
SIGNATURE
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DATE
EXP.
NO
INDEX
Page No.
STUDY OF LOGIC GATES
EXPT NO. :
DATE
:
AIM:
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To study about logic gates and verify their truth tables.
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SPECIFICATION QTY
IC 7408
1
IC 7432
1
IC 7404
1
IC 7400
1
IC 7402
1
IC 7486
1
IC 7410
1
1
14
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SL No.
COMPONENT
1. AND GATE
2. OR GATE
3. NOT GATE
4. NAND GATE 2 I/P
5. NOR GATE
6. X-OR GATE
7. NAND GATE 3 I/P
8. IC TRAINER KIT
9. PATCH CORD
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APPARATUS REQUIRED:
THEORY:
Page No.
Circuit that takes the logical decision and the process are called logic
gates. Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are
known as universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as
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is low level when any one of the inputs is low.
AND function. The output is high when both the inputs are high. The output
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OR GATE:
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The OR gate performs a logical addition commonly known as OR
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function. The output is high when any one of the inputs is high. The output
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is low level when both the inputs are low.
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NOT GATE:
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The NOT gate is called an inverter. The output is high when the
input is low. The output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high
when both inputs are low and any one of the input is low .The output is low
level when both inputs are high.
NOR GATE:
Page No.
The NOR gate is a contraction of OR-NOT. The output is high when

both inputs are low. The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.
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PROCEDURE:
(i)
Connections are given as per circuit diagram.
Logical inputs are given as per circuit diagram.
(iii)
Observe the output and verify the truth table.
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(ii)
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AND GATE:
PIN DIAGRAM:
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SYMBOL:
OR GATE:
Page No.
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NOT GATE:
PIN DIAGRAM:
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SYMBOL:
X-OR GATE :
Page No.
PIN DIAGRAM :
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SYMBOL :
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2-INPUT NAND GATE:
PIN DIAGRAM:
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SYMBOL:
Page No.
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3-INPUT NAND GATE :
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NOR GATE:
Page No.
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RESULT:
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DATE
DESIGN OF ADDER AND SUBTRACTOR
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EXPT NO. :
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AIM:
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To design and construct half adder, full adder, half subtractor and full
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subtractor circuits and verify the truth table using logic gates.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
3.
4.
COMPONENT
AND GATE
X-OR GATE
NOT GATE
OR GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION QTY.
IC 7408
1
IC 7486
1
IC 7404
1
IC 7432
1
1
23
Page No. 10
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two
outputs one from the sum S and other from the carry c into the higher
adder position. Above circuit is called as a carry signal from the addition of
the less significant bits sum from the X-OR Gate the carry out from the
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AND gate.
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FULL ADDER:
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A full adder is a combinational circuit that forms the arithmetic sum
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of input; it consists of three inputs and two outputs. A full adder is useful to
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add three bits at a time but a half adder cannot do so. In full adder sum
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output will be taken from X-OR Gate, carry output will be taken from OR
Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The
half subtractor has two input and two outputs. The outputs are difference and
borrow. The difference can be applied using X-OR Gate, borrow output can
be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
Page No. 11
The full subtractor is a combination of X-OR, AND, OR, NOT Gates.

In a full subtractor the logic circuit should have three inputs and two outputs.
The two half subtractor put together gives a full subtractor .The first half
subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-
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OR.
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LOGIC DIAGRAM:
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HALF ADDER
TRUTH TABLE:
A
CARRY
SUM
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
Page No. 12
K-Map for CARRY:
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K-Map for SUM:
CARRY = AB
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SUM = AB + AB
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LOGIC DIAGRAM:
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FULL ADDER
FULL ADDER USING TWO HALF ADDER
TRUTH TABLE:
A
CARRY
SUM
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
Page No. 13
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
0
1
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K-Map for SUM:
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SUM = ABC + ABC + ABC + ABC
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K-Map for CARRY:
CARRY = AB + BC + AC
LOGIC DIAGRAM:
HALF SUBTRACTOR
Page No. 14
TRUTH TABLE:
0
1
0
0
0
1
1
0
0
1
0
1
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0
0
1
1
BORROW DIFFERENCE
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K-Map for DIFFERENCE:
DIFFERENCE = AB + AB
K-Map for BORROW:
BORROW = AB
Page No. 15
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LOGIC DIAGRAM:
FULL SUBTRACTOR
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FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
A
0
0
0
0
0
1
0
1
0
BORROW DIFFERENCE
0
1
1
0
1
1
Page No. 16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
0
0
1
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K-Map for Difference:
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K-Map for Borrow:
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Difference = ABC + ABC + ABC + ABC
Borrow = AB + BC + AC
PROCEEDURE:
(i)
(ii)
Page No. 17
(iii)
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RESULT:
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DATE
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EXPT NO. :
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DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
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AIM:
To design and implement 4-bit

(i)
Binary to gray code converter
(ii)
Gray to binary code converter
(iii)
BCD to excess-3 code converter
(iv)
Excess-3 to BCD code converter
APPARATUS REQUIRED:
Sl.No.
COMPONENT
1.
X-OR GATE
2.
AND GATE
3.
OR GATE
SPECIFICATION QTY.
IC 7486
1
IC 7408
1
IC 7432
1
Page No. 18
4.
5.
6.
NOT GATE
IC TRAINER KIT
PATCH CORDS
IC 7404
-
1
1
35
THEORY:
The availability of large variety of codes for the same discrete
elements of information results in the use of different codes by different
systems. A conversion circuit must be inserted between the two systems if
each uses different codes for same information. Thus, code converter is a
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circuit that makes the two systems compatible even though each uses
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different binary code.
The bit combination assigned to binary code to gray code. Since each
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code uses four bits to represent a decimal digit. There are four inputs and
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four outputs. Gray code is a non-weighted code.
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The input variable are designated as B3, B2, B1, B0 and the output
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variables are designated as C3, C2, C1, Co. from the truth table,
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combinational circuit is designed. The Boolean functions are obtained from
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K-Map for each output variable.
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A code converter is a circuit that makes the two systems compatible
even though each uses a different binary code. To convert from binary code
to Excess-3 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
Page No. 19
LOGIC DIAGRAM:
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BINARY TO GRAY CODE CONVERTOR
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K-Map for G3:
G3 = B3
K-Map for G2:
Page No. 20
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K-Map for G0:
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K-Map for G1:
Page No. 21
TRUTH TABLE:
|
Binary input
Gray code output
B2
B1
B0
G3
G2
G1
G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
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B3
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LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
Page No. 22
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K-Map for B3:
B3 = G3
K-Map for B2:
Page No. 23
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K-Map for B1:
K-Map for B0:

Page No. 24
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G1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
G0
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G2
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G3
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Binary Code
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Gray Code
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TRUTH TABLE:
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Page No. 25
LOGIC DIAGRAM:
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BCD TO EXCESS-3 CONVERTOR
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K-Map for E3:
E3 = B3 + B2 (B0 + B1)
Page No. 26
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K-Map for E2:
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K-Map for E1:
Page No. 27
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K-Map for E0:
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0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
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B1
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0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
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TRUTH TABLE:
|
BCD input
B3
B2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Excess 3 output
G3
G2
G1
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
|
G0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
Page No. 28
LOGIC DIAGRAM:
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EXCESS-3 TO BCD CONVERTOR
Page No. 29
A = X1 X2 + X3 X4 X1
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K-Map for A:
K-Map for B:
Page No. 30
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K-Map for C:
K-Map for D:
Page No. 31
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B2
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
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B1
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B3
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Excess 3 Input
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TRUTH TABLE:
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1
0
0
1
1
0
0
1
1
0
BCD Output
B0
G3
G2
G1
G0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
PROCEDURE:
Page No. 32
Connections were given as per circuit diagram.
(ii)
Logical inputs were given as per truth table
(iii)
Observe the logical output and verify with the truth tables.
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(i)
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RESULT:
EXPT NO. :
DATE
:
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
Page No. 33
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.
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APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION QTY.
1.
IC
IC 7483
1
2.
EX-OR GATE
IC 7486
1
3.
NOT GATE
IC 7404
1
3.
IC TRAINER KIT
1
4.
PATCH CORDS
40
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THEORY:
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4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of
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two binary numbers. It can be constructed with full adders connected in
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cascade, with the output carry from each full adder connected to the input
carry of next full adder in chain. The augends bits of A and the addend bits
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of B are designated by subscript numbers from right to left, with subscript
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0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripples
through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters,
placed between each data input B and the corresponding input of full
adder. The input carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
Page No. 34
The addition and subtraction operation can be combined into one

circuit with one common binary adder. The mode input M controls the
operation. When M=0, the circuit is adder circuit. When M=1, it becomes
subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD,
together with an input carry from a previous stage. Since each input digit
does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum
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being an input carry. The output of two decimal digits must be represented
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in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD.
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4 bit adder to produce the binary sum.
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The 2 decimal digits, together with the input carry, are first added in the top
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PIN DIAGRAM FOR IC 7483:
Page No. 35
LOGIC DIAGRAM:
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4-BIT BINARY ADDER
Page No. 36
LOGIC DIAGRAM:
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4-BIT BINARY SUBTRACTOR
Page No. 37
LOGIC DIAGRAM:
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4-BIT BINARY ADDER/SUBTRACTOR
Page No. 38
TRUTH TABLE:
Input Data A
Input Data B
Addition
Subtraction
A4 A3 A2 A1 B4 B3 B2 B1
S4 S3 S2 S1
D4 D3 D2 D1
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Page No. 39
LOGIC DIAGRAM:
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BCD ADDER
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K MAP
Y = S4 (S3 + S2)
Page No. 40
CARRY
C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
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S1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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BCD SUM
S3
S2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
S4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TRUTH TABLE:
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PROCEDURE:
Connections were given as per circuit diagram.
(ii)
Logical inputs were given as per truth table
(iii)
Observe the logical output and verify with the truth tables.
RESULT:
.e
ee
ex
(i)
Page No. 41
EXPT NO. :
DATE
:
DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
AIM:
To design and implement
2 bit magnitude comparator using basic gates.
(ii)
8 bit magnitude comparator using IC 7485.
.c
o
(i)
og
-
1
30
.b
l
QTY.
2
1
1
1
2
si
cl
u
THEORY:
.e
ee
6.
7.
SPECIFICATION
IC 7408
IC 7486
IC 7432
IC 7404
IC 7485
ve
COMPONENT
AND GATE
X-OR GATE
OR GATE
NOT GATE
4-BIT MAGNITUDE
COMPARATOR
IC TRAINER KIT
PATCH CORDS
ex
Sl.No.
1.
2.
3.
4.
5.
sp
ot
APPARATUS REQUIRED:
The comparison of two numbers is an operator that determine one

number is greater than, less than (or) equal to the other number. A
magnitude comparator is a combinational circuit that compares two numbers
A and B and determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B,
A=B (or) A<B.
Page No. 42
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a
combinational circuit designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of
.c
o
pairs of significant digits starting from most significant position. A is 0 and
sp
ot
that of B is 0.
ve
.b
l
og
We have A<B, the sequential comparison can be expanded as
si
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
ex
cl
u
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
.e
two BCD digits.
ee
The same circuit can be used to compare the relative magnitude of
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
x3
x2
x1
x0
Page No. 43
LOGIC DIAGRAM:
.e
ee
ex
cl
u
si
ve
.b
l
og
sp
ot
.c
o
2 BIT MAGNITUDE COMPARATOR
Page No. 44
.e
ee
ex
cl
u
si
ve
.b
l
og
sp
ot
.c
o
K MAP
Page No. 45
m
.c
o
sp
ot
og
.b
l
ve
si
cl
u
ex
ee
.e
w
w
w
TRUTH TABLE
Page No. 46
og
A<B
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
.c
o
A=B
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
sp
ot
A>B
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
.e
ee
ex
cl
u
si
ve
.b
l
A1 A0 B1 B0
0
0 0 0
0
0 0 1
0
0 1 0
0
0 1 1
0
1 0 0
0
1 0 1
0
1 1 0
0
1 1 1
1
0 0 0
1
0 0 1
1
0 1 0
1
0 1 1
1
1 0 0
1
1 0 1
1
1 1 0
1
1 1 1
Page No. 47
m
.c
o
sp
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og
.b
l
ve
si
cl
u
ex
ee
.e
w
w
w
LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
Page No. 48
m
0000
0000
0001
0000
0000
0001
.b
l
0000
0001
0000
A=B
1
0
0
A<B
0
0
1
.e
ee
ex
cl
u
si
0000
0001
0000
A>B
0
1
0
og
ve
sp
ot
.c
o
TRUTH TABLE:
PROCEDURE:
(i)
(ii)

Page No. 49
.c
o
(iii)
.e
ee
ex
cl
u
si
ve
.b
l
og
sp
ot
RESULT:
EXPT NO. :
DATE
:
16 BIT ODD/EVEN PARITY CHECKER /GENERATOR
AIM:
To design and implement 16 bit odd/even parity checker generator
using IC 74180.
Page No. 50
APPARATUS REQUIRED:
COMPONENT
NOT GATE
SPECIFICATION QTY.
IC 7404
1
IC 74180
2
1
30
IC TRAINER KIT
PATCH CORDS
Sl.No.
1.
1.
2.
3.
sp
ot
.c
o
THEORY:
A parity bit is used for detecting errors during transmission of binary
og
information. A parity bit is an extra bit included with a binary message to
.b
l
make the number is either even or odd. The message including the parity bit
ve
is transmitted and then checked at the receiver ends for errors. An error is
cl
u
si
detected if the checked parity bit doesnt correspond to the one transmitted.
ex
The circuit that generates the parity bit in the transmitter is called a parity
ee
generator and the circuit that checks the parity in the receiver is called a
.e
parity checker.
In even parity, the added parity bit will make the total number is even
amount. In odd parity, the added parity bit will make the total number is odd
amount. The parity checker circuit checks for possible errors in the
transmission. If the information is passed in even parity, then the bits
required must have an even number of 1s. An error occur during
transmission, if the received bits have an odd number of 1s indicating that
one bit has changed in value during transmission.
Page No. 51
m
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o
sp
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og
.b
l
1
1
0
0
1
0
ee
.e
PO
0
0
1
1
1
0
OUTPUTS
E
O
1
0
0
1
0
1
0
1
1
0
0
1
ve
cl
u
si
PE
ex
FUNCTION TABLE:
INPUTS
Number of High Data
Inputs (I0 I7)
EVEN
ODD
EVEN
ODD
X
X
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER
Page No. 52
m
sp
ot
.c
o
TRUTH TABLE:
E
1
1
0
O
0
0
1
.e
ee
ex
cl
u
si
ve
.b
l
og
I7 I6 I5 I4 I3 I2 I1 I0 I7I6I5I4I3I211 I0 Active
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATOR
Page No. 53
m
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o
sp
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.b
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og
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 Active
1 1 0 0 0 0 0 0
1
1 1 0 0 0 0 0 0
0
0 1 0 0 0 0 0 0
0
E
1
0
1
O
0
1
0
.e
ee
ex
cl
u
si
ve
I7 I6 I5 I4 I3 I2 I1 I0
1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0
PROCEDURE:
(i)
(ii)

Page No. 54
sp
ot
.c
o
(iii)
.e
ee
ex
cl
u
si
ve
.b
l
og
RESULT:
EXPT NO. :
DATE
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER
AIM:
Page No. 55
To design and implement multiplexer and demultiplexer using logic

gates and study of IC 74150 and IC 74154.
APPARATUS REQUIRED:
SPECIFICATION QTY.
IC 7411
2
IC 7432
1
IC 7404
1
1
32
COMPONENT
3 I/P AND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
.c
o
Sl.No.
1.
2.
3.
2.
3.
og
sp
ot
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units
.b
l
over a smaller number of channels or lines. A digital multiplexer is a
ve
combinational circuit that selects binary information from one of many input
cl
u
si
lines and directs it to a single output line. The selection of a particular input
ex
line is controlled by a set of selection lines. Normally there are 2n input line
ee
and n selection lines whose bit combination determine which input is
.e
selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It

takes information from one line and distributes it to a given number of
output lines. For this reason, the demultiplexer is also known as a data
distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the
AND gates. The data select lines enable only one gate at a time and the data
on the data input line will pass through the selected gate to the associated
data output line.
Page No. 56
sp
ot
.c
o
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
ex
.e
ee
INPUTS Y
D0 D0 S1 S0
D1 D1 S1 S0
D2 D2 S1 S0
D3 D3 S1 S0
si
S0
0
1
0
1
cl
u
S1
0
0
1
1
ve
.b
l
og
FUNCTION TABLE:
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
CIRCUIT DIAGRAM FOR MULTIPLEXER:
Page No. 57
m
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.b
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ve
si
cl
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ee
ex
w
.e
TRUTH TABLE:
S1
0
0
1
1
S0
0
1
0
1
Y = OUTPUT
D0
D1
D2
D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
Page No. 58
m
.c
o
ve
INPUT
X D0 = X S1 S0
X D1 = X S1 S0
X D2 = X S1 S0
X D3 = X S1 S0
si
S0
0
1
0
1
ee
ex
cl
u
S1
0
0
1
1
.b
l
og
sp
ot
FUNCTION TABLE:
.e
Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0
LOGIC DIAGRAM FOR DEMULTIPLEXER:
Page No. 59
m
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.b
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si
cl
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ee
.e
w
w
w
TRUTH TABLE:
S1
INPUT
S0
I/P
D0
OUTPUT
D1
D2
D3
Page No. 60
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
.e
ee
ex
cl
u
si
ve
.b
l
og
sp
ot
.c
o
Page No. 61
m
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o
sp
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og
.b
l
cl
u
si
ve
PROCEDURE:
(i)
(iii)
ee
.e
w
RESULT:
ex
(ii)
Page No. 62
EXPT NO. :
DATE
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
AIM:
To design and implement encoder and decoder using logic gates and
study of IC 7445 and IC 74147.
sp
ot
.b
l
og
SPECIFICATION QTY.
IC 7410
2
IC 7432
3
IC 7404
1
1
27
ve
COMPONENT
3 I/P NAND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
ex
cl
u
si
Sl.No.
1.
2.
3.
2.
3.
.c
o
APPARATUS REQUIRED:
.e
ee
THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a
decoder. An encoder has 2n input lines and n output lines. In encoder the
output lines generates the binary code corresponding to the input value. In
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is assumed
that only one input has a value of one at any given time otherwise the circuit
is meaningless. It has an ambiguila that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
Page No. 63
A decoder is a multiple input multiple output logic circuit which

converts coded input into coded output where input and output codes are
different. The input code generally has fewer bits than the output code. Each
input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2n possible
.c
o
outputs. 2n output values are from 0 through out 2n 1.
sp
ot
.e
ee
ex
cl
u
si
ve
.b
l
og
BCD TO DECIMAL DECODER:
Page No. 64
m
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sp
ot
og
.b
l
ve
si
cl
u
ex
ee
.e
w
w
w
LOGIC DIAGRAM FOR ENCODER:
Page No. 65
m
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o
sp
ot
og
.b
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ve
si
cl
u
INPUT
Y4
Y5
0
0
0
0
0
0
1
0
0
1
0
0
0
0
ee
.e
Y3
0
0
1
0
0
0
0
Y2
0
1
0
0
0
0
0
Y1
1
0
0
0
0
0
0
ex
TRUTH TABLE:
Y6
0
0
0
0
0
1
0
Y7
0
0
0
0
0
0
1
A
0
0
0
1
1
1
1
OUTPUT
B
0
1
1
0
0
1
1
C
1
0
1
0
1
0
1
LOGIC DIAGRAM FOR DECODER:
Page No. 66
m
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o
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.b
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ve
si
cl
u
ex
ee
.e
TRUTH TABLE:
w
w
E
1
0
0
0
0
INPUT
A
0
0
0
1
1
B
0
0
1
0
1
D0
1
0
1
1
1
OUTPUT
D1
D2
1
1
1
1
0
1
1
0
1
1
D3
1
1
1
1
0
PROCEDURE:
(i)

Page No. 67
(iii)
ve
.b
l
og
sp
ot
.c
o
(ii)
.e
ee
ex
cl
u
si
RESULT:
EXPT NO. :
DATE
:
CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER
AIM:
Page No. 68
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple
counter.
APPARATUS REQUIRED:
SPECIFICATION QTY.
IC 7476
2
IC 7400
1
1
30
COMPONENT
JK FLIP FLOP
NAND GATE
IC TRAINER KIT
PATCH CORDS
sp
ot
.c
o
Sl.No.
1.
2.
3.
4.
og
THEORY:
.b
l
A counter is a register capable of counting number of clock pulse
ve
arriving at its clock input. Counter represents the number of clock pulses
cl
u
si
arrived. A specified sequence of states appears as counter output. This is the
ex
main difference between a register and a counter. There are two types of
ee
counter, synchronous and asynchronous. In synchronous common clock is
.e
given to all flip flop and in asynchronous first flip flop is clocked by external
pulse and then each successive flip flop is clocked by Q or Q output of
previous stage. A soon the clock of second stage is triggered by output of

first stage. Because of inherent propagation delay time all flip flops are not
activated at same time which results in asynchronous operation.
Page No. 69
m
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.b
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.e
ee
ex
cl
u
si
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
Page No. 70
m
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o
sp
ot
og
.b
l
ve
si
cl
u
ex
ee
.e
TRUTH TABLE:
CLK
0
1
2
3
4
5
6
7
8
9
10
QA
0
1
0
1
0
1
0
1
0
1
0
QB
0
0
1
1
0
0
1
1
0
0
1
QC
0
0
0
0
1
1
1
1
0
0
0
QD
0
0
0
0
0
0
0
0
1
1
1
Page No. 71
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
sp
ot
.c
o
11
12
13
14
15
.e
ee
ex
cl
u
si
ve
.b
l
og
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
TRUTH TABLE:
CLK
0
1
2
3
QA
0
1
0
1
QB
0
0
1
1
QC
0
0
0
0
QD
0
0
0
0
Page No. 72
4
5
6
7
8
9
10
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
ee
QA
0
1
0
1
0
1
0
1
0
1
0
1
0
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
.e
TRUTH TABLE:
ex
cl
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si
ve
.b
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sp
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.c
o
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
QB
0
0
1
1
0
0
1
1
0
0
1
1
0
QC
0
0
0
0
1
1
1
1
0
0
0
0
0
QD
0
0
0
0
0
0
0
0
1
1
1
1
0
Page No. 73
PROCEDURE:
(ii)
(iii)
cl
u
si
ve
.b
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sp
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.c
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(i)
.e
ee
ex
RESULT:
Page No. 74
EXPT NO. :
DATE
:
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS
UP/DOWN COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
ve
.b
l
og
sp
ot
SPECIFICATION QTY.
IC 7476
2
IC 7411
1
IC 7432
1
IC 7486
1
IC 7404
1
1
35
si
COMPONENT
JK FLIP FLOP
3 I/P AND GATE
OR GATE
XOR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
ex
cl
u
Sl.No.
1.
2.
3.
4.
5.
6.
7.
.c
o
APPARATUS REQUIRED:
ee
THEORY:
.e
A counter is a register capable of counting number of clock pulse
arriving at its clock input. Counter represents the number of clock pulses
arrived. An up/down counter is one that is capable of progressing in

increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of
the counter is controlled by up/down signal. When this signal is high counter
goes through up sequence and when up/down signal is low counter follows
reverse sequence.
K MAP
Page No. 75
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.b
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cl
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si
STATE DIAGRAM:
Page No. 76
CHARACTERISTICS TABLE:
Q
Qt+1
0
1
0
1
0
0
1
1
J
0
1
X
X
K
X
X
1
0
.e
ee
ex
cl
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si
ve
.b
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sp
ot
.c
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LOGIC DIAGRAM:
TRUTH TABLE:
Page No. 77
.b
l
C
KB
X
0
1
X
X
0
1
X
X
X
0
1
X
X
0
1
JB
1
X
X
0
1
X
X
0
0
1
X
X
0
1
X
X
.c
o
KA
X
0
0
0
1
X
X
X
X
X
X
X
0
0
0
1
sp
ot
JA
1
X
X
X
X
0
0
0
0
0
0
1
X
X
X
X
og
Next State
QA+1 Q B+1 QC+1
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
JC
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
KC
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
ve
Input
Present State
Up/Down QA QB QC
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
ex
cl
u
si
PROCEDURE:
(i)
(iii)
.e
w
w
RESULT:
ee
(ii)
EXPT NO. :
DATE
:
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
AIM:
Page No. 78
To design and implement

(i)
Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
APPARATUS REQUIRED:
SPECIFICATION QTY.
IC 7474
2
IC 7432
1
1
35
sp
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COMPONENT
D FLIP FLOP
OR GATE
IC TRAINER KIT
PATCH CORDS
og
Sl.No.
1.
2.
3.
4.
ve
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l
THEORY:
si
A register is capable of shifting its binary information in one or both
cl
u
directions is known as shift register. The logical configuration of shift
ex
register consist of a D-Flip flop cascaded with output of one flip flop
.e
ee
connected to input of next flip flop. All flip flops receive common clock
The simplest
pulses which causes the shift in the output of the flip flop.
possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.
PIN DIAGRAM:
Page No. 79
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LOGIC DIAGRAM:
.e
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SERIAL IN SERIAL OUT:
TRUTH TABLE:
Page No. 80
Serial in
Serial out
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o
CLK
sp
ot
LOGIC DIAGRAM:
.e
ee
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cl
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SERIAL IN PARALLEL OUT:
TRUTH TABLE:
CLK DATA
1
1
2
0
3
0
4
1
QA
1
0
0
1
OUTPUT
QB
QC
0
1
0
0
0
0
1
0
QD
0
0
1
1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
Page No. 81
Q0
1
0
0
0
Q1
0
0
0
0
O/P
1
0
0
1
sp
ot
Q2
0
0
0
0
og
Q3
1
0
0
0
.b
l
CLK
0
1
2
3
.c
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TRUTH TABLE:
ve
LOGIC DIAGRAM:
.e
ee
ex
cl
u
si
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
CLK
DA
DATA INPUT
DB
DC
DD
QA
OUTPUT
QB
QC
QD
Page No. 82
1
2
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
PROCEDURE:
(ii)
(iii)
og
sp
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(i)
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ee
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RESULT:
PREPARATORY EXERCISE
1. Study of logic gates
Page No. 83
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cl
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.e
w
w
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2. Design and implementation of adders and subtractors
using logic gates
Page No. 84
m
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sp
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cl
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ex
ee
.e
w
w
w
3. Design and implementation of code converters using
logic gates
Page No. 85
m
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sp
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ve
si
cl
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ex
ee
.e
w
w
w
4. Design and implementation of 4-bit binary
adder/subtractor and BCD adder using IC 7483
Page No. 86
m
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sp
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ve
si
cl
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ee
.e
w
w
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5. Design and implementation of 2-bit magnitude
comparator using logic gates, 8-bit magnitude comparator
using IC 7485
Page No. 87
m
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sp
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ve
si
cl
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ex
ee
.e
w
w
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6. Design and implementation of 16-bit odd/even parity
checker generator using IC 74180
Page No. 88
m
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sp
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og
.b
l
ve
si
cl
u
ex
ee
.e
w
w
w
7. Design and implementation of multiplexer and
demultiplexer using logic gates and study of IC 74150 and
IC 74154
Page No. 89
m
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sp
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og
.b
l
ve
si
cl
u
ex
ee
.e
w
w
w
8. Design and implementation of encoder and decoder
using logic gates and study of IC 7445 and IC 74147
Page No. 90
m
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sp
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og
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ve
si
cl
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ex
ee
.e
w
w
9. Construction and verification of 4-bit ripple counter and

Mod-10/Mod-12 ripple counter
Page No. 91
m
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sp
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og
.b
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si
cl
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ex
ee
.e
w
w
10. Design and implementation of 3-bit synchronous

up/down counter
Page No. 92
m
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sp
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si
cl
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ex
ee
.e
w
w
11. Implementation of SISO, SIPO, PISO and PIPO shift

registers using flip-flops
Page No. 93

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LAB MANUAL

1. Verification of Boolean theorems using digital logic gates

(ii) Binary to gray and vice-versa

(i) BCD to excess-3 code and voice versa

4. (a) Design and implementation of Adders and Subtractors using

Design and implementation of parity checker /generator using

(b) Design and implementation of 4 bit binary Adder/ subtractor

basic gates and MSI devices.

7. Design and implementation of Multiplexer and De-multiplexer using

8. Design and implementation of application using Multiplexer.

9. Construction and verification of 4 bit ripple counter and Mod-10 /

Mod-12 Ripple counters

NAME OF THE EXPERIMENT

STUDY OF LOGIC GATES

To study about logic gates and verify their truth tables.

is low level when any one of the inputs is low.

The OR gate performs a logical addition commonly known as OR

is low level when both the inputs are low.

input is low. The output is low when the input is high.

The NOR gate is a contraction of OR-NOT. The output is high when

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

2-INPUT NAND GATE:

3-INPUT NAND GATE :

DESIGN OF ADDER AND SUBTRACTOR

A full adder is a combinational circuit that forms the arithmetic sum

The full subtractor is a combination of X-OR, AND, OR, NOT Gates.

K-Map for CARRY:

K-Map for SUM:

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

K-Map for CARRY:

K-Map for DIFFERENCE:

K-Map for BORROW:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

K-Map for Difference:

K-Map for Borrow:

Difference = ABC + ABC + ABC + ABC

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

To design and implement 4-bit

different binary code.

four outputs. Gray code is a non-weighted code.

combinational circuit is designed. The Boolean functions are obtained from

K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible

BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

K-Map for G0:

K-Map for G1:

Gray code output

GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

K-Map for B1:

K-Map for B0:

BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

K-Map for E2:

K-Map for E1:

K-Map for E0:

EXCESS-3 TO BCD CONVERTOR

Connections were given as per circuit diagram.