A Main Project Report Entitled

On

DESIGN AND IMPLEMENTATION OF AHB TO AHP BRIDGE USING

VERILOG CODE ON SPARTAN 3 BOARD

A report Submitted in partial fulfillment of the

Academic requirements for the award of the degree of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING
By

K.SHIVA KUMAR

(10QM1A0437)

P.KAVYA REDDY

(11QM1A0470)

N.BALA MURALI KRISHNA

(11QM1A0456)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ABSTRACT
DESIGN AND IMPLEMENTATION OF AHB TO AHP BRIDGE USING
VERILOG CODE ON SPARTAN 3 BOARD
The AHB2APB interfaces AHB and APB. It buffers address, controls the data from the
AHB, drives the APB peripherals and return data along with response signal to the AHB .The
AHB2APB interface is designed to operate when AHB and APB clocks have the any
combination of frequency and phase.TheAHB2APB performs transfer of data from AHB to APB
for write cycle and APB to AHB for Read cycle. Interface between AMBA high performance bus
(AHB) and AMBA peripheral bus (APB) provides latching of address, controls and data signals
for APB peripherals. It also supports APB compliant slaves and peripherals which require
additional wait states.
In this project, we mainly concentrates on synthesis and simulation of AMBA based
AHB2APB Bridge using Verilog HDL (Hardware Description Language) for implementation
purpose in Xilinx ISE design suite. AHB2APB Bridge interfaces AHB and APB buses. It is
required to bridge the communication gap between low bandwidth peripherals on APB with the
high bandwidth ARM Processors and/or other high-speed devices on AHB. This is to ensure that
there is no data loss between AHB to APB or APB to AHB data transfers.

Hardware Required
Spartan -3 board.

Software Required
Xilinx ISE design suite.

Block diagram
AHBtoAPB
AHB

APB

Bridge

Design of AHB2APB Bridge

Hclk

Pclk

Hreset

Preset

Hsel

Psel

Htrans[1:0]
Haddr[31:0]

AHB to APB
Bridge

Hwrite

Pen
Paddr[31:0]
Pwrite

Hwdata [31:0]

Pwdata

Hrdata[31:0]

Prdata

Hready

Pin details of AHB to APB bridge