Term End Examination - May 2013

Course

: EEE598

Class NBR

Time

: Three Hours

Computer Aided Design for VLSI

Slot: G1+TG1

2334
Max.Marks:100

NOTE : Answer to the point. For algorithms, write the sequence of steps or pseudo code as shown
below and not in paragraphs:
Algorithm
Input values, define variables
Step1 :
Step2:
.
Output results
End
Answer ALL Questions
1.

a) Explain the mapping of Y chart methodology in VLSI Design.

[6]

b) What is the difference between floorplanning and placement for a full custom

[4]

design?
2.

The graph shown in Fig.1 represents a bisectional partition of a digital circuit.

[4]

a) If nodes 1 and 4 are swapped across the partition, what is the gain g14?
b) Draw the resulting partition and find the cut-size.

[3]

Fig.1

Page 1 of 4

3.

What is clock skew? How is H-tree used to distribute the clock signal without skew?

[6]

Draw a H-tree and X-tree to distribute clock to 16 points.

4.

The figure in Fig.2 models 2 subtrees where ti is the delay from node i to one of its

[6]

leaves. The wire which connects the 2 subtress is modeled as a segment. Find the
tapping point to route a clock signal with zero skew.

Fig.2
5.

Simulated annealing is a general optimization technique for a large search space.

[7]

Formulate an algorithm which uses simulated annealing to optimize a floor plan.

6.

Consider the floorplan shown in fig.3. The dimensions of modules 1 to 8 are (2,4),

[10]

(1,3), (3,3), (3,5), (3,2), (5,3), (1,2), (2,4) respectively. Draw a slicing tree for the floor
plan and find the corresponding polish expression.

Fig.3
7.

a) Draw the positive step lines and negative step lines for the module arrangement
shown in the fig.4. Hence form a valid sequence pair.
b) For m modules in a floor plan, how many sequence pairs are possible?

Page 2 of 4

[10]

c) Name two ways to find a neighbor to a sequence pair i.e to perturb the floorplan
solution.

Fig.4
8.

Formulate a partitioning driven placement algorithm. Illustrate two schemes for the [5+5]
selection of cutlines and the sequence in which they are processed as recommended by
Breuer.

9.

In the grid shown in fig.5, route the net using Hadlocks detour algorithm. Fill the grid

[6]

with detour numbers.(S-source,T-target).

Fig.5
10.

Illustrate Mikami-Tabuchis line search algorithm on the grid shown in Fig.6. Draw
trial lines.(S-source,T-target)

Fig.6

Page 3 of 4

[6]

11.

For the following channel, route the nets using Left edge algorithm. Also draw HCG

[12]

and VCG.

12.

What is dogleg in channel routing? Illustrate with an example.

[4]

13.

How is Power and Ground routing done by inter digitated approach? Illustrate with a

[6]

floor plan. Do all the nets have same widths?

Page 4 of 4