IP Design for low power

Most complex chips are designed

using IP
Well designed IP can be used
in many different applications

Design aspects for good low power IP

Design partitioning for different low power
strategies
Explicit support for power gating
Reference power intent files
Clocking and reset strategy
IP packaging
IP Verification for various low power strategies
Techniques used in IP implementation
Multi VT
Clock gating
Power gating
Voltage scaling

Different IP types need different low power
support
Memories: Normal/retention/power off mode
Physical layer interfaces: Normal operation / Idle
/ shut down
Configurable soft IP
Different low power techniques
Different operating modes
User configurable
Architecture and Partitioning for
Power Gating
Decide, when and how the IP will be powered up
or down
Decide, which blocks will be power gated and
which are not
Design the power up and power down sequences
Design a power controller
Determine signals to be isolated during power
down
Develop initial strategy for clock, reset and power
control signal
Power Down Mode
SW and/or HW controlled
SW writes the power down bit in the power
controller register
Power controller executes the power down
sequence
Power controller shuts down the subsystem after
a certain idle time
Power controller must take in account
possible pending operations or transactions
before starting the power down sequence
Partitioning constraints
Operating modes
Blocks that can be powered off
Blocks with retention mode
Blocks with clock gating
Always alive (Wake up logic, bus interface, etc)
WAKE UP strategies
SW driven
Power on sequence started by writing a certain
register/bit
Software controlled power mode / operating
mode switching
HW driven
Power on sequence started by external HW signal
Data / Signal driven
Triggered by activity on communication interface
(bus,communication port, etc.)

Autonomous wake up
System is powered up by internal timer or other
circuitry