PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC

PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC
757-039-11
REV A
PAGE 1 OF 11
REVISIONS
REV ECO
+13VDC
9) Power & Watchdog
AGND
COIL
GNDA
TT-BACKUP
MAINDOOR DET
BILLVAL DET
DOORVAL OUT
DROPDOOR DET
CARDCAGE DET
+25VDC
BGND
COIL
GNDB
BY/DATE CHK/DATE
DESCRIPTION
EA
PROTOTYPE RELEASE
TDW/01NOV99
EB
USED MAIN 5 VOLTS FOR U62 PULLUPS
TDW/08NOV99
5043
PRODUCTION RELEASE
TDW/27DEC99
RESET MEZZ
4) QUARTs & I/O
SPEAKERSPEAKERA+
PROG TxDg
PROG RxDg
J2
+13VDC
+13VDC
GNDA ( To NETPLEX Ground )
SPEAKERTT-BACKUP
SPEAKERA+
SPEAKERB+
MAINDOOR DET\
BILLVALDET\
DOORVALOUT
DROPDOOR DET\
JKPT RST
CARDCAGE DET\
PROG TxDg
PROG RxDg
RxDf
LPSW
NETPLEXRxD
TxDf
I/O RESET\
NETPLEXTxD
DCS TxDh
DCS RxDh
SRESET\
SIN IN
COMM TxDc
COMM RxDc
COMM RTS
COMM CTS
TxDb
RxDb
LPSW
I/O RESET
RESET CPLD/F/O
RESET QUART
RESET\ SIMM
TxDd
RxDd
TxDd
RxDd
T
M
S
T T
D D
I O
ISP (OPTIONAL)
ISP3
A[1..31]
FAILURE
SYS CLK
PAGE 5
7) Video BLOCK & VDAC

A[1..31]
ISP[1..6]
IA[1..3]
3
CR8
1
1N914
3
1
1N914
3
1
CR13
1N914
CR15
NOTES: (UNLESS OTHERWISE INDICATED)

1. ALL RESISTORS EXPRESSEDINOHMS1/4W5%
ALL CAPACITORS EXPRESSED IN MICROFARADS
2. ALL 14 PIN ICS, PIN 14 IS PWR, PIN 7 IS GND
ALL 16 PIN ICS, PIN 16 IS PWR, PIN 8 IS GND
ALL 20 PIN ICS, PIN 20 IS PWR, PIN 10 IS GND
FID1 FID2 FID3
COLORSEL\
MEZRDY\
MEZ1SEL\
+13VDC
+13VDC
+25VDC
+25VDC
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
GAMESEL\
VBIT SEL\
VOUT
FWR0A\
FWR1A\
MM AUDIO1
RAM SEL\
FWR1A\
SPEAKERB+
SCL
SDA
USART TXD
USART RXD
USART CLK
V GND
RED
GREEN
BLUE
DOT CLK
BLANK2
MM RED
MM GREEN
MM BLUE
MM VERT
MM HORIZ
V SYNC
H SYNC
AUDIO
WCHDOGSEL\
NORMAL STRAPPING:
1-15,3-13, 4-12,
5-6 & 7-8
MULTI-MEDIA STRAPPING:
15-16, 13-14, 11-12,
6-10 & 8-9
PAGE 3
PX[0..7]
R187 75
1
2
R189 75
1
2
R188 75
1
2
BLOCKRW
FLATCH1
FLATCH2
BLANK1
BLANK2
DD[0..7]
FD[0..15]
BD[0..15]
SC-1
BA0
BA1
PAGE 7
DOT CLK
256COLOR
VBLK0 SEL
VBLK1 SEL
BLOCK
CA0
FWR0B\
FWR1B\
+13VDCLOW\
RESET\ VIDEO
BLOCKRW\
FLATCH1
FLATCH2
BLANK1
BLANK2
DD[0..7]
FD[0..15]
BD[0..15]
SC-1
BA0
BA1
DOT CLK
256COLOR\
VBLK0 SEL\
VBLK1 SEL\
BITBLITZ CLK
H SYNC
BLOCK
V SYNC
3. JUMPER OPTIONS SHOWN ONPAGE2

FOR PCB USEONLY
FIDUCIAL
RED
CA0
+13VDC LOW
A[1..31]
BLTCLK
D[0..15]
BLT CLK
BITBLITZ SEL\
RD
BITBLITZ SEL
BLTRDY\
RESET VIDEO BLTRDY
VERTOUT
BBSTB
BLOCKRW
FLATCH1
WR0
FLATCH2
WR1
BLANK1
BLANK2
DD[0..7]
FD[0..15]
BD[0..15]
SC-1
BA0
BA1
DOT CLK
256COLOR
BITBLITZ CLK
LPSTB
H SYNC
BLOCK
PAGE 6
V SYNC
DOT CLK2
ISP[1..6]
J5
FWR0A\
RESET MEZZ
INT1\
MM CLK
SALE
MEZ2SEL\
MEZ2 SEL\
BOOTSEL\
6) BitBlitz & VDRAM

CA0
FWR0B
FWR1B
D[0..15]
RD
RESET VIDEO
MN BLUE
MN RED
MN HSYNC
MN GREEN
DOT CLK2
MN VSYNC
CR14
X1
1N914
3
1N914
CR10
1N914
V GND
D[0..15]
VBATT
QRT1 SEL
QRT2 SEL
OUT SEL
GAME SEL
SOUND SEL
VBIT SEL
IO RD
VOUT
IO WR
FWR0A
FWR EN
FWR1A
RD
RESET SIMM
SENET SEL
FWR0B
CEOUT
FWR1B
WCHDOG SEL
VBLK0 SEL
VBLK1 SEL
WR0
WR1
COLOR SEL
SENET SEL\
E22
COLOR SEL
RED
IO RD
BLUE
IO WR
GREEN
PD[0..7]
PX[0..7]
EPR SEL
RAM SEL
FLH SEL
IOT SEL
MEZ2 SEL
BOOT SEL
A[1..31]
SENET SEL
CR9
RESERVED
FOR
SLOT
3) Main Memory
IO RD
IO WR
RESERVED
FOR
SLOT
SENRDY\
PD[0..7]
RED
BLUE
GREEN
10 PIN
FAILURE
SCLK256
VCC
28PINS
IO2B2
IO3B2
OUT5
OUT6
OUT7
SENRDY
+13VDC
RESET CPU/SEN/AUD
A[1..31]
GNDA
TO CARD CAGE SWITCH
A
SENSTB\
SENCLK
SDATATxA
SDATARxA
SDATA ADR
SDATATxB
CONNECTED TO U71 (5)
SENGND
SENRST\
GNDB
GNDB
MM BLUE
B
MM RED
MM HORIZ
MM GREEN
V GND
MM VERT
+25VDC
VCC
+5VDC
1
2
3
4
5
6
7
8
9
10
GREEN
BLUE
V SYNC
MN VSYNC
H SYNC
MN HSYNC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MM RED
MN RED
MM GREEN
MN GREEN
MN BLUE
MM BLUE
MM VERT
MM HORIZ
1A
1C
2A
2C
3A
3C
4A
4C
5A
5C
6A
6C
7A
7C
8A
8C
9A
9C
10A
10C
11A
11C
12A
12C
13A
13C
14A
14C
15A
15C
16A
16C
17A
17C
18A
18C
19A
19C
20A
20C
21A
21C
22A
22C
23A
23C
24A
24C
25A
25C
26A
26C
27A
TO
27C
28A MULTI-MEDIA
28C
29A
29C
30A
FROM
30C MULTI-MEDIA
31A
31C
32A
TO MULTI-MEDIA
32C
757 039 11
SCL
SDA
SENSTB
SENCLK
SDATA TxA
SDATA RxA
SDATA ADR
SDATA TxB
SENRST
IOT SEL\
FLH SEL\
IOT SEL
BITBLITZ CLK FLH SEL
RAM SEL
RD
PA SEL
PAGE 2
EPR SEL
J11
RESET\
INT1\
BOOTSEL\
GAMESEL\
VBIT SEL\
VOUT
CE\OUT
PASEL\
WR0\
WR1\
DWG NO:
5) SENET
USART CLK
64 PIN DIN
PD[0..7]
MM AUDIO1
IO2B2
IO3B3
OUT5
OUT6
BBSTB
1A
1C
2A
2C
3A
3C
4A
4C
5A
5C
6A
6C
7A
7C
8A
8C
9A
9C
10A
10C
11A
11C
12A
12C
13A
13C
14A
14C
15A
15C
16A
16C
17A
17C
18A
18C
19A
19C
20A
20C
21A
21C
22A
22C
23A
23C
24A
24C
25A
25C
26A
26C
27A
27C
28A
28C
29A
29C
30A
30C
31A
31C
32A
32C
RESERVED FOR MULTIMEDIA

20 PINS
AUSTRALIAN
SLOT
CONNECTION
N/C-------------------MECH SW---------N/C--------------------DET 1----------------LPSTB\--------------DET2-----------------GND------------------CARDCAGE DET
SENSTB\-----------SENCLK-------------SDATA TxA--------SDATA RxA-------SDATA ADR-------SDATA TxB--------SENGND------------SENRST\-----------GNDB----------------GNDB----------------L6-4-------------------V REEL6-----------L6-1------------------DET 6----------------L6-3------------------L6-2------------------+25VDC------------+25VDC------------DET 3----------------V REEL1-----------DET 5----------------V REEL2-----------L1-2-------------------V REEL3-----------DET 4----------------V REEL4-----------L1-1------------------V REEL5-----------L1-3-------------------L1-4-------------------L2-1-------------------L2-2-------------------L2-3-------------------L2-4-------------------L3-1-------------------L3-2-------------------L3-3-------------------L3-4-------------------L4-1-------------------L4-2-------------------L4-3-------------------L4-4-------------------L5-1-------------------L5-2-------------------L5-3-------------------L5-4--------------------
(VCC GND PLANE)

+5VDC
SCL
SDA
POWERSAVE
RxDa
DTR
TxDa
DIR
DCD
USART TXD
LPSTB\
USART RXD
WR1
WR0
BBSTB
BLTRDY
RESET CPU/SEN/AUD
FAILURE BITBLITZ SEL
BLT CLK
SENRDY
SYS CLK
D[0..15]
PAGE 4
QUART CLK
QRT1 SEL\
QRT2 SEL\
OUT SEL\
SOUND SEL\
MM[1..5]
J1
PD[0..7]
RESET CPLD/F/O
IO RD
IO WR
QUART CLK
IA[1..3]
VCC
IO2B2
IO3B2
OUT5
OUT6
OUT7
MEZRDY
MEZ1 SEL
IA[1..3]
FWR EN\
IO RD
IO WR
QUART CLK
QRT1 SEL
QRT2 SEL
OUT SEL
SOUND SEL
MM AUDIO1
SCLK256
MM CLK
S ALE
SLV SEL
ISP[1..6]
D[0..15]
IA[1..3]
PD[0..7]
FWR EN
OUT7
SCLK256
INT0
INT1
INT2
INT3
A25
A[1..31]
ISP[1..6]
+25VDC
1A
1B
2A
2B
3A
3B
4A
4B
5A
5B
6A
6B
7A
7B
8A
8B
9A
9B
10A
10B
11A
11B
12A
12B
13A
13B
14A
14B
15A
15B
16A
16B
17A
17B
18A
18B
19A
19B
20A
20B
21A
21B
22A
22B
23A
23B
24A
24B
25A
25B
26A
26B
27A
27B
28A
28B
29A
29B
30A
30B
31A
31B
32A
32B
PAGE 9
VCC
VERTOUT
INT3\
A25\
VERTOUT
INT3
A25
A[1..31]
2
A
VOUT
2) CPU
TxDb
RxDb
R191
J10
INT0\
INT0
RxDa
DTR
TxDa
DIR
DCD
0 OHM
3 Amps
VBATT
INT2
CE\OUT
+13VDC LOW
VBATT
INT2
1
2
3
4
5
6
7
8
9
ISP1
ISP6
SRESET
SIN IN
COMM TxDc
COMM RxDc
COMM RTS
COMM CTS
POWER SAVE
16
T
C
K
SRAM BAT LOW

TT BAT LOW
RESET CPU/SEN/AUD
RESET I/O
RESET CPLD/F/O
RESET QUART
CEOUT
RESET SIMM
TxDd
VOUT
RxDd
RESET VIDEO
INTERROGATE
SRAM BAT LOW\

TT BAT LOW\
RESET\ CPU/SEN/AUD
RESET\ I/O
RESET QUART
DCS TxDh
DCS RxDh
32 PIN DIN
INTERROGATE
INTERROGATE
NETPLEX TxD
NETPLEX RxD SRAM BAT LOW
TT BAT LOW
RESET CPU/SEN/AUD
RESET I/O
J4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
IO RD\
IO WR\
SLVSEL\
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
IA1
IA2
IA3
GND
GND
SYSCLK
RD\
WR0\
WR1\
CCAGE OPEN
DDOOR OPEN
MDOOR OPEN
BVAL OPEN
WCHDOG SEL
TT-DET
TT-DISABLE
TT-CNTR1
TT-CNTR2
TT-DET\
TT-DISABLE\
TT-CNTR1
TT-CNTR2
TT-DET
TT-DISABLE
TT-CNTR1
TT-CNTR2
RxDf
TxDf
ISP2
1A
1B
2A
2B
3A
3B
4A
4B
5A
5B
6A
6B
7A
7B
8A
8B
9A
9B
10A
10B
11A
11B
12A
12B
13A
13B
14A
14B
15A
15B
16A
16B
PA RESET\
PA RESET
CCAGE OPEN\
DDOOR OPEN\
MDOOR OPEN\
BVAL OPEN\
CCAGE OPEN
DDOOR OPEN
MDOOR OPEN
BVAL OPEN
JKPT RST
PA SEL\
EPR SEL\
For Reference
+13VDC
(14.74560MHz)
+13VDC
REF X1
HEADER, VIDEO 1
16 pin DIP Socket
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT
COVENANTS IT WILL NOT BE USED IN ANY MANNER
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND.
DRAWN
DATE
TDW
01NOV99
ELECTRONIC DIAGRAMS & PARTS: GAME KING PLUS 19 UPRIGHT (821-352-00) - (PRELIMINARY)
CHECKED
DATE
INTERNATIONAL GAME TECHNOLOGY

9295 PROTOTYPE DRIVE RENO, NV 89511
TITLE
SCHEMATIC, GAME KING 2

PROTECT GAME KING CTR/TT
DWG. SIZE
DWG. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
1 OF 11
SHT __
__
AUGUST 24, 2001
757-039-11
R71
REV A
PAGE 2 OF 11
VCC
10K
U26
VCC
VCC
RP13
1
2
3
4
5
6
7
8
9
10
8
7
6
5
A24
A25
A26
A27
A28
A30
A29
A31
RP6
1
2
3
4
10K
A27
A28
A29
1
2
3
A
B
C
A30
A31
6
4
5
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
EPR SEL\
FLH SEL\
RAM SEL\
BLT SEL\
SLV SEL\
IO SEL\
PA SEL\
MEZZ1 SEL\
15
14
13
12
11
10
9
7
EPR SEL\
FLH SEL\
RAM SEL\
BITBLITZ SEL\
SLV SEL\
0000 0000h
0800 0000h
1000 0000h
1800 0000h
2000 0000h
2800 0000h
3000 0000h
3800 0000h
PA SEL\
MEZ1 SEL\
74HC138
1
VCC
VCC
1
10K
D
INT0\
(1,4)
from QUART #2
R96
R83, R85, R89, R101 and R66

ARE NOT USED AT THIS TIME
2
U18A
RP5
100
INT1\
from MULTIMEDIA
INT2
Low +13VDC
2
74HC14
(1,9)
INT3\
(1,4)
from QUART #1
R72
100
U3B
A25\
(1,4)
A16
A17
A18
A19
A20
A21
A22
A23
A25
VCC
1
2
3
4
5
6
7
8
9
10
R59
910
2
RESET\ CPU/SEN/AUD
TP
U3C
BLT CLK
(1,6)
R18
BLT CLK1
U3A
2
CPU CLK1
74HC04
CPU CLK
20
INTO
INT1
INT2/INTR
INT3/INTA
70
64
61
LOCK
HOLD
HLDA
55
CLK2
56
RESET
74HC04
R58
1K
U16
J5,2C
MM CLK1
10
41
40
39
38
37
36
35
30
29
28
27
26
25
24
20
19
ALE
DT/R
DEN
A1
A2
A3
78
68
67
49
46
45
AS
READY
76
79
W/R
66
BLAST/FAIL
BE0
BE1
69
52
51
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
QUART CLK
R26
D7
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
D8
C7
11
1
C
OC
+ C5
84 pin PLCC Socket (Through Hole)

R79
R3
8
13
10
12
11
3
9
XTALOUT
S0
S1
S2
OE
GND
ISP1
ISP2
ISP3
ISP4
74AC32
10
R88
1
U42C
D15
D14
D13
D12
D11
D10
D9
D8
14.74560 MHz
R92
10K
TP
TP
TP
TP
2
1K
2
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
D8
11
1
C
OC
19
18
17
16
15
14
13
12
19
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
R93
10K
SENRDY\
(1,5)
74AC32
R80
1
1
R51
J5,4A
10K
2
(1)
2
10K
SIMMRDY\
(10)
(1,3,4,5,6,7,10)
(1,4,7,11)
18
17
16
15
14
13
12
11
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD[0..7]
G
DIR
(1,4,5,7,11)
74AC245
VCC
RP11
1
2
3
4
5
6
7
8
9
10
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
74AC573
E2
10K
VCC
VCC
RP8
D7
D6
D5
D4
D3
D2
D1
D0
RP3
1
2
3
4
5
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
RP7
D15
D14
D13
D12
D11
D10
D9
D8
10K
10K
12
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
A15
A14
A13
A12
A11
A10
A9
A8
VCC
8
(1,6)
10K
2
(1,3,4,6,7,10)
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
U32
TP
24.0143 MHZ
11.9996 MHZ
26.6722 MHZ
3.6864 MHZ
J5,3A
(1,5)
(1,3)
(1,6)
(1,3,6,10)
(1,9)
(1,3,6,7,10)
(1,3,4,5,7,11)
(1,3,4,5,7)
(1,5)
(1)
(1,3,6,10)
U52
74AC573
VCC
U3D
2 BITBLITZ CLK1
SYS CLK
IOT SEL\
BBSTB
WR0\
RESET CPLD/F/O
RD\
IO WR\
IO RD\
FAILURE
S ALE
WR1\
D[0..15]
A7
A6
A5
A4
IA3
IA2
IA1
DT/R\
XBUFF
FLPCLK
CPUCLK
CLKA
CLKB
CLKC
CLKD
XTALIN
1K
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
0.1uF
16
19
2
U3F
E4
10K
U40
74HC04
BITBLITZ CLK
R82
IA[1..3]
80960SA
QUART CLK1
A[1..31]
R20 STRAPPED DISABLES THE PLL

(TRI-STATES OUTOUTS)
20
(1,6)
74AC32
0=OPEN , 1=INSTALLED
TESTING
PURPOSE
ONLY
(1,4)
VDD
VBATT
32K
CPU CLK
R10 R9 R19 FREQUENCY
-----------------------------------0
1 0 32.0087 MHz
1
1 0 29.4912 MHZ
0
0 0 24.0143 MHz (DEFAULT)
VCC
IO_EN
EXTRDY
10K
U42B
10uF
VDD
32XIN
32XOUT
STRAPPING OPTIONS
R20
1K
TDI
TMS
TCK
TDO
15
16
17
30
R86
MEZRDY\
R70
R19
1K
24
25
26
27
28
29
38
33
34
35
36
CY2291
2
R9
1K
R10
1K
OPTIONAL FOR DIFFERENT

CPU SPEEDS
SYSCLK
IOTSEL
BBSTB
WR0
RESET
RD
IO_WR
IO_RD
FAIL
SALE
WR1
2
10K
U42A
CLK
EPROMSEL
RAMSEL
MEZ1SEL
WR
BITSEL
SLVSEL
IOSEL
ALE
AS
BLAST
RDY
DEN
BE0
BE1
NC
OPT 0
OPT 1
OPT 2
RAMNW
OPT 4
A1
A2
A3
1
1
5
6
7
8
4
3
2
1
10K
R94
757 039 11
TP
Y2
R99
5
39
40
43
44
10K
(1,6,7)
U4
14.7456 MHz 7
14
15
17
18
5
R65
ISP[1..6]
REF U16
1
2
BLTRDY\
VCC
74HC04
10K
XC9536, BUSS CONTROLLER
E17
11
4
20
1
6
2
3
4
7
8
9
11
12
13
14
22
1
37
18
20
19
42
20
RP1
CLK
EPR SEL\
RAM SEL\
MEZ1 SEL\
WR
BITBLITZ SEL\
SLV SEL\
IO SEL\
ALE
AS\
BLAST\
READY\
DEN\
BE0\
BE1\
FLH SEL\
10K
D0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
R66 1K
(1)
(1)
1
U29
10K
E12
R28
R101 1K
J5,4C
DWG NO:
(1)
U3E
MM CLK
TP
1
2
3
4
5
6
7
8
9
10
R89 1K
20
R2
57
58
59
60
A9
A10
A11
A12
A13
A14
A15
A1
A2
A3
A4
A5
A6
A7
A8
R85 1K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(1,4,5,9,11)
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
18
22
32
34
43
48
54
63
72
74
77
84
7
16
15
14
13
12
11
10
9
8
5
4
3
83
82
81
80
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
74HC04
R64
10K
1
2
3
4
5
6
7
8
9
10
VCC
10K
VCC
VCC
RP4
RP9
17
21
31
33
44
47
53
71
73
6
1
62
(1)
R83 1K
J4,15A
(1,3)
(1,3)
(1,3)
(1,6)
(1)
1
2
3
4
5
6
7
8
9
10
10K
13
20
ETCH
74HC04

RETURNED ON DEMAND.
VCC
U45
U4
U19
U42
U46
U31
U32
U19
0.1uF
C63
C34
0.1uF
C8
0.1uF
0.1uF
C49
0.1uF
C19
VSS
4
AUGUST 24, 2001
C4
0.1uF
0.1uF
C41
C47
0.1uF
22uF
+ C20
U40
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
2 OF 11
SHT __
__
17
757-039-11
(1,9)
(1,9)
(1,2,6,7,10)
(1,9,10)
REV A
PAGE 3 OF 11
VBATT
CE\OUT
D[0..15]
D[0..15]
VOUT
(1,2,4,5,6,7,10)
STUFF FOR RTC 62423

(REMOVE FOR DALLAS RTC)
A[1..31]
R61
0 OHM
VCC
EPSON RTC SEL\
CE\OUT
SRAM CE\
U39
2
U41A
(1)
BOOT SEL\
0000 0000H
0020 0000H
4
5
6
7
TP
(1,2)
Y0
Y1
Y2
Y3
A
B
2
3
A21
A22
74HC139
EPR SEL\
VCC
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(2M)
VPP(A17)
40
1
VCC
VPP
2
20
CE
OE
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
R113
1K
A1
A2
A3
A4
5
7
9
10
A0
A1
A2
A3
4
2
13
11
ALE
CS0
WR
RD
20
VOUT 24
CS1
VDD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
WR0\
RD\
R104 1K
(1,10)
DO
D1
D2
D3
19
16
15
14
STD.P
GND
GND
GND
GND
GND
GND
GND
(VDD)
(VDD)
1
3
6
8
12
17
18
21
23
22
U21
D0
D1
D2
D3
15
RTC DS1215S
VCCO
VCCI 16
TP
10
BAT2
14
BAT1
ROM/RAM
RST
WE
OE
CEO
CEI
TP
1K
VBATT
R60
1K
Y3
X2
X1
R62
9
13
3
12
11
TP
RTC 62423
32.768 MHz
D0
30
11
GND
GND
REF U39
_10) Memory Options
BASE
A[1..31]
SRAM CE
VBIT SEL
GAME SEL
256KX16 EPROM 40 pin DIP Socket

120nS
GAME SEL\
(10)
VCC
OPTIONAL REAL TIME CLOCK
SRAM CE\
U46
D[0..15]
VOUT
U7
(1,10)
(1,7)
(1,7)
VBIT SEL\
XM1 SEL\
XM2 SEL\
XM3 SEL\
XM4 SEL\
VBLK0 SEL\
VBLK1 SEL\
0800 0000H
0820 0000H
0840 0000H
0860 0000H
0880 0000H
08A0 0000H
08C0 0000H
08E0 0000H
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
3
A
B
C
A21
A22
A23
VCC
74HC138
6
4
5
G1
G2A
G2B
R31
1
1K
R30
2
1K
XMB SEL
XM1 SEL
XM2 SEL
XM3 SEL
XM4 SEL
RESET SIMM
VCC
1
2
(1,2,4,5,7)
8
7
6
5
RD
1
FW R0A\
74AC32
10K
IO WR\
IO RD\
FW R1A\
74AC32
RAM SEL\
74AC32
SRAM OE\
SRAM OE
U25C
PAGE 10
12
WR0\
(1,2,6,10)
FWR1A
U25B
10
(1,2)
FWR0A
U25A
RD\
(1,2,6,7,10)
757 039 11
WR0
WR1
RP10
1
2
3
4
R81
10K
(1,2,4,5,7,11)
DWG NO.
FLH SEL\
RESET\ SIMM
(1,2)
(9,10)
74AC32
13
SRAM W E0\
11
SRAM WE0
U25D
12
WR1\
(1,2,6,10)
13
SRAM W E1\
11
74AC32
SRAM WE1
FWR0B
FWR1B
U19D
12
(1,4)
FWR EN\
74AC32
13
FW R0B\
11
FW R0B\
FW R1B\
U42D
1
2
(1,10)
(1,10)
FW R1B\
74AC32
U19A
U20
A16
A17
A18
VCC
R57
1
1
2
3
A
B
C
6
4
5
G1
G2A
G2B
1K
2
A19
IOT SEL\
(1,2)
(1,7,10)
(1,7,10)
FW R0A\
FW R1A\
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
MEZ2 SEL\
QRT1 SEL\
SENET SEL\
WCHDOG SEL\
QRT2 SEL\
SOUND SEL\
COLOR SEL\
OUT SEL\
MEZ2 SEL\
QRT1 SEL\
SENET SEL\
WCHDOG SEL\
QRT2 SEL\
SOUND SEL\
COLOR SEL\
OUT SEL\
28000000h
28010000h
28020000h
28030000h
28040000h
28050000h
28060000h
28070000h
J5,3C
(1)
(1,4)
(1,5)
(1,9)
(1,4)
(1,4,11)
(1,7)
(1,4,11)
74HC138
VCC

RETURNED ON DEMAND.
VCC
C31
C27
U41B
14
13
A
B
0.1uF
15
Y0
Y1
Y2
Y3
12
11
10
9
TP
TP
TP
TP
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
22uF
0.1uF
R98
10K
C46
0.1uF
R97
10K
2
U41
C40
U21
C54
U26
C28
U39
U22
C48
C64
U11
R100
10K
U47
74HC139
VSS
1
18
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
3 OF 11
SHT __
__
AUGUST 24, 2001
757-039-11
REV A
PAGE 4 OF 11
U2
A25\
9
R56
2
10K
IA1
IA2
IA3
A4
A5
A6
51
50
49
48
47
46
A0
A1
A2
A3
A4
A5
4
52
3
45
6
5
38
RDN
WRN
CEN
IQRN
IACKN
DACKN
RESET
42
X1/CLK
VCC
R87
10K
INT0\
(1,2)
TP
RESET QUART
(1,9)
QUART CLK
(1,2)
E15
41
TP
INT3\
(1,2)
OPTIONAL
OUT CLK
RESET\
#2
VSS
VSS
RXDA
TXDA
IO0A
IO1A
IO2A
IO3A
19
20
27
26
25
24
RXDB
TXDB
IO0B
IO1B
IO2B
IO3B
8
7
23
22
21
16
RXDC
TXDC
IO0C
IO1C
IO2C
IO3C
36
37
29
30
31
32
RXDD
TXDD
IO0D
IO1D
IO2D
IO3D
44
43
33
34
35
39
VSS
VSS
RXDA2
TXDA2
J2,4A
SPEAKERA+
J2,3A
(1,11)
J5,21C
MM AUDIO1
28
40
TXDB2
TXDC2
TXDD2
RESET CPU/SEN/AUD
+25VDC
VCC
+13VDC
1
1N914
Q7
2N3904
1
R198
DATA
N/C
GND
GND
U87B
R199
6
5
3
4
R185
CR18
E11
TP
X2
1
14
VSS
VSS
8
7
23
22
21
16
R117
RXDC
TXDC
IO0C
IO1C
IO2C
IO3C
36
37
29
30
31
32
RXDD
TXDD
IO0D
IO1D
IO2D
IO3D
44
43
33
34
35
39
VSS
VSS
28
40
AI
BI
CI
DI
EI
FI
3
5
7
9
11
14
16
8
VOUT
VSS
MODE
VC
13
1
+13VDC
R118
1K
100K
1
2
3
4
4
3
RP24
100K
2.4K
ILD2
3
5
7
9
11
14
AO
BO
CO
DO
EO
FO
AI
BI
CI
DI
EI
FI
MODE
VC
VOUT
VSS
TxDa
RxDa
DTR
13
RP12
10
5
1
2
3
4
6
7
8
9
RXDA1
IO0A1
RXDB1
RXDC1
IO0C1
IO2C1
TP
2
4
6
10
12
15
AO
BO
CO
DO
EO
FO
16
8
VOUT
VSS
VCC
10K
VDD
U2
U76
U62
U78
U60
U78
U20
U79
C24
C26
C61
C76
C112
C105
C6
C101
C53
C70
0.1uF
C113
0.1uF
C124
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
22uF
470
74HC14
ILD2
1
A
VSS
R181
R55
1
10K
2
U18D
8
1K
TP
74HC14
AUGUST 24, 2001
(1,9)
(1,9)
Max. rate = 115.2kb/s
J1,4B
J1,3B
(1)
(1)
J1,4A
(1)
J1,5B
J1,5A
(1)
(1)
C103
RP19
TxDb
RxDb
RP20
J2,16A
J2,16B
(1)
(1)
MICROTOUCH / SPARE
10K
3
5
7
9
11
14
MODE
VC
13
1
RP21
8
7
6
5
2
1
100K
1
2
3
4
3
4
Max. rate = 9.6kb/s
RP18
100K
+13VDC
COMM TxDc
COMM RxDc
COMM CTS
COMM RTS
4504
MODE
J2,14A
(1)
J2,14B
J2,15B
J2,15A
(1)
(1)
(1)
RS232 DATA
COLLECTION
INPUT
LEVEL
OUTPUT
LEVEL
1 (VCC)
TTL
CMOS
0 (VSS)
CMOS
CMOS
A
0.1uF
2
Q5
R175
1
U18C
1
AI
BI
CI
DI
EI
FI
U30
U77
1N914
3
4
(1,8.9)
(1,8.9)
(1,8,9)
(1,8.9)
16
8
10K
2
3
VCC
U86B
(1,5)
RS485
4504
POWER SAVE
CR12
DCD
DIR
+13VDC
0.1uF
2N3904
U44
6
5
(1)
PAD
2
4
6
10
12
15
4504
2N3904
1
J2,13B
CHOPPED AC IN
(LOW VOLTAGE)
SCLK256
U80
VCC
J1,3A
+13VDC
U76
TXDA1
IO2A1
IO3A1
TXDB1
TXDC1
R208
220
(1)
(1)
JACKPOT RESET DETECT
RxDd
TxDd
150
+13VDC
J2,7A
ON BOARD F/O
COMMUNICATIONS
74HC125
R78
10K
Q4
(1)
(1)
74HC125
R211
J2,12A
J2,12B
JKPT RST
8
7
6
5
2
1
7
8
TELL TALE
2
1
DCS TxDh
DCS RxDh
DATA COLLECTION
SYSTEM (IGT)
E14
SNOUT
2
2
(1)
(1)
Max. rate = 4800b/s
RP22
SIN IN
11
VCC
U86A
J2,8A
J2,8B
PROGRESSIVE
COMMUNICATIONS
RP23
10K
RP25
8
7
6
5
1
2
VCC
R217
PROG TxDg
PROG RxDg
16
8
12
(1)
(1)
TT-CNTR1
TT-CNTR2
TT-DISABLE\
TT-DET\
13
1
5
VCC
J2,10B
J2,9A
SPARE F/O
U62D
R200
220
TxDf
RxDf
10K
AO
BO
CO
DO
EO
FO
(1)
SENET CYCLE DONE
U62B
2
J2,13A
+13VDC RESET\
TP
C126
0.1uF
2
4
6
10
12
15
(1)
TP
4504
VCC
41
RXDB
TXDB
IO0B
IO1B
IO2B
IO3B
SC26C94
4.7K
1
MODE
VC
VOUT
VSS
R170
1K
VCC
SNIN
VCC
Q8
1
X1/CLK
74HC125
ILD2
220
1N914
42
19
20
27
26
25
24
SILICON
SERIAL
NUMBER
TxDe
10
750
2N3904
1
3
2
4
#1
RXDA
TXDA
IO0A
IO1A
IO2A
IO3A
DS2401Z
2
U62C
NETPLEX TxD
TP
2.2K
NETPLEX RxD
RDN
WRN
CEN
IQRN
IACKN
DACKN
RESET
TP
220
J2,10A
4
52
3
45
6
5
38
RESET QUART
+13VDC
(1)
A0
A1
A2
A3
A4
A5
U61
R212
J2,11B
51
50
49
48
47
46
R197
220
(1)
IA1
IA2
IA3
A4
A5
A6
10K
IO2A1
D0
D1
D2
D3
D4
D5
D6
D7
CR17
2
1
R69
18
17
15
13
12
11
10
9
ILD2
I/O RESET\
U62A
74HC125
U87A
7
8
2
J2,11A
R225
10K
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
J2,9B
757 039 11
R226
220
R196
2.2K
(1)
VCC
2
PAGE 11
+13VDC
J2,1A,1B
IO0B2
RXDB2
RXDC2
RXDD2
IO2C2
IO0B1
(1,8,9)
(1,8,9)
(1,8,9)
(1,8,9)
(1,9)
(1,9)
DWG NO.
+25VDC
J1,18A,18B
R168
1K
U31
(1,5)
(1,5)
LIGHT PEN
SWITCH DETECT
SRESET\
2
4
6
10
12
15
4504
OUT CLK
MM AUDIO1
RESET\ CPU/SEN/AUD
TEST SWITCH
U77
3 AI
AO
5 BI
BO
7 CI
CO
9 DI
DO
11 EI
EO
14 FI
FO
U81
SPEAKER-
(1,6)
(1,8,9)
LPSW
10K
10K
VCC
SPEAKERA+
SPEAKER-
(1,2,5,9,11)
R84
RP15
IO WR
OUT CLK
(1,11)
OPTION
(1,3)
8
7
6
5
1
2
(1,11)
SOUND SEL
VCC
(1,5)
74HC175
PAD
(1,3,11)
IA1
(1,5)
OUT7
TO LEDs (DS5, DS6 & DS7)
CLK
CLR
S1
SOUND SEL\
10K
2
1
2
OUT SEL
E13
VCC
R11
1
(1,3,11)
OUT6
TP
MDOOR OPEN\
DDOOR OPEN\
BVAL OPEN\
CCAGE OPEN\
SRAM BAT LOW\
TT BAT LOW\
13
1
IA1
TP
TO LEDs (DS2 & DS3)
J9
VCC
OUT SEL\
SPARE
(1,5)
IO2B2
IO3B2
_11) Audio
PD[0..7]
PAD
OUT5
VERTOUT
INTERROGATE
SPARE I/O
VCC
9
1
TP
FWR EN\
SC26C94
RESET\ I/O
(1,9)
D4
R63
1K
X2
1
14
D3
13
E1
TP
8
7
6
5
(1,3)
12
PD7
2
3
7
6
10
11
15
14
1
2
3
4
QRT2 SEL\
D0
D1
D2
D3
D4
D5
D6
D7
U19C
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
1
2
3
4
4
3
QRT1 SEL\
(1,3)
18
17
15
13
12
11
10
9
PD6
74AC32
(1,2,3,5,7,11)
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
D2
IO WR\
VCC
U45
IO RD\
(1,2,3,5,7)
PD[0..7]
(1,2,5,7,11)
10
1
(1,2,3,5,6,7,10)
D
VCC
A[1..31]
D1
1
2
3
4
3
4
IA[1..3]
PD5
(1,2)
(1,2,7,11)
PD4

RETURNED ON DEMAND.
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
4 OF 11
SHT __
__
19
757-039-11
REV A
PAGE 5 OF 11
VCC
1
1
R17 1K
R7
1K
R6
1K
R24 10K
1
2
R8
1
10K
2
R5
1
10K
2
R23 10K
1
2
1
DON'T
STUFF
R16 1K
+13VDC
RESET\ CPU/SEN/AUD
R25 10K
1
2
10
5
(1,2,4,9,11)
RP16
SENET II
1
2
3
4
6
7
8
9
R174
10K
TP
R150
10K
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
1
19
1G
2G
VDD
VSS
20
10
R160
10K
SDATA TxB
8
7
6
5
SDATA ADR
SENCLK
SENSTB\
SENRST\
1
2
3
4
TP
RP17
TP
SDATA TxA
CR16
1N914
R193
150
13
1
2
12
R178
SDATA RxA
10K
J1,11B
(1)
J2,1A/1B
(1)
J1,2B
(1)
CR11
1N914
1
VCC
RP9
PD[0..7]
U68
SENET SEL\
+13VDC
SENRDY\
C109
0.1uF
0.1uF
C104
DWG NO.
IO WR\
IO RD\
R206
SDA
SCL
757 039 11
(1,2,3,4,7)
(1)
(1)
(1)
(1)
74C240
R149
10K
U18F
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
(1,3)
(1,2,3,4,7,11)
(1)
J1,12A
J1,10B
J1,10A
J1,13B
VCC
SENGRD - (J1-13A)
(1,2)
(1)
J1,12B
22
74HC14
(1,2,4,7,11)
J1,11A
4504
TP
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
TP
2
4
6
8
11
13
15
17
TP
16
8
1
MODE
VC
VOUT
VSS
13
1
2
4
6
10
12
15
AO
BO
CO
DO
EO
FO
E9
AI
BI
CI
DI
EI
FI
20
2
20
2
TP
22uF
3
5
7
9
11
14
VCC
R169
1
R192
1
U74
+ C25
.01uF
CH1SDO
CH2SDO
MASDO
SCLK
STB
IO_EN
C12
SENETEEG
68PLCC
U78
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CH1SDO
CH1SDI
CH2SDO
(ntr) MASDO
(rd6) SCLKO
(rd4) STB
(rd5) IO_EN
SDA
SCL
GND
GND
(rd3) NC
(rd2) NC
VCC
VCC
(rd1) NC
(rd0) NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VCC
GND (scanen)
GND (scantn)
NC (scanout)
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
GND
(oenramhi) GND
VCC
VCC
SENRDY
SENSEL
IO-WR
IO-RD
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
TP
TP
A[1..31]
(1,2,3,4,6,7,10)
4.7K
GND
GND
GND (wrtramhi)
GND (selramhi)
VCC
SCLK256 (rd7)
SCLK17
SYSCLK
RESET
VCC
SEL3
SEL2
SEL1
SEL0
CABSTBIN
CABSTBOUT
CABSDI
U10
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
SCLK256
(1,4)
TP
SYS CLK
(1,2)
100
I^2C
R205
J1,2A
(1)
100
VCC
B
U5A
U5B
3
VCC
U5C
1
OUT5
OUT6
1K
VCC
DS5
10
U83
Yellow
74HC14
(1,4)
11
OUT5
IO3B2
IO2B2
DSx
DSx
DSx
DSx
0.1uF
U3
U6
C125
0.1uF
C9
0.1uF
C117
0.1uF
OUT6
DSx
C21
R54
10K
2
OUT7
DSx
0.1uF
2
FAIL
C58
+13VDC
U5E
(FIRMWARE DEFINEABLE)
LED configiration (FRONT PANEL VIEW)
U18E
11
10
TP
74HC14
PCB side
20
OPTIONAL
4
Yellow
74HC14
OUT6
8
1
2
DS3
12
13
SCL
VCC
SDA
NC
MODE/WC NC
WCR
VSS
M34R32
10
5
2
Yellow
U5F
OUT5
1
2
3
4
6
7
8
9
DS2
6
(FIRMWARE DEFINEABLE by QUART)
RP2
IO3B2
74HC14
(1,4)
2
Yellow
74HC14
(1,4)
U85
6
5
7
3
DS1
(1,4)
(FIRMWARE DEFINEABLE by QUART)
R179
10K
OUT7
Yellow
74HC14
IO2B2
R177
10K
10K
2
DS4
OUT7
CPU FALURE
R194
U5D
(1,4)
2
Red
74HC14
FAILURE (FAILURE DETECTED)
(1,2,5)
DS6

RETURNED ON DEMAND.
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
5 OF 11
SHT __
__
AUGUST 24, 2001
757-039-11
REV A
PAGE 6 OF 11
U18B
R218
DOT CLK2
(1)
1
1
74HC14
BITBLITZ CLK
(1,2)
R221
2
0 OHM
10K
R4
VCC
10K
2
OPTIONAL
C3
14
VCC
2
TP
DIN
CCLK
CE
RESET/OE
4
3
DONE
1
2
R15
STUFF IF PLL NOT USED
26.667MHz
DATA
CLK
VPP
CEO
XC1765D
EN
GND
10K
7
6
0 OHM
7
U17
VCC
OUT
Y1
0.1uF
R48
DOT CLK
SC-1
(1,7)
(1,7)
SC-2
E8
D[0..15]
(1,2,3,7,10)
DD[0..7]
(1,7)
VCC
R49
VCC
VCC
U8
(1)
(1,2,3,10)
(1,2,3,10)
(1,2,3,7,10)
(1,7,9)
LPSTB\
WR0\
WR1\
RESET
ADRSTB
BITCLK
BLTSEL
OSC
LPSTB
DSF-2
WR0 DIN/256COLOR
WR1
CCLK
DONE
RD
RD\
RESET\ VIDEO
E3
R14
37
72
74
55
SE
40
NC
41
DSF
38
QSF
256X16 VDRAM
60nS
R29
10K
TP
RAS
37
36
35
34
31
30
29
28
27
A0
A1
A2
A3
A4
A5
A6
A7
A8
63
SE
40
NC
41
DSF
38
QSF
R1
10K
E6
1
8
18
32
47
57
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
4
6
9
11
14
16
19
21
44
46
49
51
54
56
59
61
SC-1 34
38
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
FD[0..15]
E5
U48
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
11
1
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
CLK
OC
BD[0..15]
2
3
4
5
6
7
8
9
R67
11
1
10K
CLK
OC
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
note:
BD12, BD13, BD14 and BD15
are NOT USED or connected
74HC574
BD12
BD13
BD14
BD15
R127
1K
V SYNC
1
TP
BLANK1
FLATCH1
1
1N914
TP
(1,7)
(1,7)
FLATCH2
R108
1K
(1,7)
BA0
(1,7)
BA1
(1,7)
CR6
1N914
TP
U59A
CR4
TP
1
3
74HC32
(1,4)
(1,7)
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
VCC
1N914
CR5
10
U59C
1N914
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
74HC574
9
8
(1)
2
3
4
5
6
7
8
9
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
BLTRDY\
CR7
(1,7)
U27
JUMPER
74HC32
256X16 VDRAM
60nS
FOR ENGINEERING TESTING
H SYNC
R37 R41
10K 10K
R53
4.7K
E7
(1)
R33
10K
(1,2,7)
R102 10K
R32
10K
ISP[1..6]
220
ISP4
ISP2
ISP3
ISP5
(1,7)
(1,7)
R27
10K
VCC
(1,2)
15
16
17
30
XC9536, DD CONTROLLER
R42
TDI
TMS
TCK
TDO
C256
2
1
35
29
33
36
37
SC1
0 OHM
NORMALLY NOT STUFFED
NC
NC
NC
NC
NC
BLOCK
CA0
63
CAS
26
28
39
VS0
VS1
VS2
VS3
VS4
VS5
VS6
VS7
VS8
VS9
VS10
VS11
VS12
VS13
VS14
VS15
39
BLOCK
CA0
4
6
9
11
14
16
19
21
44
46
49
51
54
56
59
61
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
DT/OE
WBL/WEL
WBU/WEU
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
5
7
10
12
15
17
20
22
43
45
48
50
53
55
58
60
37
36
35
34
31
30
29
28
27
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
RAS
24
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SC
CAS
26
18
19
20
22
24
25
26
27
39
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TP
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
WBL/WEL
WBU/WEU
64
VS[0..15]
9
30
29
47
58
56
36
38
57
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
SI/O
DT/OE
SC-3
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BITBLITZ SEL\
BLTRDY
FLATCH1
FLATCH2
BA0
BA1
BLOCKRW
DOTCLK
HORZ
VERT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3
13
23
33
42
52
62
(1,2)
BLT CLK
12
31
32
5
7
10
12
15
17
20
22
43
45
48
50
53
55
58
60
DCLK
VS0
VS1
VS2
VS3
VS4
VS5
VS6
VS7
VS8
VS9
VS10
VS11
VS12
VS13
VS14
VS15
43
1
(1,2)
54
10
13
11
75
79
5
4
83
PWRDN
M0
M1
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
A20
A21
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
24
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SC
5
6
7
8
9
11
12
13
14
40
42
43
44
1
2
3
4
62
63
59
60
65
67
68
69
70
33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BBSTB
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
BLANK
64
VS0
VS1
VS2
VS3
VS4
VS5
VS6
VS7
VS8
VS9
VS10
VS11
VS12
VS13
VS14
VS15
757 039 11
+13VDC LOW\
0 OHM
(1,2)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
BLANK2
A20
A21
SC-1
SC-2
SC-3
U1
DWG NO.
(1,8,9)
R47
24
21
27
61
66
16
71
14
73
25
23
28
26
20
19
18
17
15
39
34
35
8
7
6
82
81
3
2
84
80
78
76
77
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
SC-1
SC-2
SC-3
OE-1
OE-2
WE-1
WE-2
WE-3
DSF-1
CAS-1
CAS-2
RAS
VA[0..8]
FIDUCIAL
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
FOR PCB USE ONLY
44
46
41
45
40
42
48
49
50
51
52
53
GND
GND
FID4 FID5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
XC3142, BitBlitz
VCC
VCC
U9
U11
3
13
23
33
42
52
62
22
64
84 pin PLCC Socket (SMT)
1
8
18
32
47
57
BB DOT CLK
10K
1
REF U9
(1,2,3,4,5,7,10)
R219
20
1
A[1..31]
BLOCKRW\
VERTOUT
(1,7)
BLANK2
(1,7)
VCC
U13
U12
U7
U14
U28

RETURNED ON DEMAND.
U50
+ C2
0.1uF
2
0.1uF
C36
22uF
2
C56
0.1uF
2
0.1uF
C35
C13
0.1uF
2
0.1uF
C1
C14
0.1uF
2
0.1uF
C74
C23
U55
VSS
DRAW N
TDW
4
AUGUST 24, 2001
DATE
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
01NOV99
DATE
SCALE
NONE
6 OF 11
SHT __
__
21
757-039-11
PD[0..7]
(1,2,4,5,11)
COLOR SEL\
(1,3)
FLATCH1
SC-1
BLANK1
FW R0B\
(1,6)
(1,6)
(1,6)
(1,3,10)
IA[1..3]
VBLK1 SEL\
13
BLOCKRW\
12
74HC32
FLATCH2
11
1
DIR
G
11
1
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
PL CA4
PL CA3
PL CA2
PL CA1
PL CA0
10K FLATCH2
1K
(1,2,6)
(1,3)
(1,3,10)
(1,6)
9
1
CA0
CA1
CA2
CA3
CA4
TP
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
BA19
VPP(A19)
R115
10K
CLK
CLR
22
24
FWR1B\
256C GND
FLATCH1
RESET\
BK8
BK9
BK10
BK11
BK12
BK13
BK14
BK15
BL9
BK15
BK14
BK13
BK12
BK11
BK10
BK9
BK8
BL10
BL11
SC0
E10
COLOR SEL\
IO RD\
VDAC W\
IO WR\
256COLOR\
24
25
26
27
11
39
33
34
35
36
37
38
29
SC-1
15
16
17
30
ISP5
ISP2
ISP3
ISP6
IA1
IA2
FLATCH2
FLATCH1
BLOCKRW\
R46
ISP3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
26
27
25
15
RS0
RS1
W
R
REF U73
1
2
3
R173
10K
IREF
PCLK
13
BLANK
16
10pF
50V
DOT CLK
R176
(1,6)
2 BLANK2
(1,6)
0 OHM
VDAC (DIP)
E20
28 pin DIP Socket

VCC
R95
10K
REF U53
C127
1.0uF
C108
0.1uF
32 pin DIP Socket
Q3
LM334
-
U57
BK8
BK9
BK10
BK11
BK12
BK13
BK14
BK15
2
3
4
5
6
7
8
9
FLATCH2 11
1
U58
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
CLK
OC
2
ENBLK2
SCO
74HC574
R123
2
5
11
14
3
6
10
13
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
1A
2A
3A
4A
1B
2B
3B
4B
15
1
1Y
PX0
2Y
PX1
3Y
PX2
4Y
12
PX3
R148
15
1%
CR3
1N914
R147
150
74HC257
G
A/B
10K
R190
0 OHM
3 Amps
0 OHM
3 Amps
R186
B
PX[0..7]
(1)
ISP[1..6]
VBLK0 SEL\
FW R1B\
BLOCK
10
TP
U44C
C73
C71
C72
22uF
0.1uF
VSS
3
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
TP
74HC08
U44D
C44
C33
C45
C52
C123
C57
C43
C55
C30
C29
C42
C50
C32
+ C51
11
12
74HC08
TP
74HC08
17
18
19
20
21
22
23
24
RED
GREEN
BLUE
C114
CA[0..4]
13
P0
P1
P2
P3
P4
P5
P6
P7
U44B
22
5
6
7
8
9
10
11
12
FERRITE BEAD
U73
10K
VCC
R91
10K
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
XC9536, PIXEL CONTROLLER
BL12
BL14
BL15
10uF
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
GND
0.1uF
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
44
L1
+ C81
RESET\ VIDEO
R103
10K
C82
RD\
ENBLK1 COLORSEL
IO_RD
B256
VDAC_WR
DD0
IO_WR
DD1
DD2
C256
DD3
PX0
DD4
PX1
DD5
PX2
PX3
DD6
DD7
PX4
F1
PX5
BLANK1
PX6
BLOCK
PX7
CA1
CA2
CA3
SC1
CA4
TDI
ENBLK2
TMS
VDAC_RD
TCK
TDO
SCO
ENBLK1 5
256 EN\ 40
DD0 2
DD1 42
DD2 4
DD3 7
DD4 18
DD5 19
DD6 20
DD7 28
FLATCH1 13
BLANK1 43
BLOCK
3
CA1 8
CA2 9
CA3 14
CA4 1
ENBLK2 12
VDAC R\ 22
FLATCH2
5
4
VCC
U24
A1
A2
A3
BL4
BL5
BL6
BL7
BL8
BK7
BK6
BK5
BK4
BK3
BK2
BK1
BK0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
R114 512KX8 EPROM

10K
100nS
74AC174
72 Pin SIMM
CE
OE
CA0
VBLK1 SEL\
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
74HC257
VIDEO VCC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
R76
2
2
5
7
10
12
15
Q1
Q2
Q3
Q4
Q5
Q6
D1
D2
D3
D4
D5
D6
3
4
6
11
13
14
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
U35
BL13
PX7
VDAC (PLCC)
19
18
17
16
15
14
13
12
74HC574
(1,6)
BLOCK LOOKUP
12
4Y
J3
BA1
BA0
GND
VBLK0 SEL\
U53
CLK
OC
10K
512KX8 EPROM
100nS
PX6
R68
CE
OE
FD[0..15]
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
32 pin DIP Socket
3Y
40
OPTIONAL
IF PLCC PART NOT AVAILABLE
BL0
BL1
BL2
BL3
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
REF U30
2Y
PX5
VCC
FWR0B\
1
R73
10K
R77
10K
74HC574
2
3
4
5
6
7
8
9
FLATCH2
G
A/B
PX4
VPP(A19)
U28
(1,6)
15
1
10K
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
(1,6,9)
256 EN\
SC1
1Y
PCLK
BLKRW\+VBLK1
BA19
22
24
CLK
OC
R75
1A
2A
3A
4A
1B
2B
3B
4B
BLANK
R90
11
1
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BK0
BK1
BK2
BK3
BK4
BK5
BK6
BK7
19
18
17
16
15
14
13
12
FLATCH2
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
2
3
4
5
6
7
8
9
BD8
BD9
BD10
BD11
FD0
FD1
FD2
FD3
2
5
11
14
3
6
10
13
0.1uF
TP
757 039 11
74HC574
U43
VCC
BL4
BL5
BL6
BL7
BL12
BL13
BL14
BL15
30
C120
2
R105 10K
RS0
RS1
WR
RD
OPA
CLK
OC
17
18
16
6
31
11
1
IA1
IA2
VREF
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
D0
D1
D2
D3
D4
D5
D6
D7
DWG NO.
FLATCH2
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
G
A/B
8
9
10
11
12
13
14
15
2
3
4
5
6
7
8
9
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
74HC257
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
28
29
U47
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
PX3
IREF
COMP
J1,24B
J1,25B
J1,24A
BD[0..15]
(1,6)
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
PX2
12
U49
BA[2..24]
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
4Y
10K
U30
BA0
BA1
3Y
BK[0..15]
(1,6)
(1,6)
PX1
RED
GREEN
BLUE
BK8
BK9
BK10
BK11
BK12
BK13
BK14
BK15
74HC245
A[1..31]
(1,2,3,4,5,6,10)
11
12
13
14
15
16
17
18
B8
B7
B6
B5
B4
B3
B2
B1
RED
GREEN
BLUE
28
A8
A7
A6
A5
A4
A3
A2
A1
2Y
VCC
9
8
7
6
5
4
3
2
D8
D9
D10
D11
D12
D13
D14
D15
R74
ENBLK1 15
SC0
1
1Y
PX0
1
25
26
27
VSS
VBLK0 SEL\
1
19
74HC574
1A
2A
3A
4A
1B
2B
3B
4B
N/C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RD\
CLK
OC
2
5
11
14
3
6
10
13
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
14
74HC245
U23
U34
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
P0
P1
P2
P3
P4
P5
P6
P7
2
3
5
19
23
24
41
42
43
44
U44A
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
D2
D3
D4
D5
D6
D7
D8
32
33
34
35
36
37
38
39
74HC08
U59B
2
3
4
5
6
7
8
9
BK0
BK1
BK2
BK3
BK4
BK5
BK6
BK7
BK0
BK1
BK2
BK3
BK4
BK5
BK6
BK7
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
6
74HC32
U33
11
12
13
14
15
16
17
18
B8
B7
B6
B5
B4
B3
B2
B1
A8
A7
A6
A5
A4
A3
A2
A1
BL[0..15]
9
8
7
6
5
4
3
2
D0
D1
D2
D3
D4
D5
D6
D7
1
5
DIR
G
VCC
VCC
VCC
VCC
U82
U22
1
19
(1,2,3,6,10)
4
20
21
22
0.1uF
D[0..15]
(1,2,3,6,10)
C119
U59D
DD[0..7]
(1,6)
11
(1,6)
(1,3)
(1,2,4,11)
(1,6)
PAGE 7 OF 11
IO WR\
IO RD\
(1,2,3,4,5,11)
(1,2,3,4,5)
REV A

RETURNED ON DEMAND.
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
7 OF 11
SHT __
__
AUGUST 24, 2001
757-039-11
REV A
PAGE 8 OF 11
VDD
(1,9)
1
R204
470K
2
R213
470K
2
R210
470K
R203
470K
CARDCAGE DET\
R209
U66A
2
100K
4071
3
CCAGE OPEN\
CC-OPEN
1
3
4081
DDOOR OPEN\
U75A
MD-OPEN
MDOOR OPEN\
5
4
(1,9)
DROPDOOR DET\
4071
(1,9)
BILLVAL DET\
4071
D0
D1
12
D2
13
D3
9
1
R152
10
1K
R214
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
2
3
7
6
10
11
15
14
1
CLK
CLR
R125
2
4
6
10
12
14
I1
I2
I3
I4
I5
I6
1
15
DA
DB
1K
4081
DDA
DDB
CLK
ODA
ODB
RST
CC-OPEN
U67A
8
7
6
5
Q0
Q1
Q2
Q3
3
4
5
6
4076
12
4081
13
A
B
E
Q0
Q1
Q2
Q3
4
5
6
7
R154
STUFF R154 FOR CARD CAGE ALARM (DEFAULT)
STUFF R153 FOR MAIN DOOR ALARM
0 OHM
TP
MD-OPEN
4556
U75D
U66D
RP14
R153
0 OHM
12
R107
470K
4071
U67B
11
13
TT-CNTR1
A
B
15
1K
Q0
Q1
Q2
Q3
12
11
10
9
TP
TP
TP
757 039 11
R133
14
13
DWG NO.
1
2
3
4
470K
4556
TT-CNTR2
VDD
TT-DISABLE\
INTERROGATE
R183
10K
U83A
+13VDC LOW\
1
3
4001
(1,6,9)
9
10
7
1
2
15
U75C
11
(1,4,9)
D0
D1
D2
D3
VDD
(1,4,9)
14
13
12
11
8
10
2
2
3
(1,4,9)
3
5
7
9
11
13
4503
100K
(1,4,9)
(1,4,9)
U70
O1
O2
O3
O4
O5
O6
40175
100K
(1,9)
U65
U71
U66C
R201
(1,4,9)
VDD
8
1
(1,4,9)
100K
MAINDOOR DET\
BVAL OPEN\
U75B
U66B
5
R202
4081
(1,4,9)
R184
TT-DET\
(1,4,9)
100K
DOORVAL OUT
U83B
VDD
5
6
U61
U50
C100
8
2
390K
R157
R158
10K
10K
C102
6
7
R182
Q6
MOSFET N
200K
2
O1
O2
DO
13
U83D
8_BY
CINH
12
2
R171
13
11
4001
1K
MONO
OINH
IN1
U68
4536
R145
1K
1
R156
1K
1
R136
1K
1
R159
1K
1
R161
1K
1
2
1000pF
C92
15
14
3
1
R142
47K
A
B
C
D
9
10
11
12
VSS
10
R155
1000pF
U37
4001
100
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
2
0.1uF
C99
C98
C116
C78
C91
10uF
0.1uF
R137
1
+ C62
C87
C86
U83C
U35
U25
U60
U92
(1,9)
TT-BACKUP
U41
(9)
U36
4001

RETURNED ON DEMAND.
DRAW N
TDW
4
AUGUST 24, 2001
DATE
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
C
APPROVED
01NOV99
REV LTR
757 039 11
DATE
SCALE
NONE
8 OF 11
SHT __
__
23
757-039-11
REV A
PAGE 9 OF 11
REF U84B1
HEAT SINK
VDD
VCC
E21
FOR EXTERNAL
POWER SUPPLY
1
2
HEATSINK COUMPOUND
REF U84A
VCC
CLIP
U64A
R172
0 OHM
3 Amps
HEAT SINK
U84
40106
.01uF
100uH
+ C107
TP
D3
.01uF
1N6373
R21
51
HFBR-2522
.25W
1N6373
FO2
1N5823
C11
.01uF
C122
D4
1000uF
25V
R215
C10
1000pF
2
0 OHM
3 Amps
+
D
1
1
LM2576T-5.0
3
OFF
C118
40106
FO1
3
VCC OUT1
OUT
100uF
25V
L2
1
+ C93
VCC OUT2
FDB
+VIN
+13VDC
J2,1A/1B
GND
(1)
D
R12
3.3K
U64B
REF U84B2
REMOVE E27 WHEN USING AN

EXTERNAL POWER SUPPLY
REF U84B3
U6
RxDd
TxDd
3
1
2
4
CR2
R143
TP
VCC
Q2
2N3904
10K
R35
10K
430
Schottky
U69
TP
TP
TP
R52
100K
1%
R44
22M
TP
2
TP
BT2
R163
OUT1
V+
HYS1
OUT2
SET1
SET2
VCC
1
(1,4)
GND
HYS2
OPTIONAL COMPONENTS TO BE USED ONLY

WHEN BT1 IS NOT INSTALLED.
R45
R39
1M
1%
R36
R34
100K
1%
1K
0.1uF
R38
1M
1%
R22
100
2
C
1N5818
BT1
C18
R13
10K
3.0V
Lithium
ICL7665
3.6V
NiCad
VCC
CR1
1
R40
10K
22M
R43
1M
1%
1
R146
2
51K
TP
TP
TP
VCC
U12
OPTIONAL
16
15
14
13
12
11
10
9
CHG
VDD
DCHG
N/C
PFN
VIN
MMN OPRF
CMN AUX1
SEL0 AUX0
SEL1
RC
VSS
MRN
R111
TP
1
2
3
4
5
6
8
7
R121
1M
1%
VCC
SRAM BAT LOW\
D2
1
R126
Q1
2N3904
680K
VCC
2
1
R110
Schottky
21
(1,4)
D1
R120
TT BAT LOW\
VCC
510
VCC
39
2
TP
75453
R112
R122
TP
1N914
39
LM317
OPTIONAL
6
7
8
7
6
5
VIN
NC
VOUT VOUT
VOUT VOUT
ADJ
NC
1
2
3
4
OPTIONAL
HFBR-1522
U72
+13VDC
(1,4)
(1,4)
C106 15K
ICS1722N
330K
1
100pF
VBATT
(1,3)
5
R141
R138
10K
330K
+13VDC
(1,4)
40106
U56A
2
1
RESET MEZZ
757 039 11
RESET QUART
DWG NO.
U64C
VCC
(1)
U63
TT-BACKUP
13
CE OUT
12
LOW LN
PFI
11
RESET
15
RESET
16
WDO
14
PFO
10
WDI
47pF
OSC IN
OSC SL
GND
C88
VOUT
U64D
9
R134
1K
INT2
12
(1,2)
40106
U56B
3
RESET\ SIMM
4
40106
RESET\ I/O
(1,4)
40106
U56D
TT-DET
(3,10)
U56C
5
INTERROGATE
(1,2,4,5,11)
U56F
13
TT-DISABLE
INTERROGATE
RESET\ CPU/SEN/AUD
10
40106
TP
TT-BACKUP
(1,4,8)
11
40106
2
TT-DISABLE\
(1,3)
U64E
8
8) TellTale
(1,4,8)
(1,3,10)
CE\OUT
Supervisory (691)
R109
1K
(1,2)
TP
R139
6.04K
1%
0 OHM
R119
VOUT
CE IN
WCHDOG SEL\
BATT/N
VBATT
R140
47K
9
(1,3)
RESET CPLD/F/O
VCC
(1,8)
40106
VCC
RESET\ VIDEO
(1,6,7)
40106
TT-CNTR1
(1,8)
(1,8)
DROPDOOR DET\
DROPDOOR DET
PA RESET\
TT-CNTR2
+13VDC LOW
MAINDOOR DET\
MAINDOOR DET
BILLVAL DET
(1,8)
(1,8)
DOORVAL OUT
CARDCAGE DET
(1,4,8)
(1,4,8)
TT-CNTR2
(1,4,8)
A
VCC
C80
0.1uF
U56E
C79
11
TP
0.1uF
0.1uF
C22
0.1uF
C77
C68
0.1uF

RETURNED ON DEMAND.
U69
U22
10
TP
40106
R116
10K
VSS
24
(1,4,8)
TT-DET\
TT-CNTR1
PAGE 8
A
(1,4,8)
CCAGE OPEN\
CCAGE OPEN
CARDCAGE DET\
(1,4,8)
DDOOR OPEN\
DDOOR OPEN
DOORVAL OUT
(1,4,8)
MDOOR OPEN\
MDOOR OPEN
BILLVAL DET\
(1,6,8)
BVAL OPEN\
BVAL OPEN
(1,8)
(1)
+13VDC LOW\
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
9 OF 11
SHT __
__
AUGUST 24, 2001
757-039-11
A[1..31]
WE0\
WE1\
CE\
OE\
A18
GAME
A19
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
A20
VPP(A19)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
22
24
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A19
REF U13
32 pin DIP Socket
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
1
CE
OE
A19
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
A20
VPP(A19)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
22
24
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A19
REF U36
32 pin DIP Socket
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
1
(3)
(1,2,3,6)
(1,2,3,6)
(2)
(3)
C16
0.1uF
A19
WE
CE1/CS
OE
VPP(A19)
D0
A0
D1
A1
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
A8
A9
A10
A11
A12
VCC
A13
A14
CE2/A17
A15
A16
NC/A18
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
D8
D9
D10
D11
D12
D13
D14
D15
REF U14
32 pin DIP Socket
CE
OE
1MX8 EPROM
U37
13
14
15
17
18
19
20
21
D8
D9
D10
D11
D12
D13
D14
D15
32
VOUT
30
A18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
REF U38
32 pin DIP Socket
C39
0.1uF
A19
WE
CE1/CS
OE
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
VPP(A19)
22
24
D0
D1
D2
D3
D4
D5
D6
D7
REF U37
32 pin DIP Socket
CE
OE
512KX8 SRAM
1MX8 EPROM
FW R1A\
FWR1A\
SRAM WE1\
FWR1B\
RESET\ SIMM
VCC
J6
FWR0A\
SRAM WE0\
FWR0B\
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
XM1 SEL\
4
XM2 SEL\
6
GAME SEL\
8
SRAM CE\
10
VBIT SEL\
12
WR0\
14
WR1\
16
XM3
SEL\
18
D7
20
D6
22
D5
24
D4
26
D3
28
D2
30
D1
32
D0
34
RD\
36
SRAM OE\
38
D15
40
D14
42
D13
44
D12
46
D11
48
D10
50
D9
52
D8
54
XM4 SEL\
56
SIMMRDY\
58
GND
60
A31
62
VOUT
64
A30
66
A29
68
A28
70
XMB SEL\
72
72 Pin SIMM
FWR0A\
SRAM WE0\
FWR0B\
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
GND
FWR1A\
FWR1B\
A26
A27
RESET\
SRAM WE1\
FW R0A\
VCC
J7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
XM1 SEL\
4
XM2 SEL\
6
GAME SEL\
8
SRAM CE\
10
VBIT SEL\
12
WR0\
14
WR1\
16
XM3
SEL\
18
D7
20
D6
22
D5
24
D4
26
D3
28
D2
30
D1
32
D0
34
RD\
36
SRAM
OE\
38
D15
40
D14
42
D13
44
D12
46
D11
48
D10
50
D9
52
D8
54
XM4 SEL\
56
SIMMRDY\
58
GND
60
A31
62
VOUT
64
A30
66
A29
68
A28
70
XMB SEL\
72
72 Pin SIMM
J8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
FWR0A\
SRAM WE0\
FWR0B\
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
GND
FWR1A\
SRAM WE1\
FWR1B\
A26
A27
RESET\
2
XM1 SEL\
4
XM2 SEL\
6
GAME SEL\
8
SRAM CE\
10
VBIT SEL\
12
WR0\
14
WR1\
16
XM3
SEL\
18
D7
20
D6
22
D5
24
D4
26
D3
28
D2
30
D1
32
D0
34
RD\
36
SRAM OE\
38
D15
40
D14
42
D13
44
D12
46
D11
48
D10
50
D9
52
D8
54
XM4 SEL\
56
SIMMRDY\
58
GND
60
A31
62
VOUT
64
A30
66
A29
68
A28
70
XMB SEL\
72
72 Pin SIMM
FW R0B\
FW R1B\
XMB SEL\
WR0\
WR1\
SIMMRDY\
XM4 SEL\

RETURNED ON DEMAND.
C38
0.1uF
C15
0.1uF
0.1uF
2
0.1uF
C17
C37
VCC
AUGUST 24, 2001
1
22
24
D0
D1
D2
D3
D4
D5
D6
D7
757 039 11
(1,3,7)
(1,3,7)
A18
32 pin DIP Socket
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16(1M)
A17(2M)
PRG(A18)
XM1 SEL\
XM2 SEL\
XM3 SEL\
A26
A27
(3,9)
VOUT
30
REF U15
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
VBIT SEL\
(1,3)
32
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A20
29
22
24
CE
OE
VCC
(1,3)
D0
D1
D2
D3
D4
D5
D6
D7
DWG NO.
(3)
(3)
(3)
13
14
15
17
18
19
20
21
512KX8 SRAM
U38
1MX8 EPROM
(1,3)
D0
A0
D1
A1
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
A8
A9
A10
A11
A12
VCC
A13
A14
CE2/A17
A15
A16
NC/A18
U14
A20
29
22
24
1MX8 EPROM
U36
GAME SEL\
BIT
SRAM
U15
SRAM
SRAM
VOUT
SRAM
SRAM
RD\
U13
(1,3)
(3)
(3)
(1,3,9)
(3)
(3)
(1,2,3,6,7)
(1,2,3,4,5,6,7)
D[0..15]
(1,2,3,6,7)
REV A PAGE 10 OF 11
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
SHT10
__ OF 11
__
25
757-039-11
U51
PD2
12
74AC32
U19B
D3
PD3
13
RESET\
9
1
D4
CLK
CLR
2
3
7
6
10
11
15
14
TP
E23
TP
E24
TP
E25
TP
E16
PAD
PAD
PAD
74HC175
R222
10K
2
R106
10K
(1,2,4,7)
PAD
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
R223
10K
R224
10K
D2
D1
28070000h
OUT SEL\
PD0
PD1
OUT CLK
(4)
(1,3,4)
REV A PAGE 11 OF 11
IA1
J4,27C
PD[0..7]
(1,2,4,5,7)
IO WR\
(1,2,3,4,5,7)
RESET\ CPU/SEN/AUD
(1,2,4,5,9)
SOUND SEL\
(1,3,4)
Audio Pre-Amp Power
VO
C65
2
0.1uF
0.1uF
AUDIO
LM340LAZ-5.0
+ C69
+ C59
4.7uF
U55
4.7uF
R130
C84
12
1
15
14
13
12
11
1
2.2uF
10V
R132
2.2K
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
IA1
YM2413
C83
12
YM2413 XOUT
C94
2
2.2uF
10V
2.2K
R144
15pF
2
22K
1
+ C97
100uF
25V
15pF
AUDIO
C96
1
R167
22K
10uF
35V
0.1uF
R166
AUDIO
C66
22K
1
C115
R151
C67
757 039 11
+25VDC
3.579 MHz
R131
2.2K
10K
DWG NO.
2.2uF
10V
Y4
R129
J5,21C
J1,18A/18B
16
17
18
2
3
4
5
6
7
10
E18
MM AUDIO1
(1)
VCC
D0
D1
D2
D3
D4
D5
D6
XIN
D7
A0
XOUT
AUDIO
(1,4)
GND
RO
MO
IC
CS
WE
YM2413 XIN
AUDIO
R207
0 OHM
3 Amps
2.2K
R216
0 OHM
3 Amps
C85
VI
GND
J2,1A\1B
(1)
U50
+13VDC
C89
2
.001uF
1
AUDIO
C121
LM1875
1
R135
10K
AUDIO
1000uF
25V
U79
U54B
AUDIO
1.0uF
REF U79A2
LM358
3
+ C90
AUDIO
R128
10K
2.2uF
10V
2
150K
CLIP
R162
1 OHM
R165
10K
AUDIO
HEAT SINK
HEATSINK COUMPOUND
REF U79A3
REF U79A1
R164
R124
10K
U54A
LM358
AUDIO
C95
E19
J2,4A
SPEAKERA+
(1,4)
C110
+ C111
10uF
0.22uF
R180
(1,4)
J2,3A
SPEAKER-
2
0 OHM
AUDIO
VCC
A

RETURNED ON DEMAND.
C75
C60
0.1uF
0.1uF
26
DRAW N
DATE
TDW
01NOV99
CHECKED
DATE

TITLE

DW G. SIZE
DW G. NO.
REV LTR
757 039 11
APPROVED
DATE
SCALE
NONE
SHT11
__ OF 11
__
AUGUST 24, 2001

PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC - Game King IGT

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PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC - Game King IGT

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USED MAIN 5 VOLTS FOR U62 PULLUPS

7) Video BLOCK & VDAC

NOTES: (UNLESS OTHERWISE INDICATED)

FID1 FID2 FID3

3. JUMPER OPTIONS SHOWN ONPAGE2

6) BitBlitz & VDRAM

RESERVED FOR MULTIMEDIA

(VCC GND PLANE)

SRAM BAT LOW

SRAM BAT LOW\

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

INTERNATIONAL GAME TECHNOLOGY

SCHEMATIC, GAME KING 2

AUGUST 24, 2001