LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity ANN_Controller is
-------------------------------------------------------------------------------------------------------------port (m_clk,int:in STD_LOGIC:='1';
reset:in STD_LOGIC:='0';
cs,rd,wr :out std_logic:='1';
setpoint_sel:in std_logic_vector(1 downto 0):="00";
setpoint_out:out std_logic_vector(7 downto 0):="00000000";
adc_data: in std_logic_vector(7 downto 0):="00000001";
pwm:out std_logic:='0');
end ANN_Controller ;
--------------------------------------------------------------------------------------------------------------architecture Behavioral of ANN_Controller is
--------------------------------------------------------------------------------------------------------------type statetype is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10);
signal state,nextstate: statetype;
signal setpoint,adc_data_temp,error:std_logic_vector(7 downto 0):="00000000";
signal clk_sig,clk_sig1,clk_sig0:std_logic:='0';
signal error_with_signbit:std_logic_vector(8 downto 0):="000000000";
signal w21,w31,w41,w51,w61,w72,w73,w74,w75,w76:std_logic_vector(7 downto
0):="00000000";
signal b2,b3,b4,b5,b6,b7:std_logic_vector(7 downto 0):="00000000";
signal neu2_input,neu3_input,neu4_input,neu5_input,neu6_input:std_logic_vector(15
downto 0):="0000000000000000";
signal sta,nsta:integer range 0 to 4:=0;
--------------------------------------------------------------------------------------------------------------begin
--------------------------------------------------------------------------------------------------------------w21<="00001000";w31<="00001000";w41<="00001001";w51<="00111000";w61<="00
011000";
w72<="00001001";w73<="01001000";w74<="00001001";w75<="01001000";w76<="0
1001000";
b2<=
"00000011";b3<="00000011";b4<="00010001";b5<="00010001";b6<="00010011";b7<=
"00010011";

---------------------------------------------------------------------------------------------------------------p0:process(setpoint_sel)
begin
case setpoint_sel is
when "00"=>
setpoint<=conv_std_logic_vector (32,8);
when "01"=>
setpoint<=conv_std_logic_vector (50,8);
when "10"=>
setpoint<=conv_std_logic_vector (130,8);
when "11"=>
setpoint<=conv_std_logic_vector (40,8);
when others=> null;
end case;
setpoint_out<=setpoint;
end process;
---------------------------------------------------------------------------------------------------------------p1:process(m_clk,reset)
variable cnt:integer:=1;
begin
if (reset='1') then
clk_sig<='0';
elsif rising_edge(m_clk) then
if(cnt=1)then
clk_sig<= not(clk_sig);
cnt:=1;
else
cnt:= cnt + 1;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------p2:process(clk_sig)
begin
if rising_edge(clk_sig) then
state<=nextstate;
end if;
end process;
--------------------------------------------------------------------------------------------------------------p3:process(state,int)
begin

case state is
when s0=> cs<='0'; nextstate<=s1;
when s1=> wr<='0'; nextstate<=s2;

when s2=> wr<='1'; nextstate<=s3;

when s3=> cs<='1'; nextstate<=s4;
when s4=> if int='1' then nextstate<=s4;
else nextstate<=s5;
end if;
when s5=> cs<='0'; nextstate<=s6;
when s6=> rd<='0'; nextstate<=s7;
when s7=> adc_data_temp<= adc_data;

nextstate<=s8;

when s8=> rd<='1'; nextstate<=s9;

when s9=> cs<='1'; nextstate<=s10;

when s10=>nextstate<=s0;
when others=> nextstate<=s0;
end case;
end process;
--------------------------------------------------------------------------------------------------------------p4:process(m_clk,reset)
variable cnt:integer:=1;
begin
if(reset='1') then
clk_sig1<='0';
cnt:=1;
elsif rising_edge(m_clk) then

if(cnt=1)then--100
clk_sig1<= not(clk_sig1);
cnt:=1;
else
cnt:= cnt + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------p5:process(clk_sig1)
variable cnt:integer:=1;
begin
if rising_edge(clk_sig1) then
if(cnt=2)then
error<=(setpoint - adc_data_temp);
cnt:=cnt+1;
end if;
if(cnt=3)then
if ( setpoint <= adc_data_temp)then
error_with_signbit<=('1' & (not (error)+'1'));
cnt:=cnt+1;
else
error_with_signbit<=('0' & error);
cnt:=cnt+1;
end if;
end if;
if(cnt=4)then
cnt:=1;
else
cnt:= cnt + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------p6:process(m_clk,reset)
variable cnt:integer:=1;
begin
if (reset='1') then
clk_sig0<='0';
elsif rising_edge(m_clk) then
if(cnt=2)then --20
clk_sig0<= not(clk_sig0);

cnt:=1;
else
cnt:= cnt + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------p7:process(clk_sig0)
variable cnt:integer:=1;
begin
if rising_edge(clk_sig0) then
sta<=nsta;
end if;
end process;
--------------------------------------------------------------------------------------------p8:process(sta)
begin
case sta is
when 0=>neu2_input<=((error_with_signbit(7 downto 0) *
w21) + b2);
nsta<=sta+1;
when 1=>neu3_input<=((error_with_signbit(7 downto 0) *
w31) + b3);
nsta<=sta+1;
when 2=>neu4_input<=((error_with_signbit(7 downto 0) *
w41) + b4);
nsta<=sta+1;
when 3=>neu5_input<=((error_with_signbit(7 downto 0) *
w51) + b5);
nsta<=sta+1;
when 4=>neu6_input<=((error_with_signbit(7 downto 0) *
w61) + b6);
nsta<=0;
when others=> nsta<=0;
end case;
end process;
---------------------------------------------------------------------------------------------end Behavioral;