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American International University-Bangladesh

Digital Design with SystemVerilog, VHDL & FPGAs

Experiment No: 01.


Name of the Experiment: Introduction to HDL Modeling, Simulation,
Synthesis, Place-and- Route and Silicon Realization in an FPLD with
Xilinx ISE WebPack 8.2i Integrated Design Environment (IDE).

Name of the Student: Hasan, Mohammed Rabiul


ID No: 11-19066-2
Section No: A
Department: EEE
Date of Performance: 13/01/15
Date of Submission: 16/03/15

Faculty: Shahriyar Masud Rizvi.

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