Chapter1: Introduction

Chapter 1: Introduction
Prof. Ming-Bo Lin

Department of Electronic Engineering

National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles
Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Objectives
After completing this chapter, you will be able to understand:
The features of HDLs and Verilog HDL
The HDL-based design flow
The basic features of the modules in Verilog HDL
How to model a design in structural style
How to model a design in dataflow style
How to model a design in behavioral style
How to model a design in mixed style
How to simulate/verify a design using Verilog HDL

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
HDL-based design flow

Introduction to Verilog HDL

Module modeling styles
Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Importance of HDLs
HDL: Hardware Description Language
Two commonly used HDLs
Verilog HDL (also called Verilog for short)
VHDL (Very high-speed integrated circuits HDL)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Features of HDLs
Design can be described at a very abstract level
Functional verification can be done early in the
design cycle
Designing with HDLs is analogous to computer
programming

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Verilog HDL
A general-purpose, easy to learn, and easy to use
HDL language
Allowing different levels of abstraction in the same
module
Programming Language Interface (PLI)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
HDL-based design flow

Introduction to Verilog HDL

Module modeling styles
Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

HDL-Based Design Flow

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Concept of module
Basic syntax
Data types

Module modeling styles

Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Concept of Modules
Module
A core circuit (called internal or body)
An interface (called ports)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Modules Verilog HDL modules

module --- The basic building block

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Concept of module
Basic syntax
Data types

Module modeling styles

Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Lexical Conventions
Almost the same lexical conventions as C language
Identifiers: alphanumeric characters, _, and $
Verilog is a case-sensitive language
White space: blank space (\b), tabs (\t), and new
line (\n)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Lexical Conventions
Comments
// --- the remaining of the line
/* .*/ --- what in between them

Sized number: <size>`<base format><number>

4`b1001
16`habcd

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Lexical Conventions
Unsized number:
`<base format><number>
2009
`habc

x or z
x: an unknown value
z: a high impedance

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Lexical Conventions
Negative number:
-<size>`<base format><number>
-4`b1001
-16`habcd

_ and ?
16`b0101_1001_1110_0000
8`b01??_11?? // = 8`b01zz_11zz

String: Have a lovely day

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Coding Style
Lowercase letters
For all signal names, variable names, and port names

Uppercase letters
For names of constants and user-defined types

Meaningful names
For signals, ports, functions, and parameters

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

The Value Set

Four-value logic

0 : logic 0, false condition

1 : logic 1, true condition
z : high-impedance
x : unknown

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Concept of module
Basic syntax
Data types

Module modeling styles

Simulation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Data Types
Nets: any hardware connection points
Variables: any data storage elements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Nets
Driven by

Primitive
continuous assignment
force release
module port

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Variables
Assigned value only within
Procedural statement
Task
Function

Cannot be used as
input
inout

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-23

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles

Introduction
Structural style
Dataflow style
Behavioral style
Mixed style

Simulation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Module Modeling Styles

Structural style
Gate level
Switch level

Dataflow style
Behavioral or algorithmic style
Mixed style
RTL = synthesizable behavioral + dataflow constructs

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-25

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles

Introduction
Structural style
Dataflow style
Behavioral style
Mixed style

Simulation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Port Declaration
Types of ports
input
output
inout

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Port Connection Rules

Named association
Positional association

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Port Declaration

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Structural modeling
// gate-level hierarchical description of 4-bit adder
// gate-level description of half adder
module half_adder (x, y, s, c);
input x, y;
output s, c;
// half adder body
// instantiate primitive gates
xor (s,x,y);
and (c,x,y);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Structural modeling
// gate-level description of full adder
module full_adder (x, y, cin, s, cout);
input x, y, cin;
output s, cout;
wire s1, c1, c2; // outputs of both half adders
// full adder body
// instantiate the half adder
half_adder ha_1 (x, y, s1, c1);
half_adder ha_2 (cin, s1, s, c2);
or (cout, c1, c2);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Structural modeling
// gate-level description of 4-bit adder
module four_bit_adder (x, y, c_in, sum, c_out);
input [3:0] x, y;
input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3; // intermediate carries
// four_bit adder body
// instantiate the full adder
full_adder fa_1 (x[0], y[0], c_in, sum[0], c1);
full_adder fa_2 (x[1], y[1], c1, sum[1], c2);
full_adder fa_3 (x[2], y[2], c2, sum[2], c3);
full_adder fa_4 (x[3], y[3], c3, sum[3], c_out);
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Hierarchical Design

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-33

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles

Introduction
Structural style
Dataflow style
Behavioral style
Mixed style

Simulation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Dataflow Modeling
module full_adder_dataflow(x, y, c_in, sum, c_out);
// I/O port declarations
input x, y, c_in;
output sum, c_out;
// specify the function of a full adder
assign #5 {c_out, sum} = x + y + c_in;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-35

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles

Introduction
Structural style
Dataflow style
Behavioral style
Mixed style

Simulation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Behavioral Modeling
module full_adder_behavioral(x, y, c_in, sum, c_out);
// I/O port declarations
input x, y, c_in;
output sum, c_out;
reg sum, c_out; // need to be declared as reg types
// specify the function of a full adder
always @(x, y, c_in) // always @(*) or always@(x or y or c_in)
#5 {c_out, sum} = x + y + c_in;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-37

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles

Introduction
Structural style
Dataflow style
Behavioral style
Mixed style

Simulation
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Mixed-Style Modeling
module full_adder_mixed_style(x, y, c_in, s, c_out);
// I/O port declarations
input x, y, c_in;
output s, c_out;
reg c_out;
wire s1, c1, c2;
// structural modeling of HA 1
xor xor_ha1 (s1, x, y);
and and_ha1(c1, x, y);
// dataflow modeling of HA 2
assign s = c_in ^ s1;
assign c2 = c_in & s1;
// behavioral modeling of output OR gate
always @(c1, c2) // always @(*)
c_out = c1 | c2;
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles
Simulation
Basic simulation constructs
System tasks
An example

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Basic Simulation Constructs

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

1-41

Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles
Simulation
Basic simulation constructs
System tasks
An example

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

System Tasks for Simulation

$display
$display(ep1, ep2, , epn);
ep1, ep2, , epn: quoted strings, variables, expressions

$monitor
$monitor(ep1, ep2, , epn);

$monitoton
$monitotoff
$stop
$finish
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Time Scale for Simulations

Time scale compiler directive
`timescale time_unit / time_precision

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

Syllabus
Objectives
Introduction
Introduction to Verilog HDL
Module modeling styles
Simulation
Basic simulation constructs
System tasks
An example

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- A 4-bit adder

// Gate-level description of 4-bit adder
module four_bit_adder (x, y, c_in, sum, c_out);
input [3:0] x, y;
input c_in;
output [3:0] sum;
output c_out;
wire C1,C2,C3; // Intermediate carries
// -- four_bit adder body-// Instantiate the full adder
full_adder fa_1 (x[0],y[0],c_in,sum[0],C1);
full_adder fa_2 (x[1],y[1],C1,sum[1],C2);
full_adder fa_3 (x[2],y[2],C2,sum[2],C3);
full_adder fa_4 (x[3],y[3],C3,sum[3],c_out);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- A 4-bit adder

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- A Test Bench

`timescale 1 ns / 100 ps // time unit is in ns.
module four_bit_adder_tb;
//Internal signals declarations:
reg [3:0] x;
reg [3:0] y;
reg c_in;
wire [3:0] sum;
wire c_out;
// Unit Under Test port map
four_bit_adder UUT (.x(x), .y(y), .c_in(c_in), .sum(sum), .c_out(c_out));
reg [7:0] i;
initial begin // for use in post-map and post-par simulations.
// $sdf_annotate ("four_bit_adder_map.sdf", four_bit_adder);
// $sdf_annotate ("four_bit_adder_timesim.sdf", four_bit_adder);
end
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- A Test Bench

initial
for (i = 0; i <= 255; i = i + 1) begin
x[3:0] = i[7:4]; y[3:0] = i[3:0]; c_in =1'b0;
#20 ; end
initial #6000 $finish;
initial
$monitor($realtime,ns %h %h %h %h", x, y, c_in, {c_out, sum});
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- Simulation Results

#
#
#
#
#
#
#
#
#
#
#
#
#

0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
220ns
240ns
260ns

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
2
3
4
5
6
7
8
9
a
b
c
d

0
0
0
0
0
0
0
0
0
0
0
0
0
0

00
01
02
03
04
05
06
07
08
09
0a
0b
0c
0d

#
#
#
#
#
#
#
#
#
#
#
#
#
#

280ns
300ns
320ns
340ns
360ns
380ns
400ns
420ns
440ns
460ns
480ns
500ns
520ns
540ns

0
0
1
1
1
1
1
1
1
1
1
1
1
1

e
f
0
1
2
3
4
5
6
7
8
9
a
b

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0e
0f
01
02
03
04
05
06
07
08
09
0a
0b
0c

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter1: Introduction

An Example --- Simulation Results

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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