Lab Manual s07

CSUS COLLEGE OF ENGINEERING AND
COMPUTER SCIENCE
DEPARTMENT OF ELECTRICAL AND ELECTRONIC
ENGINEERING
EEE 102L Analog/Digital Electronics

Laboratory
Laboratory Manual
Spring 2007
Table of Contents
EEE 102L Analog/Digital Electronics Laboratory Course Outline
EEE 102L Parts Kit Fall 2004
Objectives and Goals of the Laboratory
Laboratory 1 Introductory PSpice Programming Assignment
Laboratory 2 Introduction to LabVIEW
Notes Concerning the Operation of the HP Signal Generators
Laboratory 3 Exploration of Diode Characteristics
Laboratory 4 Diode Circuits
Laboratory 5 MOSFET Transistor Characteristics
Laboratory 6 BJT Transistor Characteristics
Laboratory 7 Common-Emitter Amplifier Design
Laboratory 8 OP Amp Instrumentation Amplifiers and First Order Filters
Appendix
3
5
6
9
10
19
20
24
27
31
35
37
41
EEE 102L Analog/Digital Electronics Laboratory

Service Course
2006 2008 Catalog Data: EEE 102L. Analog/Digital Electronics Laboratory. Introduction to analog/digital
electronics, diodes, FET's, BJT's, DC biasing, VI characteristics, single stage amplifiers, power supplies and voltage
regulators, power electronic devices, OP-amps, active filters, A/D and D/A converters. PSPICE used extensively.
Note: Cannot be taken for credit by E&EE Majors. Prerequisite: ENGR 017. Corequisite: EEE 102. 1 unit.
Text: Jaeger, R.C., Microelectronic Circuit Design, 2nd Edition, McGraw-Hill, 2004, ISBN 0-07-232099-0
Support Software: Herniter, M.E., Schematic Capture with Cadence PSpice, Prentice-Hall, 2nd Edition, 2003,
ISBN 0-13-048400-8.
Course Goals:
1.
2.
To reinforce learning in the accompanying EEE 102 course through hands-on experience with electronic
circuit analysis, design, construction, and testing.
To provide the student with the capability to use LabVIEW and PSpice software as tools in electronic
circuit analysis and design, and in future courses, design projects, and professional work assignments.
Prerequisites by Topic:
1.
2.
3.
General knowledge of a structured programming language (i.e. C++).

Basic physical concepts of electricity and magnetism.
Basic circuit analysis concepts and procedures.
Topics Covered/Class Schedule/Evaluation:

Topics
1.
2.
3.
4.
5.
6.
Introduction to Software Tools and Workstation Equipment: Introduction to PSpice Schematic Circuit
Construction and Analysis; Introduction to LabVIEW Virtual Instrument Workstation Operation and A/D
Conversion
Solid State Diodes and Diode Circuits: Diode Characteristics in Forward and Reverse Bias Conditions;
Power Supplies and Wave Shaping Circuits
Field Effect Transistors: FET Characteristics; Operating Regions and Characteristics of NMOS Devices;
MOSFET Biasing Circuits, Analysis, Design, Construction, Testing, and Simulation
Bipolar Junction Transistors: Operating Regions and Characteristics of the BJT; Forward-Active Region
Analysis and Design; BJT Biasing Circuits, Analysis, Design, Construction, Testing, and Simulation
Small-Signal Modeling and Linear Amplification: The BJT Common-Emitter Amplifier Analysis, Design,
Construction, Testing and Simulation
Operational Amplifiers: The Differential Amplifier; Frequency Response; Input/Output Impedance;
Instrumentation Amplifiers; Common Mode Signal Analysis; Active Filters
Course Outline
Week
Topic
Lab #
1
2
Introduction to the Lab

Introduction to PSpice
none
1
Report Due
3
Introduction to LabVIEW VI Operations
2
_____________________________________________________________________________________________
4
Diode Characteristics 1
3
R (Labs 1 & 2)
5
Diode Characteristics 2
3
6
Diode Circuits 1
4
7
Diode Circuits 2
4
8
Field Effect Transistor Characteristics
5
R (Labs 3 & 4)
9
FET Bias Circuits
5
10
Bipolar Junction Transistor Characteristics 6
11
BJT Bias Circuits
6
-------------------------------------------------------------------------------------------------------------------------------------------12
C-E Amplifier Design and Simulation
7
R (Labs 5 & 6)
13
C-E Amplifier Construction & Testing
7
14
Op-Amp Instrumentation Amplifier
8
15
Op-Amp Bandpass Filter
8
Exam Week
R (Labs 7 & 8)
--------------------------------------------------------------------------------------------------------------------------------------------
Evaluation
Laboratory Reports: Eight formal laboratory reports are required. Note that they are due two at a time according
to the schedule above. The first six count 10 points each; the last two count 20 points each for a total of 100 points.
Reports will be graded based upon written quality, format, content, and correct data analysis. Late reports will
have 1 point deducted for the first week that they are late, and will NOT be accepted for credit after that week.
Plagiarized reports will NOT be accepted.
Science and Design Content Distribution:

Design 1 unit or 100%
Contribution of Course to the Professional Education Component:

1.
2.
Laboratory exercises include practical electronic circuit design and analysis problems with realistic source
and load constraints. Actual circuit construction and testing are emphasized equally with simulation
LabVIEW and PSpice analysis and design applications introduce students to major professional
engineering software tools.
Relationship of Course to Program Outcomes:

1.
2.
#4 Knowledge of Engineering core: This course adds electronic circuit analysis and design applications to
fundamental concepts of circuit analysis, and computer programming.
#7 Use of contemporary tools for analysis and design: This course applies computer methods using PSpice
and LabVIEW software tools to electronic circuit analysis and design.
Course Coordinator: John Oldenburg, EEE
Date: January 15, 2007
EEE 102L Parts Kit Spring 2005
Capacitors
Resistors 1/4 W, Carbon Film, 5%
Qty.
1
1
1.
2.
2
2
Qty.
3.
2
1
1
2
2
1
1
1
2
1
1
2
1
4
1
1
2
1
1
6
1
6
2
2
2
1
1
4
1
4
2
2
2
1
1
2
2
2
Value
10
15
22
33
51
100
150
220
330
510
680
820
1K
1.2
1.5
2.2
3.3
5.1
6.8
8.2
10
12
15
20
30
51
68
82
100
120
150
200
300
510
680
820
1.0
5.1
10
2
1
1
1
1
Value Description
22 pF Ceramic Disc, 500 V
0.01 F Ceramic Disc, 100
0.1 F Ceramic Disc, 50 V
1 F Metallized Poly Film, 250 V
(Digikey P10979-ND)
10 F Metallized Poly Film, 100 V
(Digikey EF1106-ND)
47 F Radial Electrolytic, 25 V
Diodes/Rectifiers
Qty.
1
1
3
1
Description
1N4001 Si Rectifier
W005G Bridge Rectifier
1N914 Si Switching Diode
1N4734A 5.6V, 1W Zener Diode
Transistors
Qty.
1
1
Description
2N2222A NPN Transistor (TO-9)
IRF630A NMOS FET Power Transistor
Integrated Circuits
Qty.
1
2
1
Description
Burr-Brown INA118P Instrumentation
Amplifier
LM741N Operational Amplifier
CD4007 CMOS Dual Complementary
Pair/Inverter
Miscellaneous
Qty.
5'
5'
2
Description
22AWG Hook-up Wire, Blue
22AWG Hook-up Wire, Yellow
9V Battery Clip
Note: A Standard pin-socket protoboard is required, but not included in the kit. A small
one costing $5-$7 is sufficient and available at Radio Shack, Newark or Frys Electronics
CSUS College of Engineering and Computer Science

Department of Electrical & Electronic Engineering
OBJECTIVES AND GOALS OF THE LABORATORY
The laboratory for this course has two major objectives: 1) To acquaint you with virtual
instrument technology for electronic circuit design and testing, and 2) to introduce you to the
simulation and physical circuit behavior of basic electronic devices and circuits. At the end of
the course, you should have acquired knowledge of the fundamental principles of electronic
circuits and gained considerable facility in making time and frequency domain measurements
using modern electronic instrumentation.
GENERAL LABORATORY POLICIES
1. All laboratory work will be done in student pairs or a group of three. Each student will be
required to submit an individual laboratory report.
2. You are strongly urged to read the reference material and perform any pre-lab work
specified in the laboratory handout before you come to the lab. In many cases, you will need this
knowledge in order to efficiently plan your methods of investigation and finish the lab in the
time allotted.
3. The laboratory instructions will specify the information required in the laboratory report;
however, you are not restricted to providing only this information and the inclusion of comments
about the validity of the data and an appendix of relevant analytical work is strongly encouraged.
Laboratory Report Format
a. Introduction -- give a one - two paragraph overview, in your own words, which
describes the topic covered in the laboratory. This should be complete and concise.
b. Procedure Notes -- note any changes (voluntary or required by circumstance) from the
procedure in the handout, which you feel may have had a significant bearing on the
results. You don't need to repeat procedures described in the laboratory instructions.
c. Data and Results -- include all data specified in the handout. Use tables and graphs
where appropriate. Figures (pictures, tables, graphs, etc.) should each have a complete
figure "legend" which briefly describes the relevant information in the figure. State
results CLEARLY. Describe your results and answer any specific questions asked in the
handout in this section. You may choose to include analytical work in an appendix to
support your results. In cases where pictures of VI front panels have been taken to
document results, you may insert them directly as figures in a Microsoft Word laboratory
report document.
d. Conclusions -- did your results agree with or differ from what you might have
expected from lecture and/or your readings? Comment, as part of your conclusions,
about the value of the laboratory exercise with respect to its improvement of your
understanding of the subject material.
e. Appendix -- include relevant analytical calculations and any miscellaneous additions.
4. Laboratory reports must be hard copy format and will be due one week following the end of
the scheduled laboratory exercise (see the schedule of laboratories in the EEE 102L Course
Outline), or as determined by your instructor. They will be graded based upon completeness and
the quality of both the analysis and documentation. Reports will have one point deducted for
the first week that they are late. Reports more than one week late will NOT be accepted.
Plagiarized reports will NOT be accepted.
5. Almost all necessary equipment will be found at the computer workstations in the laboratory.
Any other equipment of a general nature that you may desire (DVMs, Capacitance Checkers,
Transformers, etc.), if not provided already at the lab station, may be requested from the
instructor (only during scheduled laboratory periods). A selection of electronic parts that you
will need is available as an EEE 102L Parts Kit, and may be obtained from your Laboratory
Instructor. Obtain a Parts Kit Purchase Form from the EEE 102L Web page. You must pay for
the parts kit and get a receipt at the Cashiers Window in Lassen Hall. Give your receipt to the
lab instructor in exchange for a parts kit. Resistors, potentiometers, capacitors, diodes,
transistors, op-amps, ICs, hook-up wire, and 9V battery clips are included. You are also free to
purchase what you need from suppliers such as Radio Shack, Fry or Newark Electronics in town,
or to use any applicable electronics parts that you may already own.
6. Starting in week 3, you will be required to have the Parts Kit for circuit construction.
You may share the cost of one kit with your lab partner(s). You and your lab partner(s) should
also purchase a suitable (two strips of terminals are sufficient) protoboard if you don't already
own one (estimated cost is $5 - $7 at the electronics suppliers mentioned above), and two 9V
alkaline batteries to use as a power supply in the last lab exercise. You will find that having your
own protoboard will be helpful in many other laboratories in the CpE program, and will be well
worth the expense.
7. As a registered EEE 102L student, you will be issued the undergraduate student lock code to
RVR-5017. You have the responsibility to keep that code to yourself and to use the laboratory
only for the purposes of the course. You have priority use of workstations in the VI Laboratory
during the scheduled hours for the laboratory portion of the course. In general however, the lab
is not crowded and you should have good access to the equipment at other times.
Open Laboratory Rules for RVR-5017
1. Your open access to this laboratory is being granted under the assumption that you will
conduct your activities there as a professional engineer and according to the following rules.
2. You should not admit anyone except yourself to the laboratory. It is for your use for the
purposes of the course you are taking and for no other purpose.
3. No eating or drinking in RVR-5017. Computers are very sensitive to spills!
4. The Macintosh workstations are primarily for support of LabVIEW and PSpice
programming/applications. They also have Microsoft Office available for laboratory document
preparation. Surfing the Net, E-mail and Instant Messaging, and other workstation needs should
be met using your own personal computer or those in open laboratories on the campus. To be
courteous to other students who will follow you, please leave the desktop of the workstation with
all icons in the default condition when you are finished with your work. Please empty your
trash!
5. Report any equipment malfunctions to your instructor as soon as it is practical to do so.
6. No equipment, manuals, etc. may be removed from the laboratory without approval of the
instructor. Peripheral equipment (PARTICULARLY TEST CABLES AND CONNECTORS)
associated with each workstation MUST remain with that station.
7. Times for use of RVR-5017 are posted on the door of the laboratory. Instructor help will be
available in the lab only during scheduled hours for the course.
8. Violation of the lab rules may result in our having to close the laboratory and restrict your use
of it only to scheduled laboratory hours. Please act professionally and responsibly!
Laboratory 1 Introductory PSpice Programming Assignment

Your goal is to complete a brief, self-instructional introduction to PSpice programming during
this laboratory, and to become familiar with the Macintosh workstations and the operation of the
software under VirtualPC. You will use chapters 1 and 3 of Herniter, M.E., Schematic Capture
with Cadence PSpice, 2nd Edition, Prentice Hall, 2003 as your guide. Please read this material
carefully before the lab period so that you can minimize the time required to complete the work.
1. Check to see that your workstation monitor is on standby (yellow light on). If the monitor is
off, turn it on before you boot up the workstation. Start up your Macintosh workstation by
pressing the gray power button on the front of the chassis. Cadence PSpice software is installed
on the Virtual PC partition on the Macintosh workstations. Find Virtual PC under the Apple
Menu (). Open Virtual PC by double clicking on its icon. When Virtual PC is fully loaded
you will see a window on the Macintosh desktop that looks like a familiar Windows 2000
Professional desktop. Under Start/Programs/, you will find the Cadence PSpice Software
organized as described in Chapter 1 of the Herniter text. There is a shortcut icon on the desktop
that will get you to the software very quickly. Alternately, (and highly preferred) you may
install the Cadence Pspice, which accompanies the Herniter text, on your home workstation and
complete this introduction as described. However, do not neglect to use the lab period to become
familiar with the Macintosh workstations, since you will be using them in subsequent laboratory
sessions. Follow the circuit schematic creation and dc nodal analysis instructions provided in
chapters 1 and 3 (up to but not including Exercise 3-1). You may skip the section J on
formatting the title block, and section M on creating hierarchical designs in chapter 1. When you
are finished, select Save All and Quit from the Macintosh File menu. This will save the current
state of the VirtualPC and allow it to be quickly started again.
2. Files can be moved to different workstations in the laboratory by placing them in the Voyager
Temporary server partition. That partition is accessible from virtually any computer connected
to the ECS network. When your project is complete, save it (the entire project partition with all
supporting files) as an appropriately named file on your personal USB Flash Drive (highly
recommended). You may FTP your file to a secure personal account using the FETCH utility
under the Apple menu or transfer it to the Voyager Temporary partition and access it from any
networked workstation. Only a hard copy picture of your final circuit schematic, as it stands at
the end of the chapter 3 section of the Herniter text, is required as a report for this first
laboratory exercise. (See Procedure for Taking Pictures of the Active Window on Macintosh
Workstations in the appendix of this lab manual.)
3. Your file should be submitted to your instructor, on or before the due date for the first report
(R) on the schedule.
4. You will score 10 points for successful completion of the PSpice assignment. One point will
be deducted during the first week after the date due for late submissions. No work will be
accepted which is more than 1 week late. No plagiarized work will be accepted. Best of luck!
CSUS College of Engineering and Computer Science

Department of Electrical & Electronic Engineering
Laboratory 2 Introduction to LabVIEW
Pre-lab Work
Your goal is to complete a brief, introduction to LabVIEW operations during this week of the
course. The Getting Started with LabVIEW PDF file on the EEE 102L Web site will be your
reference for this lab. You may choose to purchase the LabVIEW Student Edition software
for use on your home computer; however this is NOT required. The software is Windows 98
and higher, and Mac OS X compatible. Most of the exercises/problems in the Student Edition are
designed to be completed without an I/O (analog-to-digital and digital-to-analog converter)
board. Having the software will allow you to use the virtual instruments (VIs), from the lab,
which do not require I/O, at home to repeat lab work if necessary and to help solve some
problems in the lecture portion of the course. Unfortunately, the LabVIEW Student Edition is
Version 7 and our LabVIEW Professional Edition on the Macintoshes is still Version 6. VIs
created under Version 6 can be read and saved by Version 7, but Version 6 cannot read Version
7 files.
The computers available to you in RVR-5017 are Power Macintosh G4s with the Macintosh
version of the LabVIEW software loaded on the hard drive of each station. These workstations
are also equipped with National Instruments 6024E data acquisition (I/O) boards for "real world"
interfacing. EEE 102L laboratory exercises in the last 13 weeks of the course will use LabVIEW
I/O. Consequently, they will have to be done on the Macintosh workstations, unless you choose
to purchase a suitable I/O board or USB peripheral for your "home" computer (about $125 $650). Therefore, you will need to become familiar with use of the Macintosh computers, even
if you choose to purchase the LabVIEW Student Edition software for your home computer.
Notes on Workstation and File Operations
1. If the workstation monitor is not on standby (yellow light on), turn it on. Start up a
Macintosh by pressing the gray button on the front of the chassis. Although the MAC OS 9.2.2
is very similar to current versions of Windows OS, if you are not familiar with the Macintosh
operating system, you may want to take some time to follow the Macintosh Tutorial that you can
access from the Help menu in the top menu bar of the monitor screen.
2. You will probably need a USB Flash Drive to temporarily store your work and/or to keep safe
copies of submitted work. Notice that the keyboard has a convenient USB port in the top left
corner. Also, the Voyager server Temporary partition on the ECS network can be accessed from
the desktop icon on the lab workstations. Thus, files can be transferred between two computers
via this partition, if desired.
3. On the Macintosh workstations, LabVIEW will be found under the Apple menu. Double
click on its icon to open it. Please appropriately Quit all open programs from the File menu,
and select Shut Down from the Special menu when you are finished working with the
10
Macintoshes. Closing an application window in Mac OS does NOT automatically quit a

program. If you have multiple programs open you may find that command execution time
is significantly prolonged. These workstations are normally kept off when not in use so
Shut Down when you are finished working. Leave the monitor on standby.
4. At the end of a workstation session, you should copy any LabVIEW files, Word files, or
Picture files (see the appendix) that you create to one of your personal data storage devices or
server accounts. These are your personal files. If you return to a workstation to resume your
work, you should open your personal files from your storage device or account, and save any
changes to that device or account. (Alternately, you may create a folder with your name on it on
a "Temporary" partition (on Voyager or on the workstation) and store your files temporarily
there. Be aware that files stored on temporary partitions are NOT secure and should be
transferred to a secure disk or account ASAP.)
5. A formal report from this Lab 2 should be submitted to your instructor on or before the due
date (R). This report should follow the report format described in the Lab Goals & Policies
section of this manual. Unless otherwise specified by your lab instructor, it should be prepared
in hard-copy form, which includes all graphics.
7. You will score a maximum of 10 points for successful completion of Lab 2. One point will
be deducted during the first week after the date due for late submissions. No work will be
accepted which is more than 1 week late.
Good luck!
11
DIGITAL RECORDING OF ANALOG SIGNALS AND MEASUREMENTS IN THE

TIME AND FREQUENCY DOMAINS
Laboratory 2 -- Introduction to LabVIEW VI Operations
OBJECTIVES
To become familiar with Virtual Instrument operation for the digital recording of analog
signals and with the important phenomena of amplitude resolution and aliasing; to
introduce some common time and frequency domain signal measurements.
REFERENCES
Jaeger, Ch. 1, sections 1.2, 1.5, 1.6 and 6.3, and the attached handout on Fourier Series
Square Wave Analysis
EQUIPMENT
1.
2.
3.
4.
5.
EEE102L Lab_2 -- LabVIEW Virtual Instruments

HP Signal generator
1 F Capacitor and 10 K Resistor (RC circuit) from your Parts Kit
Protoboard for circuit construction
Miscellaneous patch cords and connectors
There are four Virtual Instruments (VIs) available for this lab exercise in a folder labeled
EEE102L Lab_2 on the computer at your workstation.
[Path hard
drive/Applications(OS9)/LabVIEW 6/User/Virtual Instruments S06]. Double click your mouse
on the LabVIEW icon under the Apple menu. The LabVIEW startup screen will have an
option to Open VI. Click on it and a window will open that will allow you to conveniently
navigate to the desired folder of lab exercises.
Within the Lab_2 folder, the A/DresCheck2.vi will allow you to observe the amplitude
resolution characteristics of the 6024E A/D converter board in each workstation. The Alias3.vi
will allow you to examine the effects of different digital sampling rates on the recorded analog
signal. The GDAnal2.vi will allow you to measure the "rise time" and "slew rate" of simulated
logic gate signals. And finally, the WaveAnal3.vi will allow you to see the amplitude frequency
spectrum (Fourier Series Analysis) of a signal, and to examine the effect of lowpass filtering on
that signal. Before you use a VI, examine both its front panel and its wiring diagram. Look at
the description of each VI contained under File/VI Propertie/Documentation (accessed from the
LabVIEW menu bar). A printout of the front panel and descriptions of each VI that will be used
in this course will be found in the appendix at the end of this lab manual. Ask the instructor for
help if you have any questions about the use of a VI.
12
PART I -- A/D CONVERTER AMPLITUDE RESOLUTION

Analog-to-Digital converters typically have an analog amplitude resolution of
VFSV/2(n+1). The National Instruments 6024E A/D board in your workstation contains a 12-bit
converter, which is set for an amplitude range of -10 V to +10 V.
1. Before you begin, refer to the Notes Concerning the Operation of the HP Signal Generators
attached at the end of this laboratory exercise. Connect the HP signal generator to the channel 0
input of the VI system. (See the appendix for I/O connections.) Set the generator to deliver a
100 mV DC output signal, using the DC offset control to set DC amplitude. Open the
A/DResCheck2.vi in the EEE102L Lab_2 folder. Look at the Documentation (File/VI
Properties/Documentation) under the LabVIEW menu bar to get a full description of this VI.
2. Make sure that the front panel controls on this VI are set to measure a DC signal. You will
start at 100 mV and increase the DC output of the HP signal generator in 1 mV increments until
you reach 110 mV. Press the RUN button in the menu bar of the VI to have it record the 4-Digit
Voltmeter reading and the Boolean Conversion value of the A/D converter for each increment in
generator voltage. (Note that the offset setting on the HP generator numerical display, typically,
will NOT be accurate at low output levels. The 4-Digit Voltmeter on the VI, however, IS
designed to accurately measure the generator output.) From your measured data, estimate the
amplitude resolution of the A/D converter. How does your value compare with the value
predicted by the formula given at the beginning of PART I?
3. Set the HP signal generator to deliver a DC output voltage of 4.23 V. Record the 4-Digit
Voltmeter reading and the Boolean conversion value of the A/D converter as measured on the VI
front panel. Use an appropriate calculation to determine the expected Boolean conversion value
of the 12-bit A/D converter, and compare the expected and measured values.
4. Close A/DResCheck2.vi
PART II -- ALIASING
The phenomenon of aliasing occurs when you attempt to digitally sample a signal at a
sampling rate that is too slow for "faithful reproduction" of its full frequency content. The result
is a recorded signal that contains unexpected lower frequency Fourier series components, and
therefore represents a distortion of that signal. A famous mathematical theorem, Nyquists
Sampling Theorem, states that the sampling rate must be greater than two times the highest
significant signal frequency in order to avoid aliasing. The figure below will serve as an
example of aliasing for a signal containing a single sinusoidal frequency. Note how the apparent
frequency of the undersampled signal is significantly lower than expected, and that its actual
waveform shape is distorted.
You will explore the relationship between aliasing and digital sampling frequency using
the following study protocol:
13
1. Connect the HP signal generator to the channel 0 input of the VI system and adjust its settings
to produce a 100 Hz sine wave with 10 V p-p amplitude and zero DC offset. Open the Alias3.vi,
which is inside the EEE102L Lab_2 folder. Look at the Documentation (File/VI
Properties/Documentation) under the menu bar to get a full description of this VI. If you click
the RUN button on the Alias3.vi front panel, the instrument will record the generator signal as
waveform 1 at a sampling rate of 1000 samples/second (Hz), and as waveform 2 at the sampling
rate of 125/s. Note that the waveform 2 sampling rate is set using the rotary switch on the front
panel of the VI. Click on the red and blue chart measurement cursors and drag (manually adjust)
them to measure the period of waveform 2. Take a "picture" of the front panel to document your
results. (See the appendix for information about taking "pictures" on the Macs.)
2. Use the mouse and the VI hand tool to rotate the switch on the front panel of the VI so that
waveform 2 is now recorded by sampling the generator signal at 150 samples/second. Repeat the
recording of the signals and, again, measure the waveform period and take a "picture" of the
front panel to document your results.
3. Repeat 2 above for sampling rates of 175/s, 200/s, 225/s and 250/s
4. Using the waveform 2 period measurements, calculate the recorded (apparent) frequency of
waveform 2 at each sampling rate. It might help if you first calculate the expected alias
frequency using the formula given in lecture. Describe the differences between the six recorded
waveforms produced by the six different sampling rates. Consider both the waveform shape and
the apparent frequency. Which ones are aliased?
5. What can you conclude from your data about the relationship between digital sampling rate
and faithful reproduction of the signal frequency?
6. Close Alias3.vi.
PART III RISE TIME AND GATE DELAY TIME MEASUREMENTS -- Time Domain
14
Since digital gates dont respond instantaneously to changes in their input signals, it is
often desirable to measure the rise time of an electronic gate, its slew rate and its "delay
time". In this part of the laboratory you will be recording the response of an RC circuit
(simulating a logic gate connection) to a square wave signal, and measuring its rise time, slew
rate and delay time.
1. Set the signal generator to produce a 5 Hz square wave with 5 V p-p amplitude and 2.5 V DC
offset. Use a 1.0 F capacitor and 10 resistor from your Parts Kit to construct a series RC
circuit. (See the circuit diagram below for reference.) Connect the output of the signal generator
to channel 0 of the VI system and across the RC circuit. Connect channel 1 of the VI system
across the capacitor in the circuit. Open GDAnal2.vi. Make sure to review the Documentation of
this VI, since it contains some important information regarding signal recording.
R
+
V0
HP
(channel 0)
-
+
C
V1
(channel 1)
-
2. Now click the RUN button on the VI to record the two signals. Repeat the procedure, if
necessary, until you are satisfied with your measurement results. Then take a picture of the front
panel of the instrument to document this result for your lab report.
3. This VI will automatically measure the "rise time", "slew rate" and "delay time" of the
simulated gate input signal. Note that rise time of the signal is defined as the time it takes the
signal to go from 10% to 90% of its peak-to-peak amplitude. The slew rate is the voltage rise
divided by the rise time. The gate delay time is the time differential between the 50% amplitude
points on the input and output waveforms. These are common measures of gate dynamic
response in digital circuits. Note that, in this virtual instrument, the cursors are automatically
placed at the appropriate points on the waveform in order to make the desired measurements a
great convenience, wouldnt you agree?
4. Calculate the expected rise time, slew rate and delay time for the capacitor voltage in this RC
circuit, and compare those calculations with the three automatic measurements made by the VI in
part 3 above.
5. Close GDAnal2.vi
PART IV -- FOURIER SERIES AMPLITUDE SPECTRUM OF A SQUARE WAVE -Frequency Domain
1. Open WavAnal3.vi and review its panel, wiring diagram and documentation.
2. Use the WavAnal3.vi to record a 2V p-p, 100 Hz. square wave with zero DC offset from the
signal generator. Note that the upper waveform graph is the time domain signal with the time
15
axis displayed in seconds. The lower waveform graph is the frequency domain signal (Fourier
Amplitude Spectrum) with the frequency axis displayed in Hertz. Take a picture of your front
panel results as documentation for your report.
3. Manually adjust the position of the red chart cursor (click on and drag it using the mouse) to
measure the peak height at each harmonic frequency in the amplitude spectrum display. Record
the values of peak height and frequency. Are the fundamental and harmonic frequencies of the
square wave consistent with the values predicted from a Fourier series expansion (see attached
handout) for the square wave? Are the measured peak heights of the fundamental frequency and
the next four harmonics in the square wave consistent with the values predicted from the Fourier
series expansion? (Note: relative peak height, as calculated in the handout, sets the height of the
fundamental frequency peak at 1.00 and measures the other peak heights relative to that one.)
Justify your answer.
4. Pressing the Lowpass Filter button, and adjusting the slider switch on the VI front panel, will
allow you to record the input square wave signal after it is sharply low-pass filtered with
adjustable cutoff frequencies from 0 - 1000 Hz. Notice the effects of filtering on the time
domain waveform and the loss of particular harmonic components in the Amplitude Spectrum at
each filter cutoff frequency setting. Take pictures of your front panel results as documentation
for your report. Describe the effects of the filtering in both the time and frequency domains.
Fourier Series Representation for a Square Wave of Period T and Amplitude 1
V
-1
16
According to the theory of Fourier Series, any periodic function of time can be represented as an
infinite series of sine and cosine terms that have arguments that are integral multiples of the
"fundamental frequency" of the periodic function. The fundamental frequency (fo) is defined as:
fo = 1/T where (T) is the period of the function. If we define the fundamental radian frequency
of the periodic function as: o = 2f, the Fourier Series may be written as follows:
V(t) = ao + ancos not + bnsin n ot

2 n=1
n=1
where
T
ao = 2
T
V(t)dt ; an = 2
T
V(t)cos (not)dt ; bn = 2
T
V(t)sin (n ot)dt
0
We evaluate the above constants as follows:

T
2
ao = 2
T
V(t)dt = 2
T
1dt + 2
T
-1dt
T
2
T
ao = 2 [t]20 + 2 [-t]T = 1 - 2 + 1 = 0
T
T 2
T
2
an = 2
T
V(t)cos (nt)dt = 2
T
an = 2 T sin n2 t
T n2
T
T
2
0
cos (n 2 t)dt - 2
T
T
cos (n 2 t)dt
T
T
2
- 2 T sin n2 t
T n2
T
T
T
2
=0
(Remember that n is an integer and sin (n2) = 0.)

T
2
bn = 2
T
V(t)sin (n t)dt = 2
T
bn = 2 T -cos n2 t
T n2
T
sin (n 2 t)dt - 2
T
T
T
2
0
T
2
sin (n 2 t)dt
T
+ 2 T cos n2 t
T n2
T
T
T
2
bn = 1 -cos n + 1 + 1 cos n2 - cos n

n
n
17
bn = 0 for n = 2, 4, 6, ... and bn = 4 for n = 1, 3, 5, ...

n
Therefore, substituting these constants into the Fourier Series expression, we have:
V(t) =
n = 1, 3, 5, ...
4 sin (2 nfot)
n
V(t) = 4 sin (2 fot) + 1 sin (6 fot) + 1 sin (10 fot) + 1 sin (14 fot) + 1 sin (18 fot) + ...
3
5
7
9
The relative amplitudes of the harmonic (multiples of fo) frequency components [V(t)/(4/)] are:
Frequency
fo
3fo
5fo
7fo
9fo
Amplitude
1.00
0.33
0.20
0.14
0.11
18
Notes Concerning the Operation of the HP Signal Generators

1. The controls on the HP signal generators in the laboratory are quite intuitive and should
present only a minor challenge to you as you learn to operate them. Always remember to
press the green signal button in the lower right corner of the front panel of the generator
so that its associated green LED is on. Otherwise, you will not get a signal output from
the front panel cable connector!
2. These generators have a nominal 50 output impedance over all frequencies of
operation. They are designed to be used with a matched load of 50 , as is usually
presented when they are attached directly to other pieces of HP instrumentation. Since
you will generally be using these generators with very high impedance loads during your
laboratory exercise, you should use a 50 feedthru adapter to connect your test cable.
Only then will the digital output voltage indicated on the generators display closely
match the actual voltage output of the generator. Since these feedthru adapters are quite
expensive and easily disappear from the lab, they are kept locked up in RVR-5017A
except during scheduled lab hours for the course.
3. If you use the signal generators during open time in the lab, you will not have a
feedthru adapter to use. When connected to a high impedance load without the adapter,
the generator display will read one half the actual voltage output of the generator. For
example, lets say you want to output a sine wave of 5 volts p-p (peak-to-peak) amplitude
without using the feedthru adapter. You will need to set the generator controls to display
a 2.5 volts p-p sine wave one half of the actual (desired) generator output voltage under
this condition. If you were using the feedthru adapter, you would simply set the
generator controls to display the desired 5 volts p-p sine wave.
4. The maximum output voltage of the generator cannot exceed a value of 5 V with a
feedthru adapter ( 10 V without the adapter). This limitation needs to be considered
when you are setting up the generator to deliver a specified output voltage. Suppose you
want to generate an 18 V p-p amplitude sine wave with 0 V dc offset. If you connect
using a feedthru adapter, you wont be able to generate anything greater than a 10 V p-p
amplitude sine wave. Therefore, you must connect without the feedthu adapter and set
the generator to display a 9 V p-p amplitude sine wave. As another example, suppose
you want to generate an 8 V p-p amplitude sine wave with a 5 V dc offset. Notice that
you are asking for a maximum +13 volts from the generator at the positive peak of the
sine wave, and there is no way this generator can accomplish that!
5. Think carefully about generator voltage set up and youll avoid significant frustration! If
you are confused about how to produce a particular generator voltage, ask your instructor
for help.
19
Laboratory 3 Exploration of Diode Characteristics

Objective: To explore the characteristics of signal and Zener diodes through the use of
mathematical modeling, protoboard circuit testing, and PSpice simulation. Upon completion of
this laboratory exercise, you should have a good understanding of the electrical characteristics
and the parameters affecting the design of semiconductor junction diodes.
Part I -- Mathematical Models of Forward and Reverse Bias Diodes
1. Open LabVIEW and navigate to open the EEE102L Lab_3 folder. Inside you will find
three VIs necessary for this part of the lab: Diode Current Analyzer.vi, Diode Graph.vi,
and Diode Junction Analyzer.vi.
2. Open the Diode Current Analyzer.vi. Examine its front panel, wiring diagram, and
documentation. Note that the following symbols are used for the diode equation
quantities:
ID is the diode current; VD is the diode voltage; T is absolute temperature; VT is the
thermal voltage at temperature T; Is is diode reverse saturation current at temperature T;
Isref is diode reverse saturation current at a specified temperature Tref; RD is the
effective DC diode resistance at the operating point, and n is the nonideality factor. Note
that this diode equation model has been accurately corrected for changes in Is due to
changes in temperature.
3. A set of default input parameters is present at startup. Notice that Isref is 1e-13 A for this
diode at "room" temperature (290 K). n will be equal to 1.0 except when we consider
exceptionally high diode current conditions in this exercise. Use the model to complete
the following data table for this "default conditions" diode:
VD
ID
.1V
.2V
.3V
.4V
.44V
.46V
.48V
.50V
.52V
.54V
VD
ID
.56V
.58V
.60V
.62V
.64V
.70V
.75V
.80V
.85V
.9V
4. Open Diode Graph.vi. and examine its panel, diagram and documentation. Plot the data
in part 3 above for the forward-bias VD vs. ID characteristic of your default diode on the
semi-log graph of this VI. From your graph, use the chart measurement cursors to
estimate the change in VD (VD) per decade change (x10 change) in ID at VD = 0.7 V.
(Hint: Use the editing tool [arrow] to change the low and high limits on your graph
axes in order to magnify the measurement region of the graph for better measurement
precision.) Compare your value with the prediction of example 3.4 in your EEE 102
class text.
20
5. Close Diode Graph.vi and return to Diode Current Analyzer.vi. Note the diode current at
VD = 0.6 V and room temperature. Increase the operating temperature (T) by 25 C.
Adjust the value of VD by trial-and-error until you achieve the same (to 3 significant
figures) diode current. Note this value of VD. Now decrease the operating temperature
by 25 C from room temperature and again determine the VD required to produce this
same diode current. Calculate VD/T using the data from the two temperature
extremes above. Now calculate dVD/dT for this diode at VD = 0.6 V from equation 3.15
in your text. How do these two calculations compare?
6. Notice that diode current at VD = 0.9V is quite high. Suppose the non-ideality factor n =
1.1 under that condition. What ID does the model predict? What does your text say
about the value of n at high current? What can you conclude about the accuracy of the
diode model predictions at high current if n is not precisely known?
7. Now use this VI model to "design" a diode which, when operating at 30 C, will have an
ID = 15 mA at a VD = 0.6 V. This means determining the reference specification of
saturation current (Isref) for this diode design at room temperature (Tref). (Hint: Use a
trial-and-error method with the VI model here.)
8. Close the Diode Current Analyzer.vi and open the Diode Junction Analyzer.vi. Examine
its front panel, wiring diagram, and documentation. Note that the following symbols are
used for the junction equation quantities:
A is the crossectional area of the diode junction; NA is electron acceptor concentration;
ND is electron donor concentration; T is absolute temperature; VR is reverse bias voltage
across the junction, VT is the thermal voltage at temperature T; Emax is the maximum
electric field intensity across the junction; j is the junction barrier voltage; wd is the
width of the space charge or depletion zone, and Cj is the junction capacitance.
9. The default parameters represent the characteristics of a moderately doped signal diode
under conditions of zero volts of reverse bias voltage (VR). Apply increasing amounts of
reverse bias voltage (increase VR) until you just achieve dielectric (avalanche)
breakdown in this diode. (Hint: Remember that the electric field strength Emax at
which silicon breaks down is 300,000 V/cm.) What value of VR is barely sufficient to
cause breakdown? What happens to the width of the depletion zone as reverse bias
voltage is increased? What happens to the breakdown voltage if the temperature (T) is
increased to 25 C?
10. Use the model to design a Zener diode. At an operating temperature of 25 C, it should
have a reverse bias voltage of 4.7 V at breakdown. Do this by trial-and-error variation of
the diode design parameters, A, NA, and ND. (Check the relevant equations in your text
and in the VI's documentation!) Recall that Zener diodes are characterized by high
doping levels; however do not exceed a maximum doping level of 1E20/cm3. In addition,
design your diode to have a junction capacitance of 12.0 pF at this temperature and
breakdown voltage. Report your final design values for the three diode parameters.
21
Part II PSpice Analysis of Simple Diode Circuits

1. Use sections 3C and 4.B of the Herniter text as a guide to examine the characteristics of
both signal and Zener diodes using PSpice simulation. Complete sections 3C (skip
Exercise 3-5) and 4.B (include Exercises 4.2 and 4.3). Use a D1N914 diode (because
there is one in your parts kit which you will be using in Part III) in place of the D1N5401
diode specified in the text for the 4B circuit. Take pictures of the schematics and probe
graph windows to document your results here.
Part III Prototype Diode Circuit Construction and Testing
1. Using the Fluke RTD Thermometer in the Lab, measure the room temperature in C.
Select a 1 k resistor from your parts kit and measure its actual resistance to 3 significant
digits using a bench ohmmeter. On your protoboard, construct the circuit shown in the
section 3.C of the Herniter text. Use a 1N914 (or equivalent) signal diode from your
parts kit. Use the HP signal generator for the DC voltage source. Make sure you attach
a 50 feed-through connector to the output of the generator. (Remember that this is
necessary to match the actual generator voltage output with its digital display.) Begin
with a setting of 0 V DC Offset.
2. Open LabVIEW and navigate once again to the folder EEE102L Lab_ 3. This time open
the Filtered DC/AC Voltmeter.vi. Examine the front panel, wiring diagram, and
documentation to become familiar with this VI. Connect the channel 0 (+ and -) input
leads of your VI workstation to measure voltage across the resistor in your circuit. Set
the DC/AC switch on the VI front panel to DC and RUN the VI. Now set the HP
generator Offset voltage so that the voltage you measure across the resistor is 1.00 V DC.
Record the generator source voltage (V1) and then measure the diode voltage (Vd).
Return the generator Offset voltage to 0 V and reverse the voltage polarity of the
generator in your circuit. Now set the generator voltage (V1) to 1.00 V. Again, measure
Vd and then the voltage across the resistor.
3. How do the diode voltage and current measured under each of the two conditions in part
2 above compare with what you would predict from your PSpice simulation in Part II.
Can you explain any differences between measurement and PSpice prediction?
4. Now set the HP generator to deliver a sine wave of 10 Hz frequency and 2 V p-p
amplitude. Switch your VI to AC measurement (p-p) and measure the generator voltage
(V1). Now measure Vd. When you are satisfied with your measurement stability of Vd,
press the stop button on the VI front panel and take a "picture" of the panel window to
document your result. Explain the characteristics of the waveform you observe on the
Voltage Stability/Waveform Monitor, in terms of the voltage vs. current characteristic of
the diode.
5. Construct the circuit shown in Exercise 4-3 (p. 206) of the Herniter text on your
protoboard. Use the 1N4734A Zener diode from your parts kit in this circuit. Replace
22
the DC voltage source shown in that circuit with your HP generator. Adjust generator
voltage (V1) to 18 V p-p at 10 Hz and then use the VI to measure Vz. (Note: To
achieve 18 V p-p output, you must remove the feed thru adapter from the output of
the generator and adjust Amplitude to 9 V p-p on the digital display. With no feed
thru adapter connected, the actual output voltage of the HP generator is twice the
value of its digital readout.) When you are satisfied with your measurement stability of
Vz, press the stop button on the VI front panel and take a picture of the panel window to
document your result. Explain the characteristics of the waveform you observe on the
Voltage Stability/Waveform Monitor in terms of the voltage vs. current characteristic of
the Zener diode.
Note that you have two weeks to do this laboratory exercise and prepare the formal report.
Check the (R) date on your course outline.
23
Laboratory 4 Diode Circuits

Objectives: 1) To compare the characteristics of a half-wave and a full-wave rectified power
supply; 2) to construct and test a full-wave, bridge-rectified, Zener diode-regulated power
supply; 3) to examine the characteristics of a diode wave shaping circuit, and 4) to simulate the
piecewise linear VTC of a diode circuit using PSpice. Upon completion of this laboratory
exercise, you should have a good understanding of the design and function of these basic diode
circuits.
Part I Design, Construction, and Testing of a Half-wave Rectified Power Supply
the VIs necessary for this part of the lab: Rectifier Supply.vi. and Filtered DC/AC
Voltmeter.vi.
2. Open Rectifier Supply.vi. Examine its front panel, wiring diagram, and documentation.
Note that the following symbols are used for the rectifier design equation quantities:
Vrms is the RMS voltage of the sinusoidal source; w is the radian frequency of the
source; CVD is the constant voltage drop across a diode; T is the period of the source
voltage; Vp is the peak amplitude of the source voltage; Vdc is the nominal dc output
voltage of the power supply; R is the load resistance; Idc is the nominal dc output
current of the power supply; Vr is the ripple voltage; PRV is the percent ripple
voltage; C is the capacitance; dT is the diode conduction time; Ip is the peak diode
current; PIV is the diode peak inverse voltage, and PD is the nominal power
dissipation of the diode.
3. A set of zero default input parameters is present at startup. Notice that the operating
frequency is defaulted to 60 Hz for obvious reasons. Use this design VI to determine the
necessary components for a half-wave rectified power supply, operating with a 17.8
V(rms) source voltage, required to produce a dc output current of 10 mA with a percent
output voltage ripple of 4.3%. Take a picture of the front panel of your VI to document
your results. Compare the components required in this design with those required for a
full-wave rectified power supply design with the same constraints. Explain (using
appropriate equations from circuit theory) the reason for the differences.
4. From your EEE 102L Lab Kit, select components to implement the full-wave rectifier
design shown in Figure 3.67 of your text. Use a W005G bridge rectifier chip. (Appendix
A in your text may be helpful for identifying resistor color band codes.) Your resistor
will be a 1/4 W carbon film type. Does it have an adequate power rating for use in this
application? Justify your answer. Determine (if you can) PIV, Ip and Isc specifications
for the W005G rectifier diode from its data sheet. (See the Data Sheets folder in the
Documents folder under your hard drive icon.) Is this chip adequate for this application?
Justify your answer.
24
5. The transformer that your lab instructor will provide you with for this laboratory exercise
has a nominal secondary output voltage Vs = 16 V (rms). Plugged into our power lines in
the lab, the output voltage is around 17.8 V(rms). You cant measure this with our VI
systems because the voltage amplitude is larger than the full-scale range of our A/D
converter boards ( 10 V). Check and confirm the output voltage (rms) of your
transformer using the hand-held or bench-top voltmeters, which will be available in the
lab. Use the ac measurement setting for rms voltage readings. Go back and change this
value in your Rectifier Supply.vi if necessary.
In order to keep your measurements inside the VI full-scale range, make a voltage divider
out of your calculated load resistor. See below:
Rs
Vp - 2Von
C
10 mA
Vo
RL
Let Rs be 1.5 k. Calculate the required RL so that the sum of the two resistors is equal
to the value specified in your design VI.
Also, after your circuit is constructed and working, it will be a good idea to use your VI
voltmeter to measure the Von of one of the diodes in your bridge rectifier chip. If it isnt
the value indicated for default in the design VI, consider that fact in your theoretical
calculation of what you should expect for output voltage here
6. Using Figure 3.67 in your text as a guide, wire your circuit on your protoboard using the
step-down transformer provided. When you are satisfied with your wiring job, open
Filtered DC/AC Voltmeter.vi and proceed to make the following measurements. Note:
You must connect the white ground wire from the green connector block to an
appropriate location on your circuit to provide a reference ground for your
measurements. Unlike the HP signal generator, the transformer secondary is
entirely isolated from ground, so you have no earth ground reference in this circuit
unless you connect the white wire.
7. Connect the channel 0 input lead wires of your VI to measure the output voltage (Vo)
across the RL resistor in your circuit.
8. Now switch your VI to AC (p-p) and measure the output voltage waveform. When you
are satisfied with your signal, press the Stop button on the VI front panel to freeze your
measurement. Use the VIs chart cursors to measure Vdc, Vr, and dT on the Voltage
25
Stability/Waveform Monitor. Take a picture of your front panel for documentation of

your results.
9. Calculate Idc and PRV for your circuit and compare these, and the three measured values
from 8 above, with their predicted values from part 3 above. Can you offer explanations
for any differences between these measured/calculated values and the design values?
10. Now find the 1N4734A Zener diode in your parts kit and figure out how to add it to your
circuit to clamp the voltage across the load resistor to 5.6 V and to significantly reduce
the ripple. Measure Vdc again using the Filtered DC/AC Voltmeter.vi (AC p-p setting)
and take a picture of the Voltage Stability/Waveform Monitor to document your results.
Part II DC Restoring Circuit Evaluation
1. On your protoboard, construct the positive dc restoring circuit diagramed in figure 3.78b
in your Jaeger class text. Again, use the HP signal generator for the voltage source in the
diagram. Select a 1 F metalized polymer film capacitor and a 1N914 switching diode
from your parts kit. When you are satisfied with your wiring job, set the generator to
deliver a 100 Hz triangle wave of 8 V p-p output and zero V dc offset. Record the
generator output voltage using Filtered DC/AC Voltmeter.vi. Push the Stop button on the
VI and take a picture of the front panel to document this input signal.
2. Now measure Vo across the diode. When you are satisfied with the signal, push the Stop
button on the VI and use cursors to measure the maximum and minimum peak voltages.
Compare your measurements to the predictions of Figure 3.79b in your text. Can you
explain any differences between your measurements and the predictions of that figure?
Take a picture of the VI front panel to document your results.
Part III PSpice Simulation of the Piecewise Linear Voltage Transfer Characteristic of a
Diode Circuit. (May be done in the lab or at home on your own workstation.)
1. Open PSpice Capture and construct the circuit shown in Figure 3.119 on page 174 in your
Jaeger text. Use a 1N914 signal diode from your parts kit for each of the three identical
diodes in this circuit. Setup a Simulation to run a DC Sweep on Vs between 15 and +15
volts. Run the simulation and display a plot of Vo versus Vs in the Probe window. Save
a Probe window picture file to include in your report.
2. Measure the key break points and slopes in the PSpice-simulated VTC for this circuit and
compare them with the corresponding ideal diode model predictions illustrated in
problem 3.140, which was done as an example in class. Identify and explain the
differences.
Note that a formal laboratory report on this lab should be included with the report of Lab
3. Both reports are due on the lab day specified in the course outline.
26
Laboratory 5 MOSFET Transistor Characteristics

Objectives: 1) To examine the characteristics of a MOSFET transistor by means of a
mathematical VI model; 2) to design a single-supply dc biasing circuit for operation of an
NMOS device in the saturation region, and 3) to simulate a CMOS inverter circuit using PSpice.
Upon completion of this laboratory exercise, you should have a good understanding of MOSFET
transistor characteristics and the dc biasing of such devices.
Part I Examining the Electrical Characteristics of MOSFET Transistors
1. Open LabVIEW and navigate to open the EEE102_Lab 5 folder. Inside you will find the VIs
necessary for this part of the lab:
NMOSFET.vi, NMOSFETAnalMeas4.vi,
NMOSFETBias3.vi, NMOSFET_LL2.vi and Filtered DC/AC Voltmeter.vi.
2. Open NMOSFET.vi. Examine its front panel, wiring diagram, and documentation. Note that
the following symbols are used for the NMOS transistor model parameters:
Kn is the transconductance parameter; W/L is the channel aspect ratio; is the channel
length modulation parameter; VT0 is the standard threshold voltage with a grounded
body; is the body effect parameter; VGS is the gate-source voltage; VSB is the sourcebody voltage; 2f is the surface potential parameter; VDS is the drain-source voltage, and
IDS is the drain-source current. The pinchoff point is defined as the Q point drainsource voltage where VDS = (VGS-VTN).
3. A set of default input parameters is present at startup. This parameter set is constructed
based upon data used for NMOS device problems in Chapter 4 of your Jaeger class text.
Explore how these parameters affect the IDS vs. VDS characteristic of the NMOS transistor
using the following protocol. In each case, start with the default parameter set (Use the
Reinitialize All to Default command under the Operate menu) and change only the parameter
indicated by the protocol. Describe any significant changes to the cutoff, linear or triode
region, pinchoff point, and/or saturation region of the characteristic. It is not necessary to
take pictures of the front panel results for each case. Your description of the changes you
observe will be sufficient for your report.
3
4
5
6
7
8
9
10
Increase Kn by a factor of 10
Increase W/L by a factor of 10
Increase by a factor of 10
Increase VT0 to 4 volts
Decrease VT0 to 2 volts
Increase VGS to 6 volts
Decrease VGS to 0.5 volts
Increase VSB to 5 volts
4. Pre-lab Work -- Refer to the data sheet for the Motorola MC14007UB IC. (Use Adobe
Acrobat Reader under the Apple menu. Clicking on File/Open should take you to the Data
27
Sheets folder on your workstation.) Figure 3 (attached at the end of this lab for easy
reference) in the data sheet for the MC14007UB gives typical IDS vs. VDS characteristics
for the transistors on the chip. Notice that these characteristics vary with temperature over
the rated operating range of the chip. Use the characteristic for VGS = 5 V and TA = 25 C.
Estimate the values of Kn = Kn(W/L) and VT0 = VTN for VSB = 0, for the NMOS devices
on the chip. Consider using the pinchoff point where VDS = (VGS-VTN) and the saturation
region where IDS = (Kn/2)(VGS-VTN)2 to calculate the two parameter values. Notice that
is very small for these devices and may be approximated as = 0 for our estimation
purposes.
5. Open NMOSFETAnalMeas4.vi; examine its front panel, wiring diagram and documentation.
Notice that this VI allows you to use a test circuit to directly measure the Kn, VT0, and
parameters of your chosen transistor. Pick one of the NMOS devices on the IC and use the
diagram on the lower portion of the front panel of the VI to design a test circuit (as shown on
the VI front panel) for that chosen device on your protoboard. You will use the bench power
supplies and the HP generator for the necessary voltage sources. Leave all gate pins on the
unused devices of the IC in an open circuit condition. (Do NOT connect pin 14 to your VDD
source or pin 7 to your VSS source, as indicated in the Schematic Figure. Such a connection
is NOT appropriate for single transistor operation here, and will adversely affect your circuit
operation.) Make sure (if necessary for your transistor choice) to wire a "jumper" between
the Base and the Source of the transistor to set VSB = 0 V. Follow the documentation for
this VI, which is conveniently listed with the front panel figure in the appendix of this lab
manual, to measure Kn, VT0 and for your transistor. Take a picture of your front panel as
documentation for your report once you are satisfied with your measurements. Note that this
VI uses three simultaneous input channels to obtain necessary circuit voltages. It also uses a
white wire to identify system ground for the differential voltage measurements. How do
your measured values for Kn, VT0 and compare with the ones calculated in part 4 above?
Which set of values will you choose to rely upon for Part II? Why?
Part II Single Supply DC Biasing Circuit Design and Prototype Construction
1. Open NMOSFETBias3.vi; examine its front panel, wiring diagram and documentation. This
VI uses the example 4-R bias circuit design done in class as a guide. Assume W/L=10 for
your transistor and your best estimates for VT0, Kn and from Part I above. Determine
values of R1, R2, RD, and RS for a four-resistor biasing network for the selected NMOS
device on your MC14007UB IC. Design for a Q point (VDS, IDS) of (3.5 V, 5 mA) in the
saturation region of the device. (Adjust the "Gate Margin" parameter to give you 5% resistor
values close to those available in your parts kit.) Make sure your Q point will be in the
saturation region of the device [VDS > (VGS-VTN) > 0]. Use 12 V as your VDD supply
voltage.
2. Now open NMOSFET_LL2.vi and examine its front panel, wiring diagram and
documentation. Notice that this VI will plot the characteristic of your device as well as the
load line equation for your biasing circuit. It will also determine the Q point (Q-VDS, QIDS) for your device. Enter YOUR device and circuit design data (not the default values).
(N.B. that Kn' is entered in A/V2 in this VI.) Note that you will have to choose available 5%
28
tolerance resistor values for your simulation here; however, you may choose to make modest
"trial-and-error" adjustments to your resistor choices in order to achieve a better match to
your design Q point. When you are satisfied with your result, take a picture of the front
panel of this VI for documentation.
3. On your protoboard, mount the MC14007UB IC and wire the selected NMOS transistor
according to your dc biasing circuit design. Use a 12V power supply for VDD and selected
resistors from your parts kit. When you are satisfied with your circuit wiring, open Filtered
DC/AC Voltmeter.vi. Using DC measurement mode, measure the voltage across drain and
source (VDS), and measure the voltage across RS. Use the later to calculate IDS. How does
your measured Q point compare with your design target? If it isn't close, can you offer an
explanation as to why?
Part III PSpice CMOS Inverter Circuit Simulation.
1. The CMOS transistors on the MC14007UB are typically used to construct digital inverter
circuits. Follow the directions for section 4.D.3 in the Herniter text and perform Exercise 4-7
to create the voltage transfer characteristic (VTC) for a CMOS inverter. Use generic
NMOS/PMOS enhancement mode transistors in your Parts list. Simulate the circuit and
display the voltage transfer characteristic (VTC) in the Probe window. Take a picture of the
probe window results as documentation for your report.
29
30
Laboratory 6 BJT Transistor Characteristics

Objectives: 1) To examine the characteristics of a BJT transistor by means of a mathematical
VI model; 2) to design a single-supply dc biasing circuit for operation of an NPN BJT device in
the forward active region, and 3) to simulate this circuit using PSpice. Upon completion of this
laboratory exercise, you should have a good understanding of BJT transistor characteristics and
the dc biasing of such devices.
Part I Examining the Electrical Characteristics of BJT Transistors
the VIs necessary for this part of the lab: NPNBE.vi, NPNBE_LL.vi, NPNCE.vi,
NPNCE_LL.vi, NPNBFISAnalMeas.vi, and Filtered DC/AC Voltmeter.vi.
2. Open NPNBE.vi. Examine its front panel, wiring diagram and documentation. Note that
the following symbols are used for the NPN BJT transistor model parameters:
3. IS is saturation current; BF is forward (ce) current gain; BR is reverse (ce) current gain; T
is absolute temperature; VCE is collector-emitter voltage; IB is base current and VBE is
base-emitter voltage.
based upon data used for NPN BJT device problems in Chapter 4 of your text. Explore
how these parameters affect the IB vs. VBE characteristic of the NPN transistor using the
following protocol. In each case, start with the default parameter set and change only the
parameter indicated by the protocol. (Use the Reinitialize All to Default command under
the Operate menu.) Describe any significant changes to the characteristic. It is not
necessary to take pictures of the front panel results for each case. Your description of the
changes you observe will be sufficient for your report.
Increase IS by a factor of 10
Decrease IS by a factor of 10
Increase BF to 200
Decrease BF to 20
Increase BR to 5
Decrease BR to 0.1
Increase VCE to 10 V
Decrease VCE to 0.1 V
Increase T by 30 C
Decrease T by 30 C
5. Open NPNCE.vi. Examine its front panel, wiring diagram and documentation. Note that
the same symbols are used for the NPN BJT transistor model parameters as were used in
NPNBE.vi.
31
based upon data used for NPN BJT device problems in Chapter 4 of your text. Explore
how these parameters affect the IC vs. VCE characteristic of the NPN transistor using the
following protocol. In each case, start with the default parameter set and change only the
parameter indicated by the protocol. Describe any significant changes to the
characteristic. It is not necessary to take pictures of the front panel results for each case.
Your description of the changes you observe will be sufficient for your report.
Increase IS by a factor of 10
Decrease IS by a factor of 10
Increase BF to 200
Decrease BF to 20
Increase BR to 5
Decrease BR to 0.1
Increase IB by a factor of 10
Decrease IB by a factor of 10
Increase T by 30 C
Decrease T by 30 C
7. Refer to your data sheet on the Motorola 2N2222A NPN BJT transistor. Figure 3
(attached at the end of this lab for easy reference) in the data sheet gives typical hFE vs.
iC characteristics for the transistor. As usual, some different notation is used in the data
sheet for the transistor parameters. Here hFE = F in our textbook notation. Notice that
these characteristics vary with temperature over the rated range of the collector current.
Use the characteristic for T = 25 C in your design work. Estimate the value of F for
this transistor for a bias operating Q-point (VCE, IC) = (3.5V, 5 mA). Because we
usually buy cheap grades of these transistors for the parts kits, you may find F to be as
low as 50% of the nominal value found in figure 3. Since it is not very significant in
forward active region operation of the transistor, you may assume R = 1. Use
NPNBFISAnalMeas.vi to measure the F and IS values for your transistor under the
specified bias conditions. (Be sure to read the Documentation window before you begin.)
Use the previous two VIs, with these measured BF and IS values, to plot the expected IB
vs. VBE and IC vs. VCE characteristics for this transistor. What value would you
estimate to be appropriate to use for VBE in your bias circuit design?
Part II Single Supply DC Biasing Circuit Design and Prototype Construction
1. Use problem 5.87 and Figure 5.39 in your Jaeger text as a design guide. (Note that
problem 5.87 was done as an example for you in class.) Open NPNBias.vi and read its
documentation window. Use it to determine values of R1, R2, RC, and RE for a fourresistor biasing network for the 2N2222A. Design for a Q point (VCE, IC) of (3.5 V, 5
mA) in the forward active region of the device. Use 12 V for VCC. Leave C-E Vdrops = 2,
but adjust the Base Margin to yield acceptable resistor values. You will have to choose
the nearest 5% resistor values in your parts kit for your actual circuit design. Choose
these now, and use their values in the following circuit verification VIs.
32
2. Open NPNBE_LL.vi and examine its front panel, wiring diagram, and documentation.
Notice that this VI will plot the IB vs. VBE characteristic of your device as well as the
base-emitter sub-circuit load line equation for your biasing circuit. It will also determine
the Q point (Q-VBE, Q-IB) for your device. Enter your device and circuit design
parameters and RUN the VI to examine your Q point. Is it what you expected for FAR
operation of the transistor? Note the Q point value of IB because you will need it for
input in the next design verification VI. Close NPNBE_LL.vi and open NPNCE_LL.vi.
Again, examine front panel, wiring diagram and Documentation. This VI will plot the IC
vs. VCE characteristic of your device, as well as the collector-emitter sub-circuit load
line equation for your biasing circuit. Together, they determine the Q point (Q-VCE, QIC) for your device. Enter your device and circuit design parameters and RUN the VI to
verify your Q point design. You may choose to make slight adjustments to your resistor
values (5% values) to achieve a better match to your design Q point. Take pictures of the
front panels of these two design verification VIs to document your final result.
3. On your protoboard, mount the 2N2222A transistor from your parts kit and wire it
according to your dc biasing circuit design. Use a 12 V power supply as your protoboard
VCC supply voltage.
4. When you are satisfied with your circuit wiring, open Filtered DC/AC Voltmeter.vi.
Using DC measurement mode, measure the voltage across collector and emitter (VCE),
and measure the voltage across RC. Use the later to calculate IC. How does your
measured Q point compare with your design target? If its not too close, measure VBE.
Is it what you expected for your design?
Part III PSpice Single Supply DC Biasing Circuit Simulation.
1. Open PSpice Capture and construct the schematic of your 2N2222A transistor biasing
circuit. Simulate the circuit and display VBE, VCE, and IC to confirm the Q point. Take
a picture of the schematic with the I and V data displayed as documentation of your
results.
Note that a formal laboratory report on this lab should be included with the one for Lab 5.
E
B
33
2N2222A NPN Bipolar Junction Transistor Forward (ce) Current Gain as a function of
Collector Current
34
Laboratory 7 Common-Emitter Amplifier Design

Objectives: 1) To design a high voltage gain, common-emitter amplifier using an NPN BJT
transistor and a single-supply dc biasing circuit, 2) to construct a prototype of the design and test
it for ac voltage gain, and 3) to simulate this circuit using PSpice. Upon completion of this
laboratory exercise, you should have a good understanding of common-emitter amplifier design
and requirements for the dc biasing of such circuits.
Part I Circuit Design and Verification Using LabVIEW
1. Design a common-emitter amplifier that will employ a 2N2222A NPN BJT as the active
device. Your amplifier should have an ac voltage gain (|AV| 100) at a frequency (f =
100 Hz) with load resistance R3 = 100 K. Your design will employ an ac voltage
source (vs) with RS = 15 . Your circuit design should use appropriate available
coupling capacitors (C1, C2, and C3) and appropriate dc biasing resistors (R1, R2, and RC,
RE) from your parts kit. Use a 12V power supply as your VCC supply voltage. Note that
you will have to determine appropriate dc bias values of VCE and IC for your amplifier.
What factors must you consider in determining them?
2. On your VI workstation, open LabVIEW and navigate to the EEE102L Lab_7 folder.
Inside are all the VIs you will need for this laboratory. Open NPNCEBias.vi. Although
you have seen this VI before in Lab 6, examine its front panel, wiring diagram, and
documentation once again, if necessary. Note that the ac model parameters for the
transistor are added as a calculation to this bias circuit designer. and IS should be set to
simulate what you have measured in Lab 6 for your 2N2222A transistor. Enter the
absolute temperature (T) of the room (check the Fluke RTD by the door to RVR-5017A),
power supply voltage (VCC) and your desired dc bias values for VCE and IC. RUN the
VI to calculate your dc bias circuit design values. You may adjust C-E Vdrops and Base
Margin to yield reasonable 5% resistor values.
3. Close NPNCEBias.vi and open both NPNBE_LL.vi and NPNCE_LL.vi. You have also
seen these VIs before in Lab 6. Examine the documentation window again, if necessary.
Use these VIs to enter the 5% resistor design values for your dc biasing circuit, and RUN
the VIs to verify the dc Q points of your design. Take pictures of the front panels of
these VIs to document your results.
4. Close these two VIs and open CEAmpAnal.vi. This one you have not seen before.
Examine its front panel, wiring diagram, and documentation window to learn about its
functions and operation. The following circuit design parameters are required as inputs
for this VI:
Rs is the equivalent voltage source resistance
Vsp is the peak input source voltage
C1, C2, and C3 are the ac coupling and by-pass capacitors
Frequency is the frequency of the input signal in Hz
R1, R2, R3, and Rc are the relevant bias circuit and ac load resistances
35
r , gm, and ro are the respective small-signal ac input resistance,

transconductance, and output resistance of the transistor at the design Q-point.
5. Enter the appropriate input parameters for your common-emitter amplifier circuit design.
Consider the size of the coupling and bypass capacitors that you will need. Note that
peak input signal amplitude (Vsp) will be 5 mV. RUN the VI to calculate the expected
peak ac output voltage (Vop) and ac voltage gain (Av). Notice that a representation of
the expected ac output voltage is displayed on the VI waveform graph. If your gain is not
sufficient, consider redesigning the circuit with a different value of IC. When you are
satisfied with your design and its verification by the LabVIEW VIs, construct the circuit
on your protoboard.
Part II Common-Emitter Amplifier Prototype Construction and Testing
1. On your protoboard, mount the 2N2222A transistor and wire the transistor and
appropriate passive components according to your common-emitter amplifier circuit
design. Using a signal generator set to deliver a 20 V p-p sinusoidal output signal at a
frequency of 100 Hz, construct the resistive voltage divider circuit shown in Figure 1. It
will deliver a Thevenin equivalent sinusoidal voltage (vs) of approximately 5 mV peak
amplitude to C1 through an equivalent source resistance (RS) of 15 .
2. When you are satisfied with your circuit wiring, open Filtered DC/AC Voltmeter.vi.
Using AC measurement mode, RUN the VI, measure the voltage (vo(t)) across load
resistor R3, and calculate the ac voltage gain (AV). How do these two compare with your
design values? Take a picture of the front panel of this VI to document your results.
Part III PSpice Common-Emitter Amplifier Simulation.
1. Open PSpice Capture and construct your 2N2222 transistor common-emitter amplifier
circuit and voltage divider source. Refer to sections 3.E., Transistor Bias Point Detail,
and review Ch 2, Introduction to Probe. Simulate the amplifier circuit and use Probe to
display vo(t). Prepare pictures of your Schematic and Probe results to include in your lab
report as documentation of your simulation.
R=30 K
R=15
vss =10sin(2ft) V
-
+
vs =0.005sin(2ft) V
-
Figure 1. Signal Generator Voltage Divider Circuit
36
Laboratory 8 OP Amp Instrumentation Amplifiers and First Order Filters

Objectives: 1) To design a high voltage gain instrumentation amplifier using the Burr Brown
INA118 IC and to design a cascaded first order bandpass filter using two LM741 operational
amplifiers; 2) to construct a prototype of the design and test it for overall ac voltage gain and
CMRR, and examine its I/O impedance, and 3) to simulate this circuit using PSpice. Upon
completion of this laboratory exercise, you should have a good understanding of instrumentation
amplifier/filter design and the electrical characteristics of such circuits.
Pre-laboratory preparation: Inspect the data sheet for the Burr Brown INA118 in the EEE
102L Data Sheets folder on your workstation. Note particularly the circuit design of the IC and
how its differential gain is determined by selection of a single external circuit component. This
pdf file may be copied to a storage device and printed outside of the lab if you desire. Compare
its circuit with the example in figure 11.12 in your text. Similarly, review the data sheet for the
LM741 Op Amp in the Data Sheets folder on the workstation. Note that you will need two 9 V
alkaline batteries with battery clips to construct 9 V power supplies to power your circuits in
this laboratory.
Part I Circuit Design and Verification Using LabVIEW
1. Determine appropriate external components for use with the INA118 to achieve an
instrumentation amplifier with differential voltage gain of 1000 at a frequency of 100 Hz.
Amplifier/Bandpass Filter Block Diagram
GEN
V DIV
INA
118
741
VO
741
2. Consider the Low-Pass Filter description in section 11.3.7 in the Jaeger text, along with
design information presented in class, and determine appropriate external components for
use with a LM741 op amp to construct a high-pass first order filter with a -3db cutoff
frequency of 10 Hz and a voltage gain of 1 in the "high-pass" frequency region.
3. Similarly, determine appropriate external components for use with a second LM741 op
amp to construct a low-pass first order filter with a -3dB cutoff frequency of 1000 Hz and
a voltage gain of 1 in the 'low-pass" frequency region. Remember that these circuits will
be using components from your parts kit, so choose available R and C values for your
designs that will achieve the desired specifications.
4. Open LabVIEW on your workstation and navigate to Amp/Filter.vi in the EEE102L
Lab_8 folder. Open this VI, read its documentation, and enter the data required for this
37
VI to verify your design values at a frequency of 100 Hz. RUN the VI and compare both
peak output voltage and gain to your predicted design values. Repeat this for frequencies
of 10 Hz and 1000 Hz. If your design checks out ok, take pictures of the front panel for
each of the 3 frequencies as documentation for your report and proceed to Part II below.
If it doesn't check out, go back and re-analyze your design.
Part II Instrumentation Amplifier/Bandpass Filter Prototype Construction and Testing
1. At one end of your protoboard, mount the INA118 and wire it according to your design.
Make sure both battery power supplies are connected as required. Using a signal
generator set to deliver a 20 V p-p sinusoidal output signal at a frequency of 100 Hz,
construct the resistive voltage divider circuit shown in Figure 1 below. It should deliver a
Thevenin equivalent sinusoidal voltage (vs) of approximately 5 mV peak amplitude
through an equivalent source resistance (RS) of 15 to the differential input pins of the
INA118. Note that this circuit is slightly different from the one used in the previous
laboratory in that the voltage (vs) is not referenced directly to "ground". Make sure you
have a common reference ground in your circuit. The ground side of the HP generator,
pin 5 (ref) of the INA118, and the ground terminal of your battery supplies, must all be
connected together (common ground).
2. When you are satisfied with your wiring, connect the instrumentation amplifier inputs
across the 15 resistor of the voltage divider. Open Filtered DC/AC Voltmeter.vi.
Using AC measurement mode, RUN the VI and measure the voltage at the output pin of
the IC. Calculate the ac voltage gain (AV). How does it compare with your design value?
Take a picture of the front panel of this VI to document your results.
3. Because this instrumentation amplifier has such a high differential input impedance, it is
almost impossible to measure it using general-purpose test instruments such as we have
in the laboratory. In order to get an impression for how large this input impedance really
is, insert a 51 K resistor from your parts kit in series with the + input of the
instrumentation amplifier. Again, measure the voltage at the output pin of the IC. Does
the 51 K resistor make any difference? Consider the high input impedance of the
INA118 circuit design and explain why.
4. Remove the 51 k resistor and reconnect the + input of the instrumentation amplifier
directly to the voltage divider. Now place a 2.2 K resistor between the output pin of the
IC and ground (output load resistor). Measure the voltage across the resistor and
compare it to the "open circuit" output voltage. Is there a difference? Try this again with
a 1 K resistor. If there is still no difference, try a 510 resistor. What do these
measurements indicate about the output current limit for your IC? What is the minimum
load impedance you should design for if you expect to achieve the desired 10 V peak-topeak output voltage swing?
5. Remove the load resistor. Disconnect the signal generator from the voltage divider and
connect BOTH the + and - inputs of the instrumentation amplifier directly to the + output
terminal of the signal generator to produce a common mode input signal. Set the
38
generator to produce a 5 V p-p sine wave. Again, measure the voltage at the output pin
of the IC. (Note you may have to edit the voltage scale after recording in order to
magnify the signal and measure the small common mode output voltage. Ignore any
"spike" noise that may be present and measure (estimate) the p-p amplitude of the 100 Hz
sinusoidal signal.) Determine the common mode gain for your amplifier. Calculate the
common mode rejection ratio in decibels (CMRR in dB). When you are finished, return
your input connections to the voltage divider as before, and reset your signal generator
amplitude to 20 V p-p.
6. Next to the INA118 on your protoboard, mount one LM741 op amp and wire it according
to your high-pass filter design. Connect the filter input to the instrumentation amplifier
output, and use the Filtered DC/AC Voltmeter.vi to measure the filter output voltage.
How does it compare to the instrumentation amplifier output voltage measured in part 2
above? Now change the signal generator frequency to 10 Hz and measure the filter
output voltage again. Is the amplitude of the output voltage reduced by -3dB (a factor of
.707) at this frequency as predicted by your design? Explain.
7. Right next to the high-pass filter mount another LM741 op amp and wire it according to
your low-pass filter design. Measure the output voltage of the low-pass filter at 100 Hz.
Is it what you expected? Change the signal generator to a frequency of 1000 Hz and
measure the low-pass filter output voltage. Is the amplitude reduced by -3dB at this
frequency as predicted by your design? Explain. Measure the output voltage of your
low-pass filter at 100 Hz. Nominally, it should be 5 V peak. Is it greater or less than you
expected? What instrumentation amplifier and/or filter circuit modifications could you
make to achieve an output voltage closer to this design expectation? For report
documentation, take pictures of the front panel of your VI that show your completed
circuit output at frequencies of 10 Hz, 100 Hz, and 1000 Hz.
Part III PSpice Filter Simulation
1. Open PSpice Capture and construct the bandpass filter section (only) of your circuit using
LM741 op-amps from the parts library. Use a VSIN sine wave voltage source (at 100 Hz
and 5 mV peak amplitude) from the Parts library as input to your filter. Set up a
simulation to examine the circuit using an AC frequency sweep from 5 Hz to 5 kHz. Use
Probe to display the final output voltage vo amplitude as a function of frequency for the
frequency sweep from 5Hz to 5 kHz. Prepare pictures of your Schematic and Probe
windows to include in your lab report as documentation of your results.
39
R=15 K
R=15
vss =10sin(2ft) V
-
+
vs =0.005sin(2ft) V
-
R=15 K
Figure 1. Signal Generator Voltage Divider Circuit

Note that a formal laboratory report on this lab, along with the one for Lab 7, is due on
your lab day in the 16th week (finals week) of the semester.
40
APPENDIX
1. TAKING PICTURES OF THE ACTIVE WINDOW ON
MACINTOSH WORKSTATIONS
2. EEE 102 L VIRTUAL INSTRUMENT DOCUMENTATION
3. NATIONAL INSTRUMENTS 6024E DAQ BOARD I/O PIN
CONNECTIONS
41
Procedure for taking a "Picture" of the active window on

Macintosh workstations
1. Make sure the window is active by executing a single mouse click somewhere inside the
window.
2. Set the caps lock key and press Shift 4 (three keys) simultaneously. The mouse pointer
will change to a camera shutter.
3. Click the mouse in the active window. You will hear the sound of a camera shutter from
your workstation.
4. The "picture" of the window will be found as a document labeled Picture #, where # is
the number of the picture taken. That document will be located inside the hard drive
partition (icon) on the desktop.
5. If the hard drive icon is obscured on your desktop, you can get to the hard drive partition
most easily by executing a mouse click on the program icon in the upper right-hand
corner of the Macintosh menu bar, and selecting Finder. Repeat this mouse click and
select Hide Others from the sub-menu. Then double-click on the hard drive icon that
should now be visible just below the menu bar on the right side of the desktop. You'll
find the Picture # document in the window that opens.
6. These documents are saved on the Macintosh in a .pict format. This format is easily
handled by word processors, and you can usually insert these pictures directly into a word
processing document. Specifically, Microsoft Word can insert these files directly into a
document file using the Insert/Picture/From File command, or simply by dragging the
picture document into the open word document page. Save your desired Word
(preferred) or picture files to your personal storage device or account.
7.
Please remember to drag all picture files into the trash and Empty the trash (find the
Empty Trash command under the Special menu) before you finish your session on the
workstation.
EEE 102L Virtual Instrument Documentation
A/DResCheck2.vi
This is a high precision DC/AC voltmeter that incorporates a forth-order Butterworth antialiasing filter to provide high noise immunity and high measurement precision in DC mode.
Click the RUN (arrow) button to start measuring continuously. Monitor voltage stability using
the monitor graph. Click the STOP button on the VI front panel to stop (red) and hold the data
on the graph for the current sampling period. Click the STOP button again (white) to reset the
VI for the next continuous RUN. (Note: You may take single voltage samples (one sampling
42
period) by clicking RUN with the STOP button depressed (red).) Click and drag the red and blue
cursors on the waveform graph to measure time (X) in seconds and amplitude (Y) in volts.
There are two AC modes of recording: RMS reading and Peak-to-Peak reading that are set by
the AC Mode switch when the AC/DC slide switch is in the AC position.
This VI is configured for measuring National Instruments 6024E board A/D converter amplitude
resolution using a variety of measurement protocols. The Boolean Conversion display records
the binary output (12-bit) of the converter for the measured analog voltage.
Alias3.vi
This VI is designed to illustrate the phenomenon of aliasing using a 100 Hz sine wave signal as
input to channel 0. Click on the RUN button in the menu bar to start the VI. Click on the STOP
button on the front panel (NOT the menu bar) to hold the next record. Click this button to
RESET the VI before you RUN it again.
Waveform 1 is sampled at a fixed rate of fs = 1000 samples/s. You may switch Waveform 2 in
five steps between sampling frequencies of 125 samples/s and 250 samples/s using the Sampling
Frequency switch. LOOK AT BOTH THE SHAPE AND THE APPARENT FREQUENCY OF
THE WAVEFORM 2 SINE WAVES AS COMPARED TO WAVEFORM 1. You can measure
waveform periods using the cursors. Frequency = 1/period. Click and drag the center of a cursor
with the mouse to position it on the waveform graph. X is time in seconds and Y is amplitude in
volts.
GDAnal2.vi
This Conditional Trigger Data Acquisition VI acquires specified data from one or more analog
input channels. A hardware clock is used to control the acquisition rate for fast and accurate
timing. The data is stored in an intermediate memory buffer after it is acquired from the analog
input channels. The VI retrieves the data that matches the trigger condition, displays it and stops
the acquisition.
The VI has been configured to measure Rise Time, Slew Rate, and Delay Time for acquired
logic gate waveforms on two channels, (0 and 1), and to use a Property Node to automatically
position the waveform graph cursors. The 10% and 90% points on the output waveform, and
the 50% points (TI and TO) on both waveforms are displayed for reference.
WavAnal3.vi
This VI allows you to record both time and frequency (amplitude spectrum) domain signals
using channel 0. The digital sampling rate is designed to accommodate a signal with a
fundamental frequency on the order of 100 Hz. Clicking the red STOP button on the front panel
(NOT the menu bar) will hold the data from the next sampling period. Click RESET then RUN
(arrow) to resume continuous recording. Clicking RUN in RESET mode will allow you to
record single records. You can move the cursors by clicking and dragging with the mouse in
order to make detailed measurements of amplitude (Y) in volts in either the time or frequency
domain (X). Pushing the Filter button will cause the signal to be sharply lowpass filtered with a
43
passband from 0 - fc Hz., where the cutoff frequency, fc, is set using the slide switch in
increments of 200 Hz from 0 to 1000 Hz.
Diode Current Analyzer.vi

This VI allows you to simply solve the "diode equation" under a variety of input conditions.
You can easily explore the effect of your input choices on the diode current. Be sure to check
out the wiring Diagram to see how this VI is implemented. Notice that saturation current (Is) has
been corrected for temperature variation to make the calculation of diode current even more
realistic. Use of this VI simply requires a known saturation current (Isref) at a known reference
temperature (Tref) for the diode to be modeled . The effects of temperature (T), non-ideality
factor (n) and diode voltage (VD) on diode current (ID) can be observed. Edit the input data as
required and click on the RUN (arrow) button to operate the VI.
Diode Graph.vi
This VI allows you to create a convenient graph of the forward ID vs. VD characteristic of a
diode. You can use measurement cursors, along with appropriate expansions of the axis scales,
to make desired measurements of this characteristic. The set of diode voltages (VD) specified
for the diode problem in lab 3 have been entered as default values in the graph array. Use the
text tool to enter the corresponding ID array values obtained from the Diode Current Analyzer.vi.
Then RUN the VI to see your graph. You can "zoom" in on a data point on the graph by simply
editing the axis limit values with the text tool. You can perform measurements using the red and
green cursors.
Diode Junction Analyzer.vi

This VI is designed to allow you to explore the diode junction conditions that will produce
"breakdown" under reverse voltage bias. You can change the properties of the diode as input
variables and explore the consequences of those changes on the breakdown voltage, depletion
zone width, and junction capacitance. Be sure to look at the Wiring Diagram to appreciate the
critical formulas that govern these phenomena.
Have fun!
Filtered DC/AC Voltmeter.vi

This is a high precision DC/AC voltmeter that incorporates a forth-order Butterworth antialiasing filter to provide high noise immunity and high measurement precision in DC mode.
Click the RUN button to start measuring continuously. Monitor voltage stability using the
monitor graph. Click the STOP button on the VI front panel to stop (red). Click the STOP
button again (white) to reset the VI for the next continuous RUN. (Note: You may take single 1
second voltage samples by clicking RUN with the STOP button depressed (red).) There are two
AC modes, RMS reading and Peak-to-Peak reading that are set by the AC Mode switch when the
AC/DC switch is in the AC position. Cursors can be dragged to make differential measurements
on the monitor graph.
44
Rectifier Supply.vi
This VI is designed to allow the user to input specified parameters for a simple half wave or full
wave rectified power supply. It then uses a formula node to calculate the required component
parameters for the design after the RUN button is pressed. Note that the Constant Voltage Drop
(CVD) for the diode(s) used must be estimated. For the W005G Bridge Rectifier used in the lab,
a CVD = 1.1V is a good estimate for operation at a peak current on the order of 100 mA.
NMOSFET.vi
This NMOS FET analyzer VI is designed to simulate the IDS vs. VDS characteristic of an
enhancement mode (VT0 > O) or depletion mode (VT0 < 0) NMOS field effect transistor. The
modeling includes both channel length modulation effects and body voltage effects. It also
calculates the VDS at "pinchoff". Enter the appropriate input parameters for the device and press
the RUN button.
NMOSFETAnalMeas4.vi
This VI is designed to allow the user to input three channels of specified voltage measurements
from the NMOS transistor test circuit shown in the diagram below the front panel, and to
calculate the threshold voltage (VT0), transconductance (Kn) and channel width modulation
(lambda) of the transistor. It requires two RUN cycles to calculate these parameters. In the first
RUN cycle, the VDS vs. IDS characteristic at measured VGS will be graphed. Note that the
VTO, Kn and lambda output parameters will not necessarily be accurate at this point. The user
must then determine the "pinchoff point" (VDS, IDS at pinchoff) from the graph (drag the
cursor), and input them under "Graph Measurement" on the panel. Clicking on the RUN arrow a
second time will calculate accurate VTO and Kn values for the device.
Required Input Voltages: Channel 0 -- VGS; Channel 1 -- VDS; Channel 2 -- VRD (voltage
across resistor RD).
Required Voltage Sources: VSS -- 12 V DC; VDD -- 5 + 5 sin 2(pi)t V (5 V peak amplitude
sine wave with 5 V DC offset and frequency of 1 Hz). Special note: Because of maximum
voltage output limitations, in order to produce VDD with the HP Signal Generator, you will have
to refrain from using the 50-ohm feedthrough connector and set the generator to 2.5 V DC offset,
and 5 V PP amplitude sine wave at a frequency of 1 Hz. Remember, without the 50-ohm
feedthrough connector, all offset and peak-to-peak amplitude readings are effectively doubled at
the output.
Required Resistances: R1 = 100 K ohms R2 = 200 K ohms; RD = 1 K ohms.
NMOSFETBias3.vi
This VI is designed to allow the user to input specified parameters for design of a four-resistor dc
biasing circuit for an NMOS FET. It then uses a formula node to calculate the required
component parameters for the design of the biasing circuit, after the RUN button is pressed.
Default parameters are from the instructors personal NMOSFET circuit. Note that Gate Margin
is the selected source-to-ground voltage (difference between gate-to-ground and gate-to-source
45
voltages). Gate Fraction is the ratio of gate-to-ground voltage/VDD. Other parameters are those
commonly associated with NMOS devices and the biasing circuit.
NMOSFET_LL2.vi
This NMOS FET analyzer VI is designed to simulate the IDS vs. VDS characteristic of an
enhancement mode (VT0 > O) or depletion mode (VT0 < 0) NMOS field effect transistor. The
modeling includes both channel length modulation effects and body voltage effects. DC biasing
using a four-resistor, single supply circuit sets the Q point for the device in the saturation region.
The circuit load line is calculated for verification of the Q point. Q point calculation is precisely
valid only for zero channel length modulation; however small values of lambda may be
accommodated with good result.
NPNBE.vi
This NPN BJT analyzer VI is designed to simulate the IB vs. VBE (first quadrant) characteristic
of an NPN transistor. The modeling is based upon a modified Gummel-Poon description of the
transistor. IS is the saturation current at temperature T, BF is the forward (ce) current gain, BR
is the reverse (ce) current gain, T is absolute temperature, IB is base current, VCE is the
collector-emitter voltage, and VBE is the base-emitter voltage. Note also that there is NO
correction of IS in this model for changes in temperature. Input the appropriate parameters and
press the RUN button.
NPNCE.vi
This NPN BJT analyzer VI is designed to simulate the IC vs VCE characteristic in the first
quadrant of an NPN transistor. The modeling is based upon the Gummel-Poon description of the
transistor, but does not include the Early effect. IS is saturation current, BF is forward (ce)
current gain, BR is reverse (ce) current gain, IB is base current, T is absolute temperature, VCE
is collector-emitter voltage, IC is collector current. Note that IS is NOT corrected for changes in
temperature T.
NPNBFISAnalMeas.vi
This VI is designed to allow the user to input specified and measured parameters from the NPN
BJT transistor circuit shown, and calculate the BF and IS of the transistor. It uses a formula node
to calculate the required parameters after the RUN button is pressed. Parameters follow standard
definitions for the NPN BJT. Default parameters are from the instructors personal 2N2222A
BJT. Channel 0 is designed to measure VBE in the circuit, and channel 1 is designed to measure
VCE. Assumptions are that the biasing setup operates the transistor in the forward active region
and that VA (Early Voltage) is very large, so corrections to BF can be neglected. The
"Betometer" provides a graphic display of forward current gain.
NPNBias.vi
bias circuit using an NPN BJT. It then uses a formula node to calculate the required component
parameters for the design after the RUN button is pressed. C-E V Drops is a parameter that sets
the distribution of voltage drop between RC and RE. A factor of 2 divides the drop evenly; a
46
factor of 3 divides the drop 1/3 to RC and 2/3 to RE, etc. Base Margin sets the ratio of Collector
to Base bias supply current. A default value of 5 is used to be consistent with the text. Larger
Base Margin values give more power-efficient circuit performance. f is the base voltage divider
fraction. r is the (BF+1)RE/REQ ratio and should be >> 1. If it isn't, reducing the Base Margin
will help. Other parameters follow standard definitions for the NPN BJT and biasing circuit.
Default parameters are those from problem 5.87 in the text.
NPNBE_LL.vi
This Q-point analyzer VI is designed to simulate the IB vs VBE characteristic of an NPN
transistor, and calculate the Q point (Q-VBE, Q-IB) for forward active region operation in a
four-resistor, single voltage supply dc biasing circuit. The VI calculates the BE circuit load line
equation and plots it to help you graphically visualize the Q point solution. IS is the saturation
current at temperature T, BF is the forward (ce) current gain of the transistor, BR is the reverse
(ce) current gain, T is absolute temperature, RE, R1, and R2 are the relevant biasing circuit
resistances, VCC is the supply voltage, VCEQ is collector-emitter Q-point voltage, and ICEQ is
the Q-point collector current. The default parameters correspond to the solution to problem 5.87
in your text. Note also that there is NO correction of IS in this model for changes in temperature.
NPNCE_LL.vi
This Q-point analyzer VI is designed to simulate the IC vs. VCE characteristic of an NPN
transistor, and calculates the Q point (Q-VCE, Q-IC) for forward active region operation in a
four-resistor, single voltage supply dc biasing circuit. The VI calculates the CE circuit load line
equation and plots it to help you graphically visualize the Q point solution. BF is the forward
(ce) current gain of the transistor, IS is the saturation current, BR is the reverse (ce) current gain
(default 1.0), T is absolute temperature, VCC is the supply voltage, R1, R2, RC, and RE are the
biasing circuit resistances. VCE is collector-emitter voltage, IC is collector current, and Q-VCE
and Q-IC are the calculated VCE and IC Q point solution set. The default parameters correspond
to the solution to problem 5.87 in your text.
CEAmpAnal.vi
This VI is designed to allow the user to input specified parameters for small-signal ac analysis of
a CE BJT amplifier circuit. It uses a formula node to calculate the peak output voltage and ac
voltage gain parameters for the design when the RUN button is pressed. It also displays a
representation of the sinusoidal output voltage as a function of time.
Input parameters:
Rs is the equivalent voltage source resistance; Vsp is the peak input source voltage; C1 is the
input ac coupling capacitance; C2 is the emitter bypass capacitor and C3 is the output coupling
capacitor; frequency is the frequency of the input signal in Hz; R1, R2, R3, RE and RC are the
relevant bias circuit and ac load resistances; rp, gm, and ro are the respective small-signal ac
input resistance, transconductance, and output resistance of the transistor at the design Q-point.
(See Circuit Diagram below the front panel.)
47
NPNCEBias.vi
bias circuit using an NPN BJT in a Common Emitter amplifier design. It then uses a formula
node to calculate the required component parameters for the design after the RUN button is
pressed. C-E V Drops is a parameter that sets the distribution of voltage drop between RC and
RE. A factor of 2 divides the drop evenly; a factor of 3 divides the drop 1/3 to RC and 2/3 to
RE, etc. Base Margin sets the ratio of Collector to Base bias supply current. A default value of
5 is used to be consistent with the text. Larger Base Margin values give more power-efficient
circuit performance. f is the base voltage divider fraction. r is the (BF+1)RE/REQ ratio and
should be >> 1. If it isn't, reducing the Base Margin will help. Other parameters follow standard
definitions for the NPN BJT, biasing circuit and small-signal transistor model. Default
parameters are from the instructors personal BJT and design choices.
Amp/Filter.vi
This VI is designed to allow the user to input specified parameters for design of an
instrumentation amplifier and first-order bandpass filter. It uses a formula node to calculate the
peak output voltage (Vop) and ac voltage gain (Av) for the design when the RUN button is
pressed. It also displays a representation of the sinusoidal output voltage as a function of time.
GND
Ch1 +
Ch1 -
NC
Ch2 +
Ch2 -
68
Ch0 -
Ch0 +
Input parameters:
Vsp is the peak input source voltage; frequency is the frequency of the input signal in Hz; RG is
the gain control resistor for the Burr Brown INA 118 instrumentation amplifier, RH1, RH2, and
CH2 are the relevant circuit components for the first-order high-pass filter; RL1, RL2, and CL1
are the relevant circuit components for the first-order low-pass filter.
34
67
33
66
32
65
31
Green Connector Block Analog Channel Input Connections
48

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CSUS COLLEGE OF ENGINEERING AND

EEE 102L Analog/Digital Electronics

EEE 102L Analog/Digital Electronics Laboratory

General knowledge of a structured programming language (i.e. C++).

Topics Covered/Class Schedule/Evaluation:

Introduction to the Lab

Science and Design Content Distribution:

Contribution of Course to the Professional Education Component:

Relationship of Course to Program Outcomes:

Course Coordinator: John Oldenburg, EEE

Date: January 15, 2007

EEE 102L Parts Kit Spring 2005

Resistors 1/4 W, Carbon Film, 5%

CSUS College of Engineering and Computer Science

Laboratory 1 Introductory PSpice Programming Assignment

CSUS College of Engineering and Computer Science

Macintoshes. Closing an application window in Mac OS does NOT automatically quit a

DIGITAL RECORDING OF ANALOG SIGNALS AND MEASUREMENTS IN THE

EEE102L Lab_2 -- LabVIEW Virtual Instruments

PART I -- A/D CONVERTER AMPLITUDE RESOLUTION

V(t) = ao + ancos not + bnsin n ot

We evaluate the above constants as follows:

(Remember that n is an integer and sin (n2) = 0.)

bn = 1 -cos n + 1 + 1 cos n2 - cos n

bn = 0 for n = 2, 4, 6, ... and bn = 4 for n = 1, 3, 5, ...

Notes Concerning the Operation of the HP Signal Generators

Laboratory 3 Exploration of Diode Characteristics

Part II PSpice Analysis of Simple Diode Circuits

Laboratory 4 Diode Circuits

Stability/Waveform Monitor. Take a picture of your front panel for documentation of

Laboratory 5 MOSFET Transistor Characteristics

Laboratory 6 BJT Transistor Characteristics

Laboratory 7 Common-Emitter Amplifier Design

r , gm, and ro are the respective small-signal ac input resistance,

Figure 1. Signal Generator Voltage Divider Circuit

Laboratory 8 OP Amp Instrumentation Amplifiers and First Order Filters

Figure 1. Signal Generator Voltage Divider Circuit

Procedure for taking a "Picture" of the active window on

EEE 102L Virtual Instrument Documentation

Diode Current Analyzer.vi

Diode Junction Analyzer.vi

Filtered DC/AC Voltmeter.vi

Green Connector Block Analog Channel Input Connections

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