Professional Documents
Culture Documents
om
p.
su
/x
/
Compal Confidential
PAZ00 Schematics Document
yc
2010-07-15
//
m
REV: 1.0a
tt
p:
Issued Date
Security Classification
2006/08/18
Deciphered Date
2008/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Cover Page
Size
C
Date:
Document Number
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
E
of
33
LVDS
LVDS Bridge
SN75LVDS83
LCD Conn.
DDR2
RGB
DDR2 SDRAM * 4
512M/1GB
USB1(Client)
HDMI Conn.
DDC_I2C(3,3V)
HDMI
USB PHY
(USB3315)
USB3 (Host)
SDIO1(3.3V)
SD/MMC conn
HSMMC
//
m
NAND Flash
(128M)
CAM_I2C(3.3V)
tt
h
ENE KBC
KB926
BT module
WIFI
2
SIM
USB2.0
USB 2.0
DMIC
GNE_I2C(3.3V)
Webcam
Audio Codec
ALC5632
Audio AMP
TPA6017
Speaker
HeadPhone/Ext. MIC
PWR_I2C(1.8V)
p:
LED
USB2 (HOST)
GNE_I2C(1.8V)
yc
eMMC
(4/8/16/32GB)
SDIO
om
p.
su
DDC_I2C(5V)
/x
/
UART
PWR_I2C(3.3V)
3
PMU
TI TPS658621
Thermal Sensor
ADI ADT7421
GNE_I2C(3.3V)
G-SENSOR
Bosch BMA150
PS2
GNE_I2C(3.3V)
T/P
SPI
Light sensor
Intersil 29011
GNE_I2C(3.3V)
TPM ST19NP18
DC/DC Interface
EC_I2C(3.3V)
SPI ROM
DC IN
Battery
Keyboard
BATT IN
Compal Secret Data
Security Classification
CHARGER
Issued Date
2008/12/22
Deciphered Date
2009/12/22
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
Rev
0.1
Sheet
E
of
33
0.5A
5.5A
1A
D
+LCD_INV
100mA
Panel
160mA
6.036A
2A(SB)
+5VALW
0.75A
+5VS
20mA
4A
DDR2
0.5A
0.5A
1.5A
VIN
B+
0.5A
+3VALW
0.5A
0.5A
KBC
1A
SPI ROM
6.843A
+3VS
1A
//
m
14.25A
yc
15.25A
AC
0.5A
tt
BATT
0.45A
+3VS_S3
AVDD_PLL
+1.2VS_LDO2
10mA
VDD_RTC
130mA
100mA
+1.8VS_LDO4
+2.85VS_LDO6
+3.3VS_LDO7
200mA
20mA
130mA
100mA
AVDD_USB
AVDD_OSC
AVDD_CRT
HDMI(AVDD_HDMI)
C
100mA
WiFi
+LCD_VDD
+3.3VS_LDO3
110mA
Panel
600mA
WebCam
1.5A
WiFi
150mA
WWAN
+1.8VS_LDO8
100mA
HDMI
(+AVDD_HDMI_PLL)
+2.85VS_LDO9
+1.2VS_SM0
+1.0VS_SM1
+2.85VS_LDO5
150mA
EMMC
USB PHY
Codec
0.5A
0.5A
0.15A
T20
160mA
NC
USB HUB x2
1A
DC
+1.1VS_LDO1
100mA
1A
p:
USB PHY
om
p.
su
+1.8VS
/x
/
PMU
6.5A
+3.3VS_LDO0
AMP
200mA
2.286A
1.05VS
USB PWR SW
10mA
1.25A
1.2V
0.5A
G sensor
BT
+VDDIO_LCD
Light sensor
+VDDIO_UART
Card Reader
+VDDIO_AUDIO
Thermal sensor
+VDD_FUSE
T20
+VDDIO_SDIO
+VDDIO_NAND
0.75A
0.15A
+VDDIO_VI
0.5A
0.15A
5A
+VDDIO_BB
Security Classification
Issued Date
2009/08/28
Deciphered Date
2010/08/28
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power delivery
Size
C
Date:
Rev
0.1
LA-5952P
Wednesday, July 21, 2010
Sheet
1
of
33
om
p.
su
/x
/
tt
p:
//
m
yc
Security Classification
2009/08/28
Issued Date
Deciphered Date
2010/08/28
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Power Sequence
Rev
0.1
LA-5952P
Date:
Sheet
of
33
Voltage Rails
Power Plane
Description
S1
S3
S5
VIN
N/A
N/A
N/A
B+
N/A
N/A
N/A
+VDD_CPU
ON
OFF
OFF
+1.8V
ON
ON
OFF
+VDD_CORE
ON
OFF
OFF
+RTCVCC
RTC power
ON
ON
ON
+3VS_S3
ON
ON
OFF
+3VALW
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
ON
ON
ON*
+5VS
ON
OFF
OFF
BOM configuration
@
45@
PR@
SI@
For
For
For
For
reserve.
45 level.
Procyon sku only
Sirius sku only
EC_SMB_DA1
DDC_SCL_3P3
DDC_SDA_3P3
CAM_I2C_SCL
CAM_I2C_SDA
GEN1_I2C_SCL
GEN1_I2C_SDA
PWR_I2C_SCL
PWR_I2C_SDA
(3.3V)
KB926
(3.3V)
T-20
(3.3V)
T-20
(3.3V)
T-20
(1.8V)
T-20
EC
KB926
Battery
PMIC
Thermal
Sensor
Audio
Codec
G sensor
V
(3.3V)
TPM
Light
sensor
HDMI
LCD
Panel
ZZZ1
V
(3.3V)
V
(3.3V)
V
(3.3V)
yc
EC_SMB_CK1
T-20
V
(3.3V)
//
m
SOURCE
om
p.
su
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
2
/x
/
:
:
:
:
V
(1.8V)
V
(3.3V)
X76 Hynix
X7624051L02
ZZZ
V
(3.3V)
V
(3.3V)
V
(3.3V)
PCB_LA-6352P
DAZ0EF00100
tt
p:
Security Classification
2006/08/18
Issued Date
Deciphered Date
2008/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Notes List
Size Document Number
Custom
Date:
Rev
0.1
Sheet
E
of
33
+VDDIO_LCD
+3VS
+3VS
2
R1
U1E
2
1
R1278 0_0402_5%
U1D
R1253
AB21
V24
AC25
AA25
W25
R7
100K_0402_1%
TEMP_ALERT#
7 TEMP_ALERT#
AD23
AC24
HDMI_HPD
14,19 HDMI_HPD
V23
Y22
AC23
DDC_SCL_3P3
DDC_SDA_3P3
14 DDC_SCL_3P3
14 DDC_SDA_3P3
@
C6
4.7U_0603_6.3V6K
+3.3VS_LDO7
AH17
1
0_0402_5%
R9
+AVDD_HDMI
LCD
LCD_SCK
LCD_CS0#
LCD_CS1#
LCD_SDOUT
LCD_SDIN
LCD_DC0
LCD_DC1
HDMI_INT#
CRT_HSYNC
CRT_VSYNC
DDC_SCL
DDC_SDA
AVDD_VDAC
VDAC_R
VDAC_G
VDAC_B
C7
CRT
0.1U_0201_6.3V6K
VDAC_VREF
VDAC_RSET
3.3V
C4
2.2U_0603_6.3V6K
C1
10P_0201_25V8
@
LCD_D00
AA26
LCD_D00 13
LCD_D01
AC26
LCD_D01 13
LCD_D02
AC27
LCD_D02 13
LCD_D03
AC28
LCD_D03 13
LCD_D04
AD25
LCD_D04 13
LCD_D05
AD28
LCD_D05 13
LCD_D06
Y26
LCD_D06 13
LCD_D07
Y27
LCD_D07 13
LCD_D08
Y28
LCD_D08 13
LCD_D09
Y25
LCD_D09 13
LCD_D10
AA28
LCD_D10 13
LCD_D11
AA27
LCD_D11 13
LCD_D12
U25
LCD_D12 13
LCD_D13
U28
LCD_D13 13
LCD_D14
U27
LCD_D14 13
LCD_D15
U26
LCD_D15 13
LCD_D16
V27
LCD_D16 13
LCD_D17
V26
LCD_D17 13
AB25
AA23
AB23
AA22
V25 LVDS_SHTDN#_V252
1LVDS_SHTDN#
R1272 0_0402_5%
AC22
VDAC_VREF
VDAC_RSET
R17
2.2K_0402_5%
0.1U_0402_10V7K
2
HDMI_TXCN
HDMI_TXCP
RB161M-20_SOD123-2
C13
0.1U_0201_6.3V6K
AA12
HDMI_TXD0N
HDMI_TXD0P
AVDD_HDMI_PLL
HDMI_TXD1N
HDMI_TXD1P
+AVDD_HDMI_PLL
2
+1.8VS_LDO8
1
0_0402_5%
1
R13
1.8V
HDMI_TXD2N
HDMI HDMI_TXD2P
HDMI_RSET
AF17
AG17
HDMI_TXCN
HDMI_TXCP
AE16
AE17
HDMI_TXD0N
HDMI_TXD0P
AC18
AD18
HDMI_TXD1N
HDMI_TXD1P
AH18
AG18
HDMI_TXD2N
HDMI_TXD2P
C10
2
HDMI_TXD1N 14
HDMI_TXD1P 14
p:
h
1
2
@
R30
47K_0402_1%
10K_0402_5%
R41
2
10K_0402_5%
R40
2
SAN@
1
10K_0402_5%
@ R39
2
10K_0402_5%
@ R38
2
10K_0402_5%
R37
2
10K_0402_5%
R36
2
10K_0402_5%
R35
2
10K_0402_5%
@ R34
2
10K_0402_5%
10K_0402_5%
R33
GMI_CLK
GMI_DPD
GMI_RST#
GMI_WAIT
GMI_WP#
GMI_IORDY
H28
H27
VDDIO_VI
CSI_CLKAN
CSI_CLKAP
2
R15
L22
M23
J22
L27
M24
CSI_D1AN
CSI_D1AP
VI_HSYNC
VI_VSYNC
CSI_D2AN
CSI_D2AP
VI_D00
VI_D01
VI_D02
VI_D03
VI_D04
VI_D05
VI_D06
VI_D07
VI_D08
VI_D09
VI_D10
VI_D11
CSI_CLKBN
CSI_CLKBP
CSI_D1BN
CSI_D1BP
DSI_CLKAN
DSI_CLKAP
DSI_D1AN
DSI_D1AP
VI_GP0
VI_GP3
VI_GP4
VI_GP5
VI_GP6
1
10K_0402_5%
NAND_D0
NAND_D1
NAND_D2
NAND_D3
NAND_D4
NAND_D5
NAND_D6
NAND_D7
DSI_D2AN
DSI_D2AP
SDIO1_WP 18
1
1
2
R8
R1295
100K_0402_5%
1
0_0201_5%
GMI_AD18
T20_WAKE# 9,19
GMI_AD18
HSMMC_DAT[0..7]
12
1.2V
DSI_CSI_RDN
AA17
Y16
1
AF21
AH26
AG26
C11
0.1U_0201_6.3V6K
AD20
AE20
AH23
AG23
AB20
AC20
AH24
AG24
AD21
AC21
AF20
AG20
AH21
AG21
AH20
R16
49.9_0402_1%
FORCE_RECOVERY#
Strap option
Strap pin
Net Name
USB recovery
GMI_OE#
NAND_RE#
JTAG_ARM1
GMI_CLK
NAND_CLE
JTAG_ARM0
GMI_ADV#
NAND_ALE
Description
Default
0_0402_5%
Description
NAND_D[5:4]
:
:
:
:
00 Hynix 512M
NAND_D4=0 ; Install R38 ; @R27
NAND_D5=0 ; Install R39 ; @R28
NAND_D5
01 Micron 512M
GMI_AD[7:4] NAND_D[7:4]
eMMC configration.
00 SANDISK eMMC
NAND_D6=0 ; Install R40 ; @R29
NAND_D7=0 ; Install R41 ; @R30
Boot_Select
[3:0]
GMI_AD
[15:12]
01 Toshiba eMMC
NAND_D6=1 ; Install R29 ; @R40
NAND_D7=0 ; Install R41 ; @R30
00
PAZ00
L01-L04: 00
L05-L07: 01
NAND_D4
NAND_D[7:6]
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2008/12/22
Deciphered Date
00
eMMC primary x 4
eMMC primary x 8
eMMC primary x 4, high voltage
NAND
NAND (42nm)
Mobile LBA NAND
FlexMuxOne NAND
eSD x 4
SPI Flash
SNOR (Muxed x 16)
SNOR (Muxed x 32)
SNOR (Non-Muxed x 16)
MuxOne NAND
Reserved
Reserved
Use fuse data
Security Classification
Issued Date
GMI_AD
[15:12]
2009/12/22
Title
PAZ00 : 0001
A
PAZ01 : 0011
Size
C
Date:
100K_0402_5%
2
2
R6
100K_0201_5%
HSMMC_DAT0
HSMMC_DAT1
HSMMC_DAT2
HSMMC_DAT3
HSMMC_DAT4
HSMMC_DAT5
HSMMC_DAT6
HSMMC_DAT7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
R5
GMI_AD18
NAND_D6
+VDDIO_NAND
SDIO1_WP
HSMMC_CD#
HSMMC_WP
GMI_AD12
GMI_AD13
GMI_AD14
GMI_AD15
T20_WAKE#_R
+AVDD_DSI_CSI
DSI_CSI_RUP
VI_MCLK
VI_PCLK
AG5
AE9
AF11
AG6
AH8
AG11
AF9
AF8
AE6
AE12
AH12
AH6
AH11
AG3
AH9
AH5
AG12
AD3
AE5
AG8
AD8
AE7
AC5
AE11
AE8
AC11
AE10
AC8
12
MIPI
AVDD_DSI_CSI_1
AVDD_DSI_CSI_2
CAM_I2C_SCL
CAM_I2C_SDA
NAND_D[0..7]
@ D15
R1238
NAND_D7
R32
+VDDIO_VI
Net Name
NAND_RE#
NAND_WE#
NAND_CLE
NAND_ALE
GMI_AD12
GMI_AD13
GMI_AD14
GMI_AD15
NAND_D4
NAND_D5
NAND_D6
NAND_D7
GMI_OE#
GMI_WR#
GMI_AD0
GMI_AD1
GMI_AD2
GMI_AD3
GMI_AD4
GMI_AD5
GMI_AD6
GMI_AD7
GMI_AD8
GMI_AD9
GMI_AD10
GMI_AD11
GMI_AD12
GMI_AD13
GMI_AD14
GMI_AD15
GMI_AD16
GMI_AD17
GMI_AD18
GMI_AD19
GMI_AD20
GMI_AD21
GMI_AD22
GMI_AD23
GMI_AD24
GMI_AD25
GMI_AD26
GMI_AD27
100K_0402_5%
R29
100K_0402_5%
TO@
1
1
2
@
R28
100K_0402_5%
1
2
@
R27
100K_0402_5%
1
2
@
R26
100K_0402_5%
1
2
@
R25
100K_0402_5%
1
2
@
R24
100K_0402_5%
1
2
100K_0402_5%
100K_0402_5%
1
1
R23
+VDDIO_NAND
ACCELERO_INT#
18 ACCELERO_INT#
RB751V-40TE17_SOD323-2
tt
19
1
R22
R31
FORCE_RECOVERY#
R21
47K_0402_1%
4
5
6
7
NAND
VI
H23
H25
J23
J28
J24
J27
J25
J26
K23
L26
L23
M22
TPM_RESET#
TPM_DATA#
TPM_ACCPCMD
LIGHT_INT
HDMI_TXD2N 14
HDMI_TXD2P 14
Change R to 0402(PVT),
Change all pull down resistor to 10K by NVIDIA suggest.(PVT2)
CAM_I2C_SCL
CAM_I2C_SDA
19 CAM_I2C_SCL
19 CAM_I2C_SDA
GMI_CS0#
GMI_CS1#
GMI_CS2#
GMI_CS3#
GMI_CS4#
GMI_CS5#
GMI_CS6#
GMI_CS7#
2 0.1U_0402_10V7K
HDMI_TXD0N 14
HDMI_TXD0P 14
4
5
6
7
NAND boot
1
1
0
0
AC10
L25
K25
@ SW1
NSS507-212F-CCCG1T_3P
eMMC boot
1
0
0
0
SDIO1_CD#
SDIO1_CD#
AC7
AF1
AF2
L24
L28
GMI_AD12
GMI_AD13
GMI_AD14
GMI_AD15
AC9
NAND_BSY#
NAND_WP#
L21
HDMI_TXCN 14
HDMI_TXCP 14
C14
0.1U_0402_10V7K
AF3
HSMMC_CMD
+VDDIO_VI
2
R11 1K_0402_1%
HDMI_RSET 2
1
R14 1K_0402_1%
AF18
AG9
AF6
NAND_CLE
GMI_ADV#
AD11
AD6
AVDD_HDMI_1
AVDD_HDMI_2
NAND_RE#
NAND_WE#
yc
AA15
Y15
NAND_CLE
EN_VDDIO_MMC
HSMMC_CMD
//
m
C12
2.2U_0603_6.3V6K
AF5
AF12
AD12
AC6
AC12
AB12
AD5
AD9
HSMMC_CLK
NAND_BSY#
NAND_WP#
C8
2.2U_0603_6.3V6K
AH3
NAND_CE0
NAND_CE1
NAND_RE#
NAND_WE#
18
1
0_0402_5%
1
NAND_ALE
NAND_ALE
R18
2.2K_0402_5%
+3VS_S3
GEN2_I2C_SCL
GEN2_I2C_SDA
0.1U_0402_10V7K
CAM_I2C_SCL
CAM_I2C_SDA
+3VS
VDDIO_NAND_1
VDDIO_NAND_2
VDDIO_NAND_3
R12
Y7
Y8
Y9
C5
EN_VDDIO_MMC
D12
2
HSMMC_CLK
AC17
+VDDIO_VI
AB17
AB18
AE19
AE18
NAND_CE0
NAND_CE1
2
1
R1279 0_0402_5%
2
1
@ R10
0_0402_5%
C9
1
LCD_DE 13
LCD_HSYNC 13
LCD_VSYNC 13
2.85V
+AVDD_VDAC
+2.85VS_LDO6
W23
Y23
LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
LCD_DE
LCD_HSYNC
LCD_VSYNC
+VDDIO_NAND
1
0_0402_5%
+VDDIO_LCD
LCD_PWR0
LCD_PWR1
LCD_PWR2
2
@ R4
13
8,13 EN_VDD_PNL
AD24
U24
AA24
AE24
U23
AD27
AD26
LCD_PCLK
/x
/
LVDS_SHTDN# 2
1LVDS_SHTDN#_PWR0
@ R1270 0_0402_5%
EN_VDD_PNL 2
1EN_VDD_PNL_PWR2
@ R1271 0_0402_5%
13 LVDS_SHTDN#
LCD_WR#
LCD_DE
LCD_HSYNC
LCD_VSYNC
LCD_M1
LCD_PCLK
om
p.
su
0.1U_0201_6.3V6K
Y24
Reverse T20.T25 to
EN_VDD_PNL ,
T20.V25 to LVDS_SHTDN#
2
1
33_0402_5%
V28 LCD_PCLK_R
C3
C2
LCD_PCLK
VDDIO_LCD1
VDDIO_LCD2
4.7U_0603_6.3V6K
U22
V22
1
+VDDIO_NAND
+3VS_S3
1
0_0402_5%
Document Number
Rev
0.2
T20 schematic
Wednesday, July 21, 2010
Sheet
1
of
33
+3VS
+3VS
R232
1
KB_COL0
KB_COL1
KB_COL2
KB_COL3
KB_COL4
KB_COL5
KB_COL6
KB_COL7
CLK_32K_IN
@
R267
330_0402_5%
KB_ROW00
KB_ROW01
KB_ROW02
KB_ROW03
KB_ROW04
KB_ROW05
KB_ROW06
KB_ROW07
KB_ROW08
KB_ROW09
KB_ROW10
KB_ROW11
KB_ROW12
KB_ROW13
KB_ROW14
KB_ROW15
@
C232
10P_0402_50V8J
tt
1
1
4
6
SCL
SDA
GND
TEMP_THERM#
TEMP_ALERT# 6
ADT7421ARMZ-REEL_MSOP8P
/x
/
om
p.
su
H17
F20
E18
D18
F18
F17
E21
D21
F21
E17
D15
F16
E14
F13
D16
D12
D13
F23
F25
H22
G25
F22
D24
H24
E23
F9
F12
E12
E9
F10
G8
F11
G9
F19
E15
G23
D9
DDR_DQS0N
DDR_DQS0P
D19
E20
DDR_A_DQS#0 10
DDR_A_DQS0 10
DDR_DQS1N
DDR_DQS1P
F14
F15
DDR_A_DQS#1 10
DDR_A_DQS1 10
DDR_DQS2N
DDR_DQS2P
E24
F24
DDR_A_DQS#2 11
DDR_A_DQS2 11
DDR_DQS3N
DDR_DQS3P
E11
D10
DDR_A_DQS#3 11
DDR_A_DQS3 11
DDR_A00
DDR_A01
DDR_A02
DDR_A03
DDR_A04
DDR_A05
DDR_A06
DDR_A07
DDR_A08
DDR_A09
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
A20
C24
D20
B20
F26
C26
C27
F28
A26
A23
D23
C20
C18
E28
C28
VDD_DDR_RX
DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_A_DM[0..3] 10,11
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_RAS#
DDR_CAS#
DDR_WE#
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CS0#
DDR_CS1#
DDR_ODT0
DDR_CKE0
DDR_CKE1
DDR_CLK#
DDR_CLK
THERMD_N
THERMD_P
DDR_COMP_PU
DDR_COMP_PD
DDR_QUSE0
DDR_QUSE1
DDR_QUSE2
DDR_QUSE3
DDR_A_MA[0..13] 10,11
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
B23
H26
F27
DDR_A_RAS# 10,11
DDR_A_CAS# 10,11
DDR_A_WE# 10,11
B26
A24
B24
DDR_A_BS#0 10,11
DDR_A_BS#1 10,11
DDR_A_BS#2 10,11
E25
C23
M_CS#0
B21
M_ODT
A21
C21
M_CKE0
10,11
E27
E26
M_CLK_DDR#0 10,11
M_CLK_DDR0 10,11
E6
F7
THERMD_N
THERMD_P
E8
F8
R53
R54
2 49.9_0402_1%
2 49.9_0402_1%
1
1
G15 DDR_QUSE0
G17 DDR_QUSE1
A18 DDR_QUSE2
B18 DDR_QUSE3
1.8V
+1.8VS
R55 1
2
0_0402_5%
R57 1
2
0_0201_5%
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
DDR2
VDDIO_DDR_01
VDDIO_DDR_02
VDDIO_DDR_03
VDDIO_DDR_04
VDDIO_DDR_05
VDDIO_DDR_06
VDDIO_DDR_07
VDDIO_DDR_08
VDDIO_DDR_09
VDDIO_DDR_10
VDDIO_DDR_11
VDDIO_DDR_12
VDDIO_DDR_13
VDDIO_DDR_14
VDDIO_DDR_15
VDDIO_DDR_16
VDDIO_DDR_17
VDDIO_DDR_18
VDDIO_DDR_19
VDDIO_DDR_20
VDDIO_DDR_21
VDDIO_DDR_22
VDDIO_DDR_23
VDDIO_DDR_24
VDDIO_DDR_25
2.85V
4.7U_0603_6.3V6K
SYS_CLK_REQ
CLK_32K_OUT
4.7U_0603_6.3V6K
PWR_I2C_SCL 28
PWR_I2C_SDA 28
0.1U_0201_6.3V6K
CORE_PWR_REQ
CPU_PWR_REQ
PWR_I2C_SCL
PWR_I2C_SDA
C1
C2
yc
2
1
+1.8VS_LDO4
PWR_INT#
C30
R49
2.2K_0402_5%
4.7U_0603_6.3V6K
SYS_RESET#
R48
2 2.2K_0402_5%
4.7U_0603_6.3V6K
VDDIO_SYS
CLK_32K_IN
1
47P_0402_50V8J
G18
C25
4.7U_0603_6.3V6K
PWR_I2C_SCL
PWR_I2C_SDA
1 @
C29
H20
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
K20
L16
L17
L20
M17
M18
M20
N18
N20
P20
R20
T20
U20
V20
+1.8VS
OUT NC
//
m
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
C28
R51
0_0402_5%
1.8V
G12 PLL_S_PLL_LF
AVDD_PLLX
+1.8VS_SYS
1.8V
IN
AVDD_PLLE
0.1U_0402_25V4K
AVDD_PLLM
T20_XTAL_OUT
4.7U_0603_6.3V6K
AVDD_PLL_S_LF
Y1
E2
Y4
1
+1.8VS
AVDD_PLLU
L7
4
R42
2M_0402_5%
AVDD_PLLA_P_C
H15
C27
OSC
T20_XTAL_IN
C24 1
R47
8
7
VDD
THERM#
ALERT#
D+
D-
U1C
8P_0402_50V8J
R46
C26
NC
OSC
E3
+AVDD_PLLE
H14
XTAL_IN
XTAL_OUT
AA18
8P_0402_50V8J
1
2
2
AVDD_OSC
1.05V
R45
R43
1
C23
100_0402_5%
2
3
address 0X4C
C21
R44
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
1
2
0_0402_5%
1
2
0_0402_5%
1
2
0_0402_5%
1
2
0_0402_5%
1
2
0_0402_5%
+AVDD_OSCH12
1.1V
THERMD_F_N
PWR_I2C_SCL_3V3
PWR_I2C_SDA_3V3
1
C22 4.7U_0603_6.3V6K
1.1V
+AVDD_PLLU
1.1V
+AVDD_PLLX
+AVDD_PLLM
THERMD_F_P
2 2
1
R239
L1
220 @100MHz
1
2
FBMA-10-100505-221T_0402
+AVDD_PLL_P_C
THERMD_N
R237
100K_0402_5%
U22
U1B
+1.1VS_LDO1
1.1V
100_0402_5%
THERMD_P
2
1
C212
1000P_0402_50V7K
2N7002DW-7-F_SOT363-6
+1.8VS_LDO4
47P_0402_50V8J
1.8V
2N7002DW-7-F_SOT363-6
PWR_I2C_SDA_3V3
NC
C211
0.1U_0201_6.3V6K
R238
1
Y5
32.768KHZ_12.5PF_9H03200413
PWR_I2C_SCL_3V3
Q33A
1
47P_0402_50V8J
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
Q31A
PWR_I2C_SDA 1
+3VALW
2
C286
10P_0402_50V8J
p:
Q33B
4
0.1U_0201_6.3V6K
PWR_I2C_SCL
C285
10P_0402_50V8J
Q31B
4
R193
2.2K_0402_5%
+3VS_TH
2
20_0402_5%
TPS658621_XTAL2
TPS658621_XTAL1
2.2K_0402_5%
R168
+3VS
G11
A14
R59
1
2
0_0201_5%
OWR
TEST_MODE_EN
R58
10K_0201_5%
Security Classification
Issued Date
2008/10/03
2009/10/03
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
Sheet
1
of
33
3.3V
USB1_DN
USB1_DP
AB11
2
1
0_0402_5%
AVDD_USB_PLL
USB3_VBUS
+USB3_VBUS
USB
USB3_ID
USB_REXT
3.3V
R1
GPIO_PV4
GPIO_PV5
GPIO_PV6
P7
R7
R6
HSIC_DATA
AC15
HSIC_STROBE
AD15
IC_DN
IC_DP
IC_REXT
SDIO2_CLK 15
R67 100K_0402_5% +VDDIO_SDIO
SDIO2_CMD 15
1
2
W_DISABLE#
W_DISABLE#
PEX_RST0#
PEX_RST0# 15,18
PEX_WAKE#
PEX_WAKE# 15
R69
100K_0402_5%
AE13
AF28
D22
G20
G21
M21
M7
R21
U5
V7
W4
Y6
C230
10P_0402_50V8J
100K_0402_5%
R229
PEX_L1_TXN
PEX_L1_TXP
PEX_L1_RXN
PEX_L1_RXP
+VDD_PEX
R80
U8
U9
V9
VDD_PEX_1
VDD_PEX_2
VDD_PEX_3
PEX_L2_TXN
PEX_L2_TXP
R85
+VDDIO_PEX_CLK
2
V8
PEX_L3_TXN
PEX_L3_TXP
VDDIO_PEX_CLK
PEX_L3_RXN
PEX_L3_RXP
0_0402_5%
AA1
AA2
AC4
AD4
PEX_CLK_OUT2_N
PEX_CLK_OUT2_P
Y4
Y5
PEX_TSTCLKN
PEX_TSTCLKP
V1
V2
PEX_REFCLKN
PEX_REFCLKP
U1
U2
PEX_TERMP
W6
0.1U_0201_6.3V6K
T20_Codec
R25
N23
17 T20_Codec
WF_PWDN#
M28
M27
M26
P26
+VDDIO_UART
17
P24
P23
P22
P28
N25
M25
HP_DET
HP_DET
@ C280
0.01U_0402_16V7K
H6
H5
GEN1_I2C_SCL
GEN1_I2C_SDA
UART2_TXD
UART2_RXD
UART2_RTS#
UART2_CTS#
H7
F4
G6
F5
UART1_TXD
UART1_RXD
UART3_TXD
UART3_RXD
UART3_RTS#
UART3_CTS#
F3
F2
F1
E4
GPIO_PU0
GPIO_PU1
GPIO_PU2
GPIO_PU3
GPIO_PU4
GPIO_PU5
GPIO_PU6
J1
G4
E1
F6
E5
H4
J2
DAP4_DIN
DAP4_DUT
DAP4_FS
DAP4_SCLK
H1
J4
H3
H2
GPIO_PV0
GPIO_PV1
GPIO_PV2
GPIO_PV3
@ R82
2.2K_0402_5%
@
Q5B
GEN1_I2C_SDA
UART1_TXD
UART1_RXD
UART3_TXD
UART3_RXD
UART3_RTS#
UART3_CTS#
R70 2
1
100K_0402_5%
BT_RST#
LCD_BL_PWM
LCD_BL_EN
15
15
15
15
BT_RST# 15
BT_WAKEUP
2
LCD_BL_PWM
LCD_BL_EN
DAP4_DIN
DAP4_DOUT
DAP4_FS
DAP4_SCLK
R207 33_0402_1%
VDDIO_AUDIO
DAP_MCLK1
DAP_MCLK2
SPDIF_IN
SPDIF_OUT
DAP1_SCLK
DAP1_FS
AUDIODAP1_DUT
DAP1_DIN
SPI1_SCK
SPI1_CS0#
SPI1_MOSI
SPI1_MISO
DAP2_SCLK
DAP2_FS
DAP2_DUT
DAP2_DIN
P27
R24
DAP_MCLK1
DAP_MCLK2
P25
R27
R28
R26
DAP1_SCLK
DAP1_FS
DAP1_DOUT
DAP1_DIN
R23
R22
T23
T25 EN_VDD_PNL_T252
SPI2_SCK
SPI2_CS0#
SPI2_CS1#
SPI2_CS2#
SPI2_MOSI
SPI2_MISO
R75 47_0402_5%
2
1
2
1
R76 47_0402_5%
R77 47_0402_5%
2
1
DAP_MCLK1_R
DAP_MCLK2_R 16
DAP1_SCLK_R
DAP1_FS
DAP1_DOUT
DAP1_DIN 17
1 EN_VDD_PNL
R1275 0_0402_5%
EN_VDD_PNL 6
3
SDIO2_CLK
DAP_MCLK1_R
DAP_MCLK2_R
DAP1_SCLK_R
+3VS
R84
2.2K_0402_5%
2.2K_0402_5%
R83
C278
10P_0402_50V8J
2
1
C277
10P_0402_50V8J
1
C228
10P_0402_50V8J
1
C229
10P_0402_50V8J
C227
10P_0402_50V8J
@
Q5A
1
@ C289
0.1U_0402_10V6K
GEN1_I2C_SCL
GEN1_I2C_SCL_3V3 13,17,18
2N7002DW-7-F_SOT363-6
1
2
R1225 0_0402_5%
6
GEN1_I2C_SDA_3V3 13,17,18
2N7002DW-7-F_SOT363-6
1
2
R1224
0_0402_5%
Security Classification
PEX_TERMP
@
R86
2005/05/26
Issued Date
1
2006/07/26
Deciphered Date
Title
T20(3/4)USB/SDIO/UART/AUDIO
2 2.49K_0402_1%THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SDIO1_CLK
SDIO1_CMD
SDIO1_DATA0
SDIO1_DATA1
SDIO1_DATA2
SDIO1_DATA3
DAP4_SCLK
2.2K_0402_5%
@ R81
V6
V5
M6
J5
K6
K4
M5
L5
GEN1_I2C_SCL
GEN1_I2C_SDA
0_0402_5%
R1267
1
2
Y3
Y2
PEX_CLK_OUT1_N
PEX_CLK_OUT1_P
+VBUS
+VDDIO_UART
V4
V3
DAP3_DIN
DAP3_DOUT
DAP3_FS
DAP3_SCLK
P21
C38
1
AA7
AA6
L2
L1
J3
M4
PEX_L2_RXN
PEX_L2_RXP
2N7002DW-7-F_SOT363-6
AC2
AC1
ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP
+VDDIO_AUDIO
2
1
0_0402_5%
10K_0402_5%
R79
AVDD_PEX_1
AVDD_PEX_2
AVDD_PEX_3
Q28A
R8
R9
T9
+USB1_VBUS
AA5
AA4
VDDIO_UART
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
M2
M3
M1
P3
P2
J7
U6
J6
p:
PEX_L0_RXN
PEX_L0_RXP
+AVDD_PEX
AD1
AD2
tt
PEX_L0_TXN
PEX_L0_TXP
PEX
ULPI_RESET#
EN_VDDIO_SD
16 ULPI_RESET#
18 EN_VDDIO_SD
+3VS
Q28B
2N7002DW-7-F_SOT363-6
+AVDD_PEX_PLL
AVDD_PEX_PLL
+5VS
+5VS
R92
LCD_BL_EN
H11
100K_0402_5%
U1H
P8
+VDDIO_BB
SDIO1_CMD
SDIO1_DAT0
SDIO1_DAT1
SDIO1_DAT2
SDIO1_DAT3
R265
33_0402_1%
SDIO1_CLK
1
2
SDIO1_CMD
SDIO1_DAT0
SDIO1_DAT1
SDIO1_DAT2
SDIO1_DAT3
R73
NC
DNC_00013
DNC_00014
DNC_00015
DNC_00016
DNC_00017
DNC_00018
DNC_00019
DNC_00020
DNC_00021
DNC_00022
DNC_00023
EC_REQUEST#
19 EC_REQUEST#
//
m
DNC_0001
DNC_0002
DNC_0003
DNC_0004
DNC_0005
DNC_0006
DNC_0007
DNC_0008
DNC_0009
DNC_0010
DNC_0011
DNC_0012
18
18
18
18
18
SDIO1_CLK_R
2
AA3
AB4
AB6
AC13
AC3
AE21
AE22
AE23
AF23
AF24
AF26
AF27
SDIO1_CLK_R
18 SDIO1_CLK_R
+VDDIO_SDIO
AF14
AG14
ULPI_CLK_R
P4
P6
N4
L3
L4
L6
P5
N6
VDDIO_BB
AVDD_IC_USB
R206 33_0402_1%
2
1
AE15
UART
AB9
3.3V
ULPI_D0
ULPI_D1
ULPI_D2
ULPI_D3
ULPI_D4
ULPI_D5
ULPI_D6
ULPI_D7
R177 10_0402_5%
ULPI_CLK_R 2
1 ULPI_CLK
ULPI_DIR
ULPI_DIR
ULPI_NXT
ULPI_NXT
ULPI_STP
ULPI_STP
C233
10P_0402_50V8J
1
1K_0402_1%
VDDIO_HSIC
HSIC
BB
ULPI_D[0..7]
2
R72
1
2
0_0402_5%
U1G
/x
/
SDIO3_CMD
WF_LED
15
15
15
15
15,20
om
p.
su
AB8
R2
SDIO2_DAT0
SDIO2_DAT1
SDIO2_DAT2
SDIO2_DAT3
WF_RST#
WF_LED
1
1K_0402_1%
SDIO3_CLK
HSIC_REXT
R78
1
2
0_0402_5%
2
C36
0.1U_0201_6.3V6K
2
R71
R3
U3
U4
R4
T4
T6
R5
U7
yc
SDIO
SDIO3_DATA0
SDIO3_DATA1
SDIO3_DATA2
SDIO3_DATA3
SDIO3_DATA4
SDIO3_DATA5
SDIO3_DATA6
SDIO3_DATA7
C37
0.1U_0402_10V7K
1
2
0_0402_5%
ULPI_CLK_R
2
10K_0402_5%
C32
0.1U_0201_6.3V6K
2
R66
VDDIO_SDIO
1
R65
USB_REXT 1
1K_0402_1%
C35
4.7U_0603_6.3V6K
2
1
0_0402_5%
1
M8
P1
AC16
+VDDIO_UART
+3VS
R61
+5VALW
USB3_DN 16
USB3_DP 16
USB3_ID
AF15
3.3V
+VDDIO_BB
+3VS_S3
2
1
R1280
0_0402_5%
2
1
@ R64 0_0402_5%
1
+5VS
2
1
0_0402_5%
USB3_DN
USB3_DP
2
1
R1262 0_0402_5%
2
1
@ R63
0_0402_5%
R68
AH15
AG15
+3VS
2
1
@ R1304 1K_0402_5%
L:HOST
H:Client
USB1_ID
AH14
USB3_DN
USB3_DP
USB1_DN
USB1_DP
AE14
+VDDIO_SDIO
+3VS
+VBUS
USB1_ID
C33
0.1U_0402_10V7K
AD17
AC14
AD14
USB1_ID2
USB1_ID2: From EC
@C311
@C311
0.1U_0402_16V4Z
R62
USB1_VBUS
+AVDD_USB_PLL
AVDD_USB_1
AVDD_USB_2
AA14
Y14
R60 1
2
0_0402_5%
C34
2.2U_0603_6.3V6K
0_0603_5%
R1317
100K_0402_1%
U1F
USB1_ID
@ D1 RB751V-40TE17_SOD323-2
@ D2 RB751V-40TE17_SOD323-2
2
1
+USB1_VBUS_R 16
+AVDD_USB
Add R1303 and remove D1,D2 for mini USB client only.
2
1
R1303 0_0402_5%
2
1
USB1_ID1
2 +USB1_VBUS_R
1
2
+3.3VS_LDO3
L23
+USB1_VBUS
3.3V
Date:
Document Number
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
E
of
33
1.0~1.2V
U1A
+VDD_RTC
+1.2VS_LDO2
CORE
C43
0.1U_0201_6.3V6K
0.9~1.0V
+1.0VS_SM1
C46
2
C47
0.1U_0201_6.3V6K
C108
C147
C149
47P_0402_50V8J
4.7U_0603_6.3V6K
C45
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C44
47P_0402_50V8J
2
0_0805_5%
C148
47P_0402_50V8J
1
R88
H9
J10
J11
J8
J9
K9
L9
M11
M9
N11
N12
P11
P12
P13
P14
R12
R13
+VDD_CPU
+VDD_CPU
47P_0402_50V8J
VDD_CPU_01
VDD_CPU_02
VDD_CPU_03
VDD_CPU_04
VDD_CPU_05
VDD_CPU_06
VDD_CPU_07
VDD_CPU_08
VDD_CPU_09
VDD_CPU_10
VDD_CPU_11
VDD_CPU_12
VDD_CPU_13
VDD_CPU_14
VDD_CPU_15
VDD_CPU_16
VDD_CPU_17
2
1
0_0402_5%
R87
1
Change connector form ACES-87213 to ACES_87036 by ME 4/16 ,remove 5VS & 1.8VS
01EVT for T20 UART/ ENE TX/ WINBOND JTAG debug
JP1
UART1_RXD
UART1_TXD
6,19 T20_WAKE#
+3VALW
+1.8VS
+VDD_CORE
+1.2VS_SM0
28 SYSTEM_RESET#
EC_TX_P80_DATA
AA20
M13
M14
M15
M16
N15
P15
P16
R16
T13
T15
T16
U13
U14
U16
U17
V17
V18
W20
Y19
Y20
Y21
C50
1
R94
1
yc
47P_0402_50V8J
3.3V
+3VS
@ R93
2
1
0_0402_5%
C53
100K_0402_5%
tt
10K_0402_5%
p:
VDD_KFUSE
C107
VDD_CORE_SENSE
GND_CORE_SENSE
VDD_CPU_SENSE
GND_CPU_SENSE
VDD_TP
GND_TP
VGND_TP
Y18
Y17
N9
P9
W9
Y10
AA11
4
Security Classification
2007/05/29
Issued Date
2008/05/29
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
ACES_87036-1001-CP
//
m
+VDD_FUSE
AB15
C103
47P_0402_50V8J
C101
VPP_KFUSE
SYSTEM_RESET#
EC_TX_P80_DATA
1
2
3
4
5
6
7
8
9
10
GND
GND
C52
0.1U_0201_6.3V6K
+VDD_CORE
AB14
C51
2
0_0805_5%
C102
VPP_FUSE
1
2
3
4
5
6
7
8
9
10
11
12
om
p.
su
C49
0.1U_0201_6.3V6K
0.1U_0402_25V4K
C48
4.7U_0603_6.3V6K
1
R89
1
47P_0402_50V8J
VDD_CORE_01
VDD_CORE_02
VDD_CORE_03
VDD_CORE_04
VDD_CORE_05
VDD_CORE_06
VDD_CORE_07
VDD_CORE_08
VDD_CORE_09
VDD_CORE_10
VDD_CORE_11
VDD_CORE_12
VDD_CORE_13
VDD_CORE_14
VDD_CORE_15
VDD_CORE_16
VDD_CORE_17
VDD_CORE_18
VDD_CORE_19
VDD_CORE_20
VDD_CORE_21
VDD_CORE_22
UART1_RXD
UART1_TXD
T20_WAKE#
/x
/
1.0~1.2V
V12
V13
4.7U_0603_6.3V6K
VDD_RTC_001
VDD_RTC_002
47P_0402_50V8J
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
A1
A2
A27
A28
AA10
AA13
AA16
AA19
AA21
AA8
AA9
AB2
AB24
AB27
AB5
AC19
AD10
AD13
AD16
AD19
AD22
AD7
AE2
AE25
AE27
AE4
AG1
AG10
AG13
AG16
AG19
AG2
AG22
AG25
AG27
AG28
AG4
AG7
AH1
AH2
AH27
AH28
B1
B10
B13
B16
B19
B2
B22
B25
B27
B28
B4
B7
D2
D25
D27
D4
E10
E13
E16
E19
E22
E7
G2
G24
G27
G5
H10
H13
H16
H18
H19
H21
H8
K2
K21
K24
K27
K5
K8
L11
L12
L13
L14
L15
L18
L8
M12
N13
N14
N16
N17
N2
N21
N24
N27
N5
N8
P17
P18
R11
R14
R15
R17
R18
T11
T12
T14
T17
T18
T2
T21
T24
T27
T5
T8
U11
U12
U15
U18
U21
V11
V14
V15
V16
V21
W2
W21
W24
W27
W5
W8
Y11
Y12
Y13
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
E
of
33
7,11 DDR_A_BS#[0..2]
7 DDR_A_D[0..15]
7 DDR_A_DQS[0..1]
7 DDR_A_DQS#[0..1]
7,11 DDR_A_MA[0..13]
D
7 DDR_A_DM[0..1]
+1.8VS
C55
0.1U_0402_10V7K
Close to U7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A2
L3
L7
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NU/RDQS
NC
NC
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
F9
E8
F8
F2
G2
G3
G1
G8
F7
G7
F3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
+1.8VS
Group1
+VRAM_VREFA
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
7
7
7
7
7
7
7
7
C54
0.1U_0402_10V7K
Close to U7
2
C57
C58
2
1U_0402_6.3V4Z
//
m
+1.8VS
C56
0.01U_0402_25V7K
@U4
@
U4
B7 DQS
A8 DQS#
B3 DM/RDQS
C8 DQ0
C2 DQ1
D7 DQ2
D3 DQ3
D1 DQ4
D9 DQ5
B1 DQ6
B9 DQ7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
E2
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
L3
L7
NU/RDQS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
F9
E8
F8
F2
G2
G3
G1
G8
F7
G7
F3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
HY5PS1G831CLFP-Y5_FBGA60~D
yc
HY5PS1G831CLFP-Y5_FBGA60~D
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1
DDR_A_D15
DDR_A_D10
DDR_A_D11
DDR_A_D8
DDR_A_D13
DDR_A_D14
DDR_A_D9
DDR_A_D12
/x
/
1
2
1
R96
1K_0402_1%
E2
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
om
p.
su
Group0
R95
1K_0402_1%
+VRAM_VREFA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
+1.8VS
C59
0.1U_0402_10V7K
C60
0.01U_0402_25V7K
R97
10K_0402_5%
C62
2
1U_0402_6.3V4Z
C63
0.1U_0402_10V7K
B
C61
0.1U_0402_10V7K
tt
p:
0.1U_0402_10V7K
M_ODT
2
+1.8VS
@U3
@
U3
B7 DQS
A8 DQS#
B3 DM/RDQS
C8 DQ0
C2 DQ1
D7 DQ2
D3 DQ3
D1 DQ4
D9 DQ5
B1 DQ6
B9 DQ7
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0
DDR_A_D0
DDR_A_D6
DDR_A_D2
DDR_A_D3
DDR_A_D7
DDR_A_D4
DDR_A_D5
DDR_A_D1
Security Classification
2008/12/22
Issued Date
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
T20 schematic
Date:
Sheet
1
10
of
33
7,10 DDR_A_BS#[0..2]
7 DDR_A_D[16..31]
7 DDR_A_DQS[2..3]
7 DDR_A_DQS#[2..3]
D
7,10 DDR_A_MA[0..13]
7 DDR_A_DM[2..3]
+1.8VS
C65
0.1U_0402_10V7K
Close to U7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
L3
L7
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
F9
E8
F8
F2
G2
G3
G1
G8
F7
G7
F3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
NU/RDQS
NC
NC
Group3
+VRAM_VREFA
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
+1.8VS
C68
C67
1
2
1U_0402_6.3V4Z
0.1U_0402_10V7K
Close to U7
E2
VREF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A2
L3
L7
NU/RDQS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
A9
C1
C3
C7
C9
A1
E9
H9
L1
E1
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
F9
E8
F8
F2
G2
G3
G1
G8
F7
G7
F3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSSDL
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
M_ODT
M_CLK_DDR0
M_CLK_DDR#0
M_CKE0
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
M_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
HY5PS1G831CLFP-Y5_FBGA60~D
+1.8VS
B
C70
0.1U_0402_10V7K
C69
0.01U_0402_25V7K
C72
C71
2
1U_0402_6.3V4Z
0.1U_0402_10V7K
C73
0.1U_0402_10V7K
tt
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
C64
0.1U_0402_10V7K
p:
C66
0.01U_0402_25V7K
7
7
7
7
//
m
HY5PS1G831CLFP-Y5_FBGA60~D
7
7
7
7
@ U6
B7 DQS
A8 DQS#
B3 DM/RDQS
C8 DQ0
C2 DQ1
D7 DQ2
D3 DQ3
D1 DQ4
D9 DQ5
B1 DQ6
B9 DQ7
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3
DDR_A_D28
DDR_A_D24
DDR_A_D30
DDR_A_D27
DDR_A_D29
DDR_A_D25
DDR_A_D31
DDR_A_D26
/x
/
E2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDL
om
p.
su
+1.8VS
@ U5
B7 DQS
A8 DQS#
B3 DM/RDQS
C8 DQ0
C2 DQ1
D7 DQ2
D3 DQ3
D1 DQ4
D9 DQ5
B1 DQ6
B9 DQ7
yc
Group2
+VRAM_VREFA
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2
DDR_A_D17
DDR_A_D23
DDR_A_D18
DDR_A_D21
DDR_A_D16
DDR_A_D22
DDR_A_D20
DDR_A_D19
Security Classification
2008/12/22
Issued Date
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
11
of
33
Change PWR to +3VS_S3 for eMMC cold boot issue (Pre-MP 7/8)
+VCORE_MMC
+2.85VS_LDO5
+VCORE_MMC
+VDDIO_MMC
+3VS_S3
+VDDIO_MMC
C74
2.2U_0603_6.3V6K
C76
2.2U_0603_6.3V6K
C75
0.1U_0402_10V7K
C77
0.1U_0201_6.3V6K
+VDDIO_N
4G SDIN4C2-8G
0.1U_0201_6.3V6K
Y4 must connector to Y3 & AA2 for with out use 3.5 mil trace
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
C98
2.2U_0603_6.3V6K
CMD
33_0402_1%
1 R99
2
HSMMC_CMD_R
W5
HSMMC_CMD
1
C95
2
C96
0.1U_0402_10V7K
HSMMC_CMD
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
H3
H4
H5
J2
J3
J4
J5
J6
HSMMC_DAT0_R
HSMMC_DAT1_R
HSMMC_DAT2_R
HSMMC_DAT3_R
HSMMC_DAT4_R
HSMMC_DAT5_R
HSMMC_DAT6_R
HSMMC_DAT7_R
VDDi
K2
EMMC_VDDI 1
2 63.4_0402_1%
HSMMC_CLK
HSMMC_CLK
/x
/
HSMMC_CLK_R
CLK
HSMMC_DAT[0..7] 6
HSMMC_DAT0
HSMMC_DAT1
HSMMC_DAT2
HSMMC_DAT3
HSMMC_DAT4
HSMMC_DAT5
HSMMC_DAT6
HSMMC_DAT7
R1315
NAND_CE0
NAND_CE1
NAND_RE#
NAND_ALE
NAND_CLE
NAND_WE#
NAND_WP#
+VDDIO_MMC
2
@ R1311
1
0_0402_5%
Q30B
4
SYS_RESET# 17,19,28
2N7002DW-7-F_SOT363-6
+VDDIO_NAND
R109 0_0603_5%
2
+VDDIO_N
+VDDIO_MMC
1
2
3
4
5
11
14
15
23
24
25
27
28
I/O[0]
I/O[1]
I/O[2]
I/O[3]
I/O[4]
I/O[5]
I/O[6]
I/O[7]
29
30
31
32
41
42
43
44
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
PRL
26
33
34
35
39
40
45
46
47
48
20
21
22
38
VCC1
VSS1
VCC2
VSS2
NAND_D0
NAND_D1
NAND_D2
NAND_D3
NAND_D4
NAND_D5
NAND_D6
NAND_D7
12
13
+VDDIO_N
37
36
Remove EN_VDDIO_MMC
3.3V
+VDDIO_NAND
+VDDIO_MMC
1
2
R119
R169 0_0603_5%
2
+VDDIO_N
100K_0402_5%
100K_0402_5%
R118
R117
100K_0402_5%
100K_0402_5%
R116
R115
100K_0402_5%
100K_0402_5%
R114
R113
100K_0402_5%
100K_0402_5%
R112
R111
10K_0402_5%
tt
R/B#
NC27
CE#
NC28
RE#
ALE
CLE
WE#
WP#
NAND01GW3B2AN6F_TSOP48
p:
//
m
yc
NAND_D[0..7]
7
6
9
10
8
17
16
18
19
100K_0402_5%
0.1U_0201_6.3V6K
SYS_RESET_eMMC#
NAND_CE0
NAND_CE1
NAND_RE#
NAND_ALE
NAND_CLE
NAND_WE#
NAND_WP#
SI@ U25
NAND_BSY#
NAND_BSY#
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
om
p.
su
C78
2
2
2
2
2
2
2
2
U1
U2
U3
U5
U6
U7
U10
U12
U13
U14
V1
V2
V3
V12
V13
V14
W1
W2
W3
W7
W8
W9
W10
W11
W12
W13
W14
Y1
Y3
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
AA1
AA2
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AE1
AE14
AG2
AG13
AH4
AH6
AH9
AH11
R101
R102
R103
R104
R105
R106
R107
R108
HSMMC_CMD_R
HSMMC_DAT0_R
HSMMC_DAT1_R
HSMMC_DAT2_R
HSMMC_DAT3_R
HSMMC_DAT4_R
HSMMC_DAT5_R
HSMMC_DAT6_R
HSMMC_DAT7_R
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
1
1
1
1
1
1
1
Y2 must connector to AA2 for with out use 3.5 mil trace
Y5 must connector to Y6 & Y7 & AA7
for with out use 3.5 mil trace
Change to 3 mil for Toshiba eMMC 4.4
interface.(PVT 2nd build)
5
U8
R10
P5
M7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
A6
A9
A11
B2
B13
D1
D14
H1
H2
H6
H7
H8
H9
H10
H11
H12
H13
H14
J1
J7
J8
J9
J10
J11
J12
J13
J14
K1
K3
K5
K7
K8
K9
K10
K11
K12
K13
K14
L1
L2
L3
L4
L12
L13
L14
M1
M2
M3
M5
M8
M9
M10
M12
M13
M14
N1
N2
N3
N10
N12
N13
N14
P1
P2
P3
P10
P12
P13
P14
R1
R2
R3
R5
R12
R13
R14
T1
T2
T3
T5
T12
T13
T14
1
R1313 0_0402_5%
AA6
AA4
Y5
Y2
K4
U7
k6
W4
Y4
AA3
AA5
1
0_0402_5%
M6
N5
T10
U9
2
@R98
@
R98
VCC
VCC
VCC
VCC
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
12
of
33
+3VS
R121
FBMA-10-100505-221T_0402
R122
FBMA-10-100505-221T_0402
LVDS_SHTDN#
LCD_DE
32
30
25
31
17
SHTDN#
D26
D23
CLKIN
CLKSEL
R126
10K_0402_5%
1 : Rising edge
0 : Falling edge
D24
D25
Y1P
Y1M
45
46
LVDSA1
LVDSA1#
+3VS
Y2P
Y2M
41
42
Y3P
Y3M
37
38
CLKOUTP
CLKOUTM
39
40
GND
GND
GND
GND
GND
PLLGND
PLLGND
LVDSGND
LVDSGND
LVDSGND
5
13
21
53
29
33
35
36
43
49
LVDSACLK
LVDSACLK#
C85
LVDSA1#
LVDSA1
LVDSA2#
LVDSA2
C82
4.7U_0603_6.3V6K
2
2
C83
1U_0402_6.3V4Z
0.01U_0402_25V7K
p:
+LCD_INV
1
1
1
1
2
2
2
2
LCD_BL_EN
INVT_PWM_R
+LCD_INV
R127
10K_0402_5%
+3VS_LVDS_CAM
USB3_N2
USB3_P2
DMIC_CLK
DMIC_DAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
34
33
MGND4
MGND3
32
31
MGND2
MGND1
1 C87
LVDS_ACLK#
LVDS_ACLK
R1261 22_0402_5%
2
1
R128 @
1
+LCD_VDD
C86
0.1U_0402_10V6K
0_0402_5%
0_0402_5%
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2 0_0402_5%
2 0_0402_5%
1.5A
B+
R292
R293
R294
R295
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I-PEX_20143-030E-20F~D
CONN@
2 L3
1
0_0805_5%
R123
1
R124
1
2 0_0402_5%
2 0_0402_5%
R296 1
R297 1
LCD_BL_EN
+LCDVDD_R
+LCDVDD_R
LVDSACLK#
LVDSACLK
//
m
C84
0.01U_0402_25V7K
8,17,18 GEN1_I2C_SCL_3V3
0.1U_0402_10V6K8,17,18 GEN1_I2C_SDA_3V3
LVDSA0#
R290 1
LVDSA0
R291 1
+VDD_LVDS
C81
0.01U_0402_25V7K
JLVDS1
C80
LVDSA2
LVDSA2#
SN75LVDS83DGGRG4_TSSOP56
+VDD_BIO
680P_0402_50V7K
1
1
C79
C183 1
0_0402_5%
2
+3VS
Sourcer request
L4
16 USB3_HUB_P2
16 USB3_HUB_N2
1
4
2
3
USB3_P2
USB3_N2
0_0402_5%
2
@ U24
6
C94
0.1U_0402_10V6K
LCD_PCLK
+3VS
PD#OE
FS
CLKIN
GND
CLKOUT
CLKOUT#
@ R279
4.7K_0402_5%
8
@ R274
7
2
15K_0402_5%
6
5
LCD_PCLK_OUT
R271
4.7K_0402_5%
@ R281
4.7K_0402_5%
R269
4.7K_0402_5%
@ R270
4.7K_0402_5%
PCS3PS850BHG-08CR_TDFN8_2X2
PD#OE
FS
R272 @
4.7K_0402_5%
C184
1
R3
LCD_PCLK
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
DLY_CTRL
SSEXTR
47P_0402_50V8J
VDD
CLKIN#
W=20mils
0.1U_0402_10V6K
1
2
C93
C270
+3VS
@ C273
0.1U_0402_10V6K
C271
C269
68P_0402_50V8K
2200P_0402_50V7K
C268
0.1U_0402_10V7K
68P_0402_50V8K
C267
2200P_0402_50V7K
+3VS_LVDS_CAM
+3VS
C266
R136
100K_0402_5%
R135
0_0603_5%
1
2
0.1U_0402_10V7K
+LCD_VDD
W=60mils
C265
68P_0402_50V8K
C264
INVT_PWM_R
1
R132
1
R133 @
R1265
100K_0402_5%
2
20_0402_5%
2
20_0402_5%
INVT_PWM
2200P_0402_50V7K
C263
0.1U_0402_10V7K
19
3
1
3
4
Q11
AO3413_SOT23
C90
680P_0402_50V7K
tt
6 2
LCD_BL_PWM
12
2
47K_0402_5% 1
C92
0.01U_0402_16V7K
2
Q6B
2N7002DW-7-F_SOT363-6
C89
0.1U_0402_25V6
0.1U_0402_10V6K
2
C91
1
R134
6 EN_VDD_PNL
W=60mils
+3VS
R131
100K_0402_5%
Q6A
2N7002DW-7-F_SOT363-6
C88
68P_0402_50V8J
+3VS
R130
150_0603_5%
+LCD_VDD
WCM-2012-900T_0805
L5 2
1
FBMA-L11-201209-221LMA30T_0805
R273
4.99_0402_1%
27
28
LCD_PCLK_OUT
1
2
+VDD_BIO
R125
10K_0402_5%
LCD_HSYNC
LCD_VSYNC
LVDSA0
LVDSA0#
LVDS_SHTDN#
D15
D18
D19
D20
D21
D22
D16
D17
47
48
6 LVDS_SHTDN#
6
LCD_DE
15
19
20
22
23
24
16
18
Y0P
Y0M
LCD_HSYNC
LCD_VSYNC
LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05
+VDD_LVDS
6
6
D7
D8
D9
D12
D13
D14
D10
D11
+VDD_BIO
/x
/
LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05
4
6
7
11
12
14
8
10
1
9
26
44
34
47P_0402_50V8J
6
6
6
6
6
6
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11
Vcc
Vcc
Vcc
LVDSVcc
PLLVcc
om
p.
su
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11
D0
D1
D2
D3
D4
D6
D27
D5
4.7U_0805_10V4Z
6
6
6
6
6
6
51
52
54
55
56
3
50
2
yc
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
U8
6
6
6
6
6
6
LVDS Bridge
+3VS
LCD_PCLK_OUT
1
0_0402_5%
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
13
of
33
+3VS
+3VS
@R138
@
R138
2.2K_0402_5%
DDC_SDA_3P3
HDMICLK
0_0402_5%
20_0402_1%
2
WCM-2012-900T_0805
4 4
3 3
@ L6
R140
1
HDMI_TXCN
6 HDMI_TXCN
6 HDMI_TXD0P
R141
1
HDMI_TXD0P
20_0402_1%
2
+5VS
20_0402_1%
2
D4
RB161M-20_SOD123-2
//
m
1
HDMI_R_CK-
HDMI_R_D0+
R146
tt
6 HDMI_TXD2P
HDMI_R_D2HDMI_R_D1+
HDMI_R_D1HDMI_R_D0+
HDMI_R_D0HDMI_R_CK+
HDMI_R_CK-
HDMICLK
HDMIDAT
2 20_0402_1%
HDMI_R_D0-
2
20_0402_1%
HDMI_R_D1+
R145 2
HDMI_HPD
HDMI_DET
1K_0402_5%
WCM-2012-900T_0805
6 HDMI_TXD1N
D2+
D2_shield
D2D1+
D1_shield
D1D0+
D0_shield GND0
D0GND1
CK+
GND2
CK_shield GND3
CKCEC
Reserved
SCL
SDA
DDC/CEC_GND
+5V
HP_DET
20
21
22
23
ACON_HMR2A-AK120C
HDMI_TXD1P
R144 1
p:
6 HDMI_TXD1P
HDMI_TXD0N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
@ L7
6 HDMI_TXD0N
CONN@
JHDMI1
HDMI_R_D2+
+5VS_HDMI
WCM-2012-900T_0805
4 4
3 3
1
+5VS_HDMI
HDMI Connector
HDMI_R_CK+
yc
R142
1
2
1.5K_0402_5%
R143
1
2
1.5K_0402_5%
R139
1
HDMI_TXCP
6 HDMI_TXCP
om
p.
su
0_0402_5%
C97
0.1U_0402_10V6K
@ Q4B 2N7002DW-7-F_SOT363-6
R1255
R1256
1
2
1
2
@ C290
@C290
220P_0402_25V8J
R147
100K_0402_5%
2
DDC_SCL_3P3
HDMIDAT
/x
/
6 DDC_SCL_3P3
@ Q4A 2N7002DW-7-F_SOT363-6
6 DDC_SDA_3P3
@R137
@
R137
2.2K_0402_5%
@ L8
HDMI_TXD1N
R148 1
2
20_0402_1%
HDMI_R_D1-
HDMI_TXD2P
R149 1
2
20_0402_1%
HDMI_R_D2+
4
1
WCM-2012-900T_0805
4
3 3
1
@ L9
6 HDMI_TXD2N
HDMI_TXD2N
R150 1
2 20_0402_1%
HDMI_R_D2-
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Sheet
14
of
33
SI@
C100
0.1U_0402_10V6K
+3VS_WIFI
+3VS_WiFi
SI@ 1
1
C99
R151
2
+3VS_S3
0_0603_5%
SI@
4.7U_0603_6.3V6K 2
SI@
R1247
10K_0402_5%
2
1
@ R1250
XCLKO_T20 2
1 CLK_32K_OUT_Q
2
0_0402_5%
1
@
0.01U_0402_16V7K
C304
SI@
C262
8
8
8
8
SDIO2_DAT0
SDIO2_CLK
SDIO2_DAT1
SDIO2_CMD
CLK_32K_OUT_R
DAP4_DIN
DAP4_SCLK
SDIO2_DAT0
SDIO2_CLK
SDIO2_DAT1
SDIO2_CMD
R1251
1
SI@ 0_0402_5%
DAP4_DIN
DAP4_SCLK
2
BT_WAKEUP
UART3_CTS#
UART3_TXD
8 UART3_CTS#
8 UART3_TXD
BT_WAKEUP
SI@
C106
0.01U_0402_16V7K
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
+3VS_WIFI
+3VS_WIFI
R1302
0_0402_5%
SI@ Q24
19 XCLKO_T20
+1.8VS
0.01U_0402_16V7K
BSS138_NL_SOT23-3
JMIN1
CLK_32K_OUT
R1268
100K_0402_5%
DAP4_DOUT
DAP4_FS
UART3_RTS#
UART3_RXD
SDIO2_DAT2 8
SDIO2_DAT3 8
DAP4_DOUT
DAP4_FS
BT_RST# 8
UART3_RTS# 8
UART3_RXD 8
WF_RST# 8,20
SDIO2_DAT2
SDIO2_DAT3
/x
/
1
+1.8VS
+3VS_WIFI
+3VS_WIFI
C309 .01U_0402_16V7K
1
2
SI@ C104
0.1U_0402_10V6K
+3VS_S3
C308 .01U_0402_16V7K
1
2
om
p.
su
+1.0VS_SM1
+3VS
SI@ C105
0.1U_0402_10V6K
BELLW_80019-1021
CONN@
R153
2
JMIN2
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
+3VS_WWAN
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
+UIM_PWR
3G@ R1226
1
2 33_0402_5%
tt
C189
3G@
1
2
W_DISABLE#_C
1
2
@ R154
0_0402_5%
PEX_RST0# 8
3G@
W_DISABLE#
CM2
10P_0402_50V8J
0_0402_10V7K
@ R1319
100K_0402_5%
1
+3VS_WWAN
UIM_CLK_R
p:
1
3
5
7
9
11
13
15
//
m
1
3
5
7
9
11
13
15
0_0805_5%
yc
0_0805_5%
PEX_WAKE#
R1318
+3VALW
+3VS_WWAN
3G@
1
USB3_HUB_N3 16
USB3_HUB_P3 16
WW_LED#
BELLW_80019-1021
RFU
UIM_VPP
I/O
UIM_DATA
RFU
USB3_HUB_N4
1
NC
NC
10
2
HB_4210826-SINR02
CONN@ DAN217_SC59
3
DM2 @
DAN217_SC59
@ DM3
DAN217_SC59
@DM4
@
DM4
1
3G@
+UIM_PWR
3G@
1
C110
2
10U_0805_10V4Z
3G@
1
C111
3G@
2
0.1U_0402_16V4Z
1
C112
@ C185
2
0.01U_0402_16V7K
@
C186
@ CM4
22P_0402_50V8J
Issued Date
2009/12/22
Deciphered Date
Title
Date:
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
@
C187
USB3_HUB_N4 16
Security Classification
CM3
10P_0402_50V8J
C109
0.1U_0402_16V4Z
39P_0402_50V8J
CLK
USB3_HUB_P4
@ RM1
4.7K_0402_5%
5
2
VPP
RST
UIM_CLK_R
16 USB3_HUB_P4
3G@
GND
UIM_RST
3G@DM1
3G@DM1
RLZ20A_LL34
1
3G@CM1
3G@CM1
0.1U_0402_16V4Z
VCC
39P_0402_50V8J
1
JGSIM2
+UIM_PWR
+UIM_PWR
+3VS_WWAN
39P_0402_50V8J
+UIM_PWR
CONN@
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
15
of
33
+3VS_HUB1
@ R152
1
R156
8
8
HS_IND/CFG_SEL1
TEST
27
VBUS_DET
USBUP_DM
USBUP_DP
C124
15P_0402_50V8J
USBDN3_DM/PRT_DIS_M3
USBDN3_DP/PRT_DIS_P3
PRTPWR3
OCS3_N
6
7
18
19
USBDN4_DM/PRT_DIS_M4
USBDN4_DP/PRT_DIS_P4
PRTPWR4
OCS4_N
8
9
20
21
VDDIO
VBUS
21
VDD1.8
VBAT
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
VDD3.3
DM
USB2_DN
USB2_DP
8 ULPI_RESET#
8 DAP_MCLK2_R
12
22
23
24
DP
R1227
1
1
PR@ R1228
CPEN
PR@ R178
8.06K_0402_1%
GND_FLAG
25
USB3315C-CP-TR_QFN24_4X4
USB2_DN_R
USB2_DP_R
0_0402_5%
2
+3VS_HUB2
1
USB2_RESET#
PR@C128
PR@C128
PR@C133
PR@
C133 1
R280
0_0805_5%
PR@
R170
PR@
R171
PR@
R172
PR@ R173
15
36
PR@
U10
5
10
23
29
USB2_XTAL1
33
USB2_XTAL2
32
2 100K_0402_5%
25
1
1
1
2 100K_0402_5%
2 100K_0402_5%
2 100K_0402_5%
24
22
28
USB2_RESET#
26
PR@
R195
100K_0402_5%
PR@C130
PR@
C130 1
R176
VDD33CR
VDD33PLL
VDDA33
VDDA33
VDD33
VDDA33
+3VS
PR@
XTAL1/CLKIN
PR@C127
PR@
C127
PR@R192
PR@
R192
1
2
2
0_0603_5%
PR@
R1289 0_0402_5%
1
2 USB2_DN_H
1
2 USB2_DP_H
R1290 0_0402_5%
USB2_XTAL2
1M_0201_1%
PR@Y3
PR@Y3
1
2
24MHZ_12PF_X5H024000DC1H
2 0.1U_0402_16V4Z
PR@C139
PR@C139
15P_0402_50V8J
2
4.7U_0603_6.3V6K
2 0.1U_0402_16V4Z
PR@
C140
15P_0402_50V8J
2
4.7U_0603_6.3V6K
PR@
R175
RBIAS
USBDN1_DM/PRT_DIS_M1
USBDN1_DP/PRT_DIS_P1
PRTPWR1
OCS1_N
35
2
12K_0402_1%
R1287 0_0402_5%
USB2_HUB_N1
1
2
USB2_HUB_P1
1
2
R1288 0_0402_5%
1
2
12
13
USB2_HUB_N1_R
USB2_HUB_P1_R
3
4
16
17
USB2_HUB_N2
USB2_HUB_P2
WiFi
XTAL2
HS_IND/CFG_SEL1
SCL/SMBCLK/CFG_SEL0
SDA/SMBDATA/NON_REM1
SUSP_IND/LOCAL_PWR/NON_REM0
USBDN2_DM/PRT_DIS_M2
USBDN2_DP/PRT_DIS_P2
PRTPWR2
OCS2_N
BT
RESET_N
JP2
11
TEST
27
VBUS_DET
USBDN3_DM/PRT_DIS_M3
USBDN3_DP/PRT_DIS_P3
PRTPWR3
OCS3_N
+3VS_BT_WIFI
USB2_HUB_P2
USB2_HUB_N2
BT_WAKEUP_R
6
7
18
19
30
31
USBUP_DM
USBUP_DP
BT_WAKEUP
R1229 PR@
0_0402_5%
BT_WAKEUP_R
1
2
WF_PWDN#
R1230 PR@
0_0402_5%
WF_PWDN#_R
1
2
1
2
3
4
5
6
7
8
9
10
USB2_HUB_P1
USB2_HUB_N1
WF_PWDN#_R
+3VS_BT_WIFI
USBDN4_DM/PRT_DIS_M4
USBDN4_DP/PRT_DIS_P4
PRTPWR4
OCS4_N
8
9
20
21
11
12
USB2512B-AEZG_QFN36_6X6
1
2
3
4
5
6
7
8
9
10
GND1
GND2
ACES_87213-1000G
USB2_DN_R
USB2_DP_R
@R1291
@
R1291 0_0402_5%
@ R1292 0_0402_5%
USB2_HUB_N1
1
2 USB2_WiFi_N1 1
2
@R1293
@
R1293 0_0402_5%
@ R1294 0_0402_5%
USB2_HUB_P1
1
2 USB2_WiFi_P1 1
2
CONN@
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
USB2_XTAL1
10K_0402_5%
USB2_DN_R
USB2_DP_R
0_0402_5%
R289
+3VS
PR@
C144
2.2U_0603_6.3V6K
0_0402_5%
2
PR@ 1
C138
PR@ R299
10K_0402_5%
R174
1
7
USB3_HUB_N1_R
+3VS_HUB2
USB3_HUB_N4 15
USB3_HUB_P4 15
+3VS_HUB2
ID
CLKOUT
RESETB
REFCLK
RBIAS
100K_0402_5%
PR@
STP
NXT
DIR
+3VS
37
ULPI_CLK_R
20
18
19
+3VS_HUB2 2
8
9
10
11
13
14
15
16
ULPI_STP
ULPI_NXT
ULPI_DIR
17
USB3_HUB_P1_R
SIM card
+3VS_HUB2
0_0402_5%
2
ULPI_D7
ULPI_D6
ULPI_D5
ULPI_D4
ULPI_D3
ULPI_D2
ULPI_D1
ULPI_D0
ULPI_CLK_R
@ R167
1
Thermal Slug(VSS)
PR@ U12
ULPI_STP
ULPI_NXT
ULPI_DIR
USB3_HUB_N4
USB3_HUB_P4
yc
+VDDIO_BB
R1321
1
ULPI_D[0..7]
p:
tt
PR@C146
PR@
C146
0.1U_0402_16V4Z
PR@C145
PR@
C145
0.1U_0402_16V4Z
+1.8VS
R1320 0_0402_5%
1
2
USB port
4.7U_0603_6.3V4
2
2
@
C208
PR@ C141
@
C193
0.1U_0402_16V4Z
PR@C142
PR@
C142
@ C192
PR@
C275
10P_0402_50V8J
39P_0402_50V8J
PR@
R179
10_0402_5%
39P_0402_50V8J
//
m
1
0.1U_0402_16V4Z
PR@C143
+3VS_BT_WIFI
USB3_HUB_N1
USB3_HUB_P1
WCM-2012-900T_0805
Webcam
USB2514B-AEZG_QFN36_6X6
39P_0402_50V8J
37
0.1U_0402_16V4Z
C123
15P_0402_50V8J
USB1_ID1
USB1_ID1
4.7U_0603_6.3V4
11
24MHZ_12PF_X5H024000DC1H
2
0.1U_0402_16V4Z
PR@C136
RESET_N
30
31
0_0402_5%
2
L18
0.1U_0402_16V4Z
PR@C121
USB3_DN
USB3_DP
USB3_DN
USB3_DP
USB3_HUB_N2 13
USB3_HUB_P2 13
ACES_85201-1205N
CONN@
@ R159
1
USB3_HUB_P1_L
0.1U_0402_16V4Z
PR@C129
8
8
GND
GND
26
Thermal Slug(VSS)
1M_0201_1%
Y2
2
WWAN
3
4
16
17
USBDN2_DM/PRT_DIS_M2
USBDN2_DP/PRT_DIS_P2
PRTPWR2
OCS2_N
10K_0402_5%
0_0402_5%
1
VDD18
VDD18PLL
14
34
15
36
VDD33CR
VDD33PLL
SCL/SMBCLK/CFG_SEL0
SDA/SMBDATA/NON_REM1
SUSP_IND/LOCAL_PWR/NON_REM0
USB_XTAL2
SI@
R204 Reserve
R158
1
USB3_HUB_N3 15
USB3_HUB_P3 15
0.1U_0402_16V4Z
PR@C135
USB_XTAL1
1
2
12
13
SI@ R199
2
12K_0402_1%
0.1U_0402_16V4Z
PR@C137
R166
+3VS_HUB1 2
USBDN1_DM/PRT_DIS_M1
USBDN1_DP/PRT_DIS_P1
PRTPWR1
OCS1_N
14
34
35
PR@C134
USB_RESET#
24
22
28
R161
RBIAS
0.1U_0402_16V4Z
PR@C132
2 100K_0402_5%
2 100K_0402_5%
2 100K_0402_5%
13
14
XTAL2
25
1
2
3
4
5
6
7
8
9
10
11
12
32
USB_EN#
+USB1_VBUS_R
EVENT_LED
1
2
3
4
5
6
7
8
9
10
11
12
4.7U_0603_6.3V6K
/x
/
USB_XTAL2
2 100K_0402_5%
0_0402_5%
2
C125
XTAL1/CLKIN
USB1_DP_R
USB_EN#
8 +USB1_VBUS_R
20 EVENT_LED
om
p.
su
R163 1
R164 1
R160 1
5
10
23
29
VDDA33
VDDA33
VDD33
VDDA33
R165 1
+3VS_HUB1
33
4.7U_0603_6.3V6K
2 0.1U_0402_16V4Z
USB_XTAL1
JUSB1
USB1_DN_R
C122
C126 1
U9
@ R157
1
2
2
USB1_DP
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C131
WCM-2012-900T_0805
USB_RESET#
USB1_DN
0_0603_5%
0_0402_5%
C120 1
D
0_0402_5%
2
4.7U_0603_6.3V4
+5VALW
PR@ L17
0.1U_0402_16V4Z
C119
1
0.1U_0402_16V4Z
C118
R162
100K_0402_5%
0.1U_0402_16V4Z
C117
0.1U_0402_16V4Z
C116
0.1U_0402_16V4Z
C115
+3VS_HUB1
0.1U_0402_16V4Z
C114
C113
+3VS_HUB1
+3VS
VDD18
VDD18PLL
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
16
of
33
+3VS_VDD
+3VS_VDD
+3VS_AVDD
+3VS_VDD
0.1U_0402_16V4Z
C153
1U_0603_16V7_X7R 0.1U_0402_16V4Z
2
2
C152
C156
10U_0805_10V4Z
C150 1
+3VS_VDD
U14
@ Q9A
@Q9A
1
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 1
C310
0.47U_0603_6.3V6K
8,13,18 GEN1_I2C_SCL_3V3
8,13,18 GEN1_I2C_SDA_3V3
DMIC_DAT
FBMA-L10-160808-301LMT 0603
+3VS_AVDD
C222
DAP1_SCLK_R
2
C276
10P_0402_50V8J
ALC5632-GRT_QFN48_7X7
2 0.1U_0402_16V4Z
C236 1
2 0.1U_0402_16V4Z
Reserve resistor.
2
1
R185
100K_0402_5%
@ R196
100K_0402_5%
HP_OUTL
HP_OUTR
C166 150U_B2_6.3VM_R35M
HP_OUT_R
1
2
HP_OUT_L
2
1
R1323 0_0402_5%
2
1
R1324 0_0402_5%
L12 BLM18BD601SN1D_0603
HP_OUT_R_L
1
2
JHP1_3
HP_L_OUT
3
1
L13 BLM18BD601SN1D_0603
HP_OUT_R_R
1
2
HP_R_OUT
5
2
6
7
L14
EXT_MIC
BLM18BD601SN1D_0603
2
JHP1_4
4
SINGA_2SJ-C960-002
CONN@
PSOT24C_SOT23-3
D19
2 0.01U_0402_16V7K
C171
0.01U_0402_16V7K
U15
16
6
15
2
3
NC
12
SHUTDOWN
19
EC_MUTE#
VDD
PVDD
PVDD
GAIN0
C172 1
2 0.47U_0603_10V7K
SPK_OUT-
LIN-
SPKOUT+
C173 1
2 0.47U_0603_10V7K
SPK_OUT+
17
RIN-
C178 1
2 0.47U_0603_10V7K
LIN+
C179 1
2 0.47U_0603_10V7K
RIN+
HP_DET
R186
10K_0402_5%
+3VS
LOUT-
SPKL-
ROUT-
14
SPKR-
LOUT+
SPKL+
ROUT+
18
SPKR+
GND
GND
GND
GND
GND
1
11
13
20
21
GAIN1
SPKOUT-
HP_DET
1
C170
0.1U_0402_16V4Z
p:
21.6dB
tt
C169
10U_0805_10V4Z
1
C168
R183
100K_0402_5%
15.6dB
C235 1
@R182
@
R182
100K_0402_5%
BYPASS
EC_MUTE# 19
SPKRSPKR+
SPKLSPKL+
L19
L20
L21
L22
1
1
1
1
2
2
2
2
10
FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603
1
1
2
2
D5 @
PSOT24C_SOT23-3
C180
0.47U_0603_10V7K
SPK_RSPK_R+
SPK_LSPK_L+
SPEAKER
CONN@
JSPR1
SPK_RSPK_R+
1
2
3
4
D6 @
PSOT24C_SOT23-3
1
TPA6017A2PWPR_TSSOP20
A
10dB
+3VS_AVDD
0_0402_5%
2
2
+5VS
6dB
C234
1
15.6 dB
Av
MICBIAS
VREF
C162
1
2
4.7U_0603_6.3V6M
C177
330P_0402_50V7K
0.1U_0402_16V4Z
0_0805_5%
+5VAMP
C167
+3VS_VDD
R180
1
0.1U_0402_16V4Z
SPK_LSPK_L+
+5VS
TI TPE6017A2
GAIN1
C165 150U_B2_6.3VM_R35M
GAIN0
2
C158
HP_OUTL
2 MICBIAS
3.9K_0402_5%
C224
4.7U_0603_6.3V6K
T20_Codec 8
C176
330P_0402_50V7K
C175
330P_0402_50V7K
2
2
1
C274
10P_0402_50V8J
T20_Codec
C164
SPKOUT+
SPKOUT-
R1276
1
BYP
C157
SHDN#
0_0402_5%
HP_C_Depop C161 1
21U_0603_16V7_X7R
HP_OUTR
1U_0603_16V7_X7R
R181
10_0402_5%
C163
R90
10_0402_5%
@ C223
R252
680_0402_5%
R1277
T20_Codec_R
0.1U_0402_16V4Z
DAP_MCLK1_R
1
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
1
1
EXT_MIC
OUT
GND
DMIC_CLK_L
GEN1_I2C_SCL_3V3
GEN1_I2C_SDA_3V3
DMIC_CLK_L
DMIC_DAT
IN
DMIC_CLK
DAP1_FS
DAP1_FS
C174
330P_0402_50V7K
L16
DAP1_DIN
8 DAP1_DIN
Change to 0.47UF
for Bobo noise(Pre-MP)
DAP1_DOUT
DAP1_SCLK_R
DAP1_DOUT
DAP1_SCLK_R
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Thermal
GPIO5/VSADC
GPIO4/VSDAC
GPIO3/VSLRCK
GPIO2/IRQ
GPIO1/VBCLK
HPVDD
HP_C_Depop
HP_OUT_R
HPGND
HP_OUT_L
SPKVDD
SPK_OUTN
SPK_OUT
NC
SPKGND
NC
AUX_OUTN
AUX_OUT
MIC2N
MIC2P
MICBIAS
VREF
AGND1
AVDD1
yc
DBVDD
MCLK
NC
DGND1
SDAC
BCLK
DGND2
SADC
DCVDD
SDALRCK
RSTN
SADLRCK
SCL
SDA
DMIC_CLK
DMIC_DAT
AVDD2
AGND2
PHONEP
PHONEN
MIC1P
MIC1N
LINE_IN_L
LINE_IN_R
(3.3V)
300mA
U13
G9191-330T1U_SOT23-5 1
//
m
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAP_MCLK1_R
DAP_MCLK1_R
20 EN_VDD_3V3
om
p.
su
1
2
5
@ Q9B
SYS_RESET# 4
1U_0603_16V7_X7R
C160
C159
SYS_RESET#
2
0.1U_0402_16V4Z
+3VS_VDD
9,28
W=40Mil
+5VALW
+3VS_AVDD
0.1U_0402_16V4Z
2
1
BLM18BD601SN1D_0603
2.2U_0603_6.3V6K
+3VS_AVDD
L11
CODEC POWER
C151
/x
/
2
+3VS
C155 1U_0603_16V7_X7R
C154 0.1U_0402_16V4Z
L10
2
1
BLM18BD601SN1D_0603
+3VS
1
2
GND
GND
ACES_88231-02001
CONN@
JSPL1
1 1
2 2
3
4
GND
GND
ACES_88231-02001
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
17
of
33
+3VS_ACL_IO
@ R191
1
2
0_0603_5%
C181
0.1U_0402_16V4Z
+3VS_ACL
@
D7
+3VS_ACL
ACCELEROMETER (ST)
+3VS
C182
10U_0805_6.3V6M
0.4mA
RB751V_SOD323
@ U16
9
VDD
SCK
INT
SDI
SDO
10
reserved
GND
reserved
GND
11
GND
12
ACCELERO_INT# 6
Light sensor
/x
/
+VDDIO_VI
4
11
18
+V_SDIO_0
+V_SDIO_0
8 SDIO1_CLK_R
+V_SDIO_0
SDIO1_CD#
PEX_RST0#
+3VS
PEX_RST0#
EN
C301 APE8805A-33Y5P_SOT23-5
1U_0402_6.3V4Z
1
2
R1260 0_0402_5%
12
13
14
15
PEX_RST0#
R1309
0_0402_5%
7
8
9
10
11
@ R155
100K_0402_5%
1
C303
2 1U_0402_6.3V4Z
+V_SDIO_0
D3
CMD
VSS1
VDD
CLK
VSS2
D0
D1
D2
WP
CD
R200
R201
R208
100K_0402_5%
R202
R203
SDIO1_DAT1
SDIO1_DAT0
SDIO1_DAT3
SDIO1_DAT2
GND1
GND2
GND3
GND4
SDIO1_CLK_R
PROCO_SDC009-A0-00K0
R209
100K_0402_5%
@
R184
0_0402_5%
1
R1305
100K_0402_5%
SDIO1_CLK_R
IN
2
8 EN_VDDIO_SD
GND
OUT
IN
1
2
3
4
5
6
SDIO1_DAT0
SDIO1_DAT1
SDIO1_DAT2
SDIO1_WP
SDIO1_CD#_R
8 SDIO1_DAT0
8 SDIO1_DAT1
8 SDIO1_DAT2
6 SDIO1_WP
SDIO1_CD#
1
2
@R1259
@
R1259 0_0402_5%
U27
1
JCR1
SDIO1_DAT3
SDIO1_CMD
8 SDIO1_DAT3
8 SDIO1_CMD
tt
ST19NP18ER28PVLI_TSSOP28
R251
10K_0402_5%
2 in 1 Card reader
SI@
5
8
12
13
14
19
25
GND1
GND2
GND3
2
3
ISL29011IROZ-T7_ODFN8_2P1X2
LPCPD#
LCLK
LFRAME#
LRESET#
SERIRQ
PP
LIGHT_INT
GEN1_I2C_SDA_3V3
GEN1_I2C_SCL_3V3
NC_5
NC_8
NC_12
NC_13
NC_14
NC_19
NC_25
SI@
1
8
7
6
5
TPM_RESET#
B
28
21
22
16
27
7
VNC
LAD0
LAD1
LAD2
LAD3
TPM_VCC
VDDD IRDR
VDDA
INT#
GND
SDA
REXT
SCL
GND PAD
yc
26
23
20
17
10
24
C188
10U_0805_6.3V6M
VPS_10
VPS_24
//
m
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
TPM_DATA#
TPM_ACCPCMD
1
2
6
9
15
TPM_VCC
p:
GEN1_I2C_SDA_3V3
GEN1_I2C_SCL_3V3
SI@ R277
10K_0402_5%
SI@
U26
+VDDIO_VI
SI@
R278
0_0603_5%
C191
0.1U_0402_16V4Z
1
2
3
4
9
om
p.
su
SI@
R275
499K_0402_1%
TPM
SI@
U17
+VDDIO_VI
BMA150_LGA12
+3VS_ACL
ACCELERO_INT#
GEN1_I2C_SDA_3V3
GEN1_I2C_SCL_3V3
+3VS_ACL_IO
CSB
1
1
8,13,17 GEN1_I2C_SDA_3V3
VDDIO
10K_0402_1%
2 G_CS#
2
2
8,13,17 GEN1_I2C_SCL_3V3
R194 @
1
+3VS_ACL
+3VS
+VDDIO_NAND
2008/12/22
Security Classification
@
C194
10P_0402_50V8J
2009/12/22
Deciphered Date
Title
G SENSOR/BT/Light Sensor/CR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Document Number
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
18
of
33
+3VALW_EC
1
Reverse +3VL to EC
@ R1273
+3VALW_EC
KSO1
KSO2
+3VALW
+3VALW_EC
R250
LID_SW#
@ R1296
0_0402_5%
1
10K_0402_5%
+3VALW
GMI_AD18_D
1
R216
2.2K_0402_5%
2 @
13
C225
2
ON/OFF#
PWR_LED#
21 ON/OFF#
PWR_LED#
NC
OSC
32.768KHZ_12.5PF_9H03200413
1
R218
@
R1234
20M_0402_5%
100K_0603_5%
XCLKO
122
123
8.2K+/-5%
0.216V
0.250V
0.289V
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
AVCC
PS2 Interface
68
70
71
72
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
@ C292
+3VLP
+3VALW
2
R1322
0_0603_5%
ACOFF
100P_0402_50V8J100P_0402_50V8J
1
1
GPIO
SM Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
119
120
126
128
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
XCLK1
XCLK0
V18R
VCC
CS#
SYS_RESET#
ACIN
7,12,17
IREF
CHGVADJ
C195
100P_0402_50V8J
IREF
CHGVADJ
FRD#SPI_SO
C200
100P_0402_50V8J
SPI_CLK_R
+5VALW
R223
0_0402_5%
R1243
USB_OC# 1
2
4.7K_0402_5%
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
R220
USB_OC#
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_LOW_LED#
USB_OC# 16
FSTCHG
BATT_FULL_LED#
20
2
10K_0402_5%
EC_RESMUE
EC_RESMUE
28
2
1
R215 20K_0402_5%
BATT_LOW_LED#
ACIN
C231
10P_0402_50V8J
2 SPI_CLK_R
33_0402_1%
20,24
EC_RESMUE_R
HDMI_HPD_R
EC_ON
EC_ON
USB1_ID2
110
112
114
115
116
117
118
1
2
R1240 0_0402_5%
HDMI_HPD
D13
FORCE_RECOVERY_R#
FORCE_RECOVERY#
RB751V-40TE17_SOD323-2
1
2
@ R1269 0_0402_5%
USB1_ID2
+3VALW
R1285
10K_0402_5%
TEMP_THERM#
JKB1 CONN@
ACES_88170-3400
B
HOT_RST#
KBC_S3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
124
2
C209
KB926QFD3_LQFP128_14X14
0.1U_0402_16V4Z
C210
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0402_25V8K
C272 1
CAPS_LED#
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
R224
300_0402_5%
FSEL#SPICS#
EC_MUTE# 17
USB_EN#
EC_REQUEST# 8
T20_WAKE# 6,9
TP_CLK
TP_DATA
100P_0402_25V8K
BATT_TEMPA
ADP_I
U19
8
@ C297
100P_0402_50V8J
1
BDID
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
SYSTEM_RESET#
2
100P_0402_50V8J100P_0402_50V8J
1
1
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
@ C296
BATT_TEMPA 23
ADP_I
EC ROM
ACOFF
2
@ C295
R212
10K_0402_5%
1
R1310
0_0603_5%
CHGVADJ
2
@ C294
Near chip
ACOFF
0_0402_5%
@ R1252
2
XCLKO_T20
FSTCHG
2
@ C293
100P_0402_50V8J
1
0.1U_0402_10V7K
97
98
99
109
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
ADP_I
2
EVENT_LED_Q
83
84
85
86
87
88
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
IREF
20
C312
C205
22P_0402_50V8J
15 XCLKO_T20
100P_0402_50V8J
1
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
OSC
EC_TX_P80_DATA
NC
EC_TX_P80_DATA
EC_TX_P80_DATA
XCLKI
X1
3
LID_SW#
SYSTEM_RESET#
XCLKI
XCLKO
C207
22P_0402_50V8J
1
2
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
INVT_PWM
INVT_PWM
77
78
79
80
1
2
R1297 0_0402_5%
@ D18 RB751V-40TE17_SOD323-2 KBC_S3
2
1GMI_AD18_D
21 LID_SW#
28 SYSTEM_RESET#
1
B
GMI_AD18
GMI_AD18
47P_0402_50V8J
2 @
C283
0.1U_0402_16V4Z
C284
0.1U_0402_16V4Z
KBC_S3
EC_SMB_CK1
EC_SMB_DA1
CAM_I2C_SCL
CAM_I2C_SDA
23 EC_SMB_CK1
23 EC_SMB_DA1
6 CAM_I2C_SCL
6 CAM_I2C_SDA
EC_SMB_DA1
63
64
65
66
75
76
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
AD Input
p:
2
21
23
26
27
PWM Output
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
tt
2.2K_0402_5%
EC_SMB_CK1
1
47K_0402_5%
R1232 2
1
R1233 2
1
47K_0402_5%
0V
Sirius
//
m
+3VALW
0V
EVENT_LED_Q
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
GND
GND
GND
GND
GND
R214
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
11
24
35
94
113
0.1U_0402_16V4Z
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
0V
EC_RESMUE
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
V AD_BID min
C206
HOT_RST#
V AD_BID max
yc
V AD_BID typ
EC_RST#
R386
@ C291
AGND
+3VALW_EC 1
47K_0402_5%
2
12
13
37
20
38
100K+/-5%
Board ID
/x
/
+3VALW
R91
10K_0201_5%
U18
1
2
3
4
5
7
8
10
R213
C199
8.2K_0402_5%
69
VCC
VCC
VCC
VCC
VCC
VCC
1
C204
68P_0402_50V8J
0_0603_5%
10P_0402_50V8J
10U_0805_6.3V6M
C202
ECAGND
C2031
R211
1
C198
1
1
2
0.1U_0402_16V4Z
+EC_AVCC
2
C201
0.1U_0402_16V4Z
ECAGND
1
2
FBM-11-160808-601-T_0603
+3VALW
4.7U_0603_6.3V6K
L15
C197
PR@
R386
0_0402_5%
om
p.
su
C196
0.1U_0402_16V4Z
BDID
R1223
Procyon
67
0_0603_5%
0_0603_5%
9
22
33
96
111
125
10U_0805_6.3V6M
+3VALW
10U_0805_6.3V6M
@ R1274
1
R386
+EC_AVCC
+3VALW_EC
R210
SI@
0_0603_5%
+3VLP
R1223
100K_0402_5%
3.3V+/-5%
+3VLP
VCC
+5VS
7
SPI_CLK_R
HOLD#
SCLK
SO
WP#
C305
0.1U_0402_16V4Z
FWR#SPI_SI
SI
GND
Security Classification
Issued Date
MX25L2005CMI-12G_SO8
2008/12/22
Deciphered Date
2009/12/22
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
ENE KB926/ROM
Size
Document Number
Rev
0.1
T20 schematic
Date:
Sheet
1
19
of
33
+2.2VS
+VDD_3V3_SBY
0_0402_5%
1
D
R222
+VDDIO_ONKEY
2
PG_VDDIO_SYS
PG_VDDIO_SYS
U21
1
3
5
VCCA
A
DIR
6
4
2
VCCB
B
GND
EN_VDD_1V8
EN_VDD_1V8 26
SN74AVC1T45DCKR_SC70-6
+TP_PWR
4.7K_0402_5% SI@
TP_CLK 1
2 R1236
TP_DATA 1
2 R1237
4.7K_0402_5% SI@
+TP_PWR
+5VS
2
EVENT_LED_Q
+VDD_3V3_SBY
EN_VDD_3V3
EN_VDD_3V3_RESET
U20B
Y*
10 SNN_NOR_10
14
GndVcc
CM1293A-02SR SOT143-4
+3VS
Q19
Q21B
2N7002DW-T/R7_SOT363-6
TP30
LED/B Connector
5Vs change to 5Valw for event LED
function can't light on S3 issue.
+5VALW
+5VS
R225
R227
U20D
LED1
2
470_0402_5%
R276
1
2
0_0402_5%
JLED1
1
2
0_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
DC_IN
PWR_LED#
BATT_FULL_LED#
BATT_LOW_LED#
WL_WW_LED
PWR_LED#
19 BATT_FULL_LED#
BATT_LOW_LED#
2
13 EN_VDD_3V3_SET#
R298
100K_0402_5%
EVENT_LED
A
2N7002DW-T/R7_SOT363-6
PR@ R226
1
2
0_0402_5%
WF_LED
Q21A
LED_DIS#
1
2
0_0402_5%
R230
PGOOD
Y*
WL_WW_LED
SI@ R228
WF_RST# 1
2
0_0402_5%
8,15 WF_RST#
14
B
GndVcc
12
11
WW_LED#
+VDD_3V3_SBY
EN_VDD_3V3
+5VALW
+3.3VS_LDO3
1
2
3
4
GND
GND
P-TWO_161011-04021
CONN@
U20C
p:
Y*
+VDD_3V3_SBY
IO2 GND
JTP1
1
TP_DATA 2
TP_CLK 3
4
5
6
TP_DATA
TP_CLK
tt
TP_DATA
EN_VDD_3V3 17,21
U20A
14
5
GndVcc
EN_VDD_1V8
Y*
+VDD_3V3_SBY
B
2
G
//
m
14
B
GndVcc
IO1
SSM3K7002FU_SC70-3
EN_VDD_3V3_RESET
ACIN
ACIN
yc
19
VIN
DC_IN
0_0402_5%
1
EN_VDD_3V3_SET#
D8
R221
2
+TP_PWR
+3VLP
TouchPAD
19 EVENT_LED_Q
EVENT_LED
16
Q30A 2N7002DW-7-F_SOT363-6
6
1
0_0603_5%
1
2
R1245
TP_CLK
SI@
om
p.
su
+3VS
0_0603_5%
+TP_PWR
PR@ R1244
1
2
/x
/
4.7K_0402_5% PR@
TP_CLK 1
2 R1241
TP_DATA 1
2 R1242
4.7K_0402_5% PR@
1
2
3
4
5
6
7
8
9
10
GND
GND
P-TWO_161021-10021
CONN@
99-116UNC/U90/TR8_WHITE
Security Classification
Issued Date
2008/12/22
2009/12/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Wednesday, July 21, 2010
Sheet
1
20
of
33
Platform reset
Power on circuit
1
+3VALW
R240
100K_0402_5%
D
D9
2
ON/OFFBTN#
ON/OFF#
51_ON#
19
51_ON#
DAN202UT106_SC70-3
+3VALW
Remove HOT_RST#
2
ON/OFFBTN#
1000P_0402_50V7K
1
om
p.
su
P-TWO_161011-04021
CONN@
1
D14 @
PSOT24C_SOT23-3
1
R244
470_0402_5%
3 2
C217
10U_0805_10V4Z
Q7B
2N7002DW-7-F_SOT363-6
5
R248
330K_0402_5%
C221
4700P_0402_25V7K
EN_+VS#
Q7A
EN_+VS#
2
2N7002DW-7-F_SOT363-6
C216
0.1U_0402_16V4Z
2
B
Q29A
2N7002DW-7-F_SOT363-6
EN_VDD_3V3
FD4
1
C226
1U_0402_6.3V6K
EN_VDD_3V3 20
D16 RB751V-40TE17_SOD323-2
@ D17 RB751V-40TE17_SOD323-2
2
1
KBC_S3
H5
H_1P0N
H9
H_2P3N
H8
H_2P9x2P3N
FD3
1
+3.3VS_RTC
@ R1306 0_0402_5%
1
2
Q8A
2N7002DW-7-F_SOT363-6
FD2
1
3VS_S3_DIS
10K_0402_5%
Q29B
2N7002DW-7-F_SOT363-6
5
1
2
R1307 0_0402_5%
FD1
1
+3VALW
H18
H_2P8N
1
3
EN_+VS#
H4
H_2P6
RTC
2
R1283
10K_0402_5%
R249
10K_0402_5%
H3
H_2P6
3VS_S3_DIS 1
+3VLP
R1282
470_0402_5%
C306
4.7U_0603_6.3V4
0.01U_0402_16V7K
R1286
47K_0402_5%
1
C300
R1284
+RTCBATT
+3VALW
D11
3 2
C299
1
2
0.1U_0402_10V6K
+3VALW
+3VS_S3
H2
H_2P6
C298
2
+3VS_S3
BAS40-04_SOT23-3
0.1U_0402_10V6K
3
+3VALW
H1
H_6P0N
Q12
AO3413_SOT23
tt
p:
10U_0805_10V4Z
1
2
EN_+VS#
@ R247
@R247
330K_0402_5%
B
@ C219
4700P_0402_25V7K
RUNON_5VS
6
R246
1
C220
47K_0402_5%
SI7326DN-T1-E3_PAK1212-8 +5VS
Q18
1
2
5
3
Q8B
2N7002DW-7-F_SOT363-6
1
yc
1
R243
470_0402_5%
3 2
//
m
RUNON_5VS
C215
10U_0805_10V4Z
+5VALW to +5VS
+5VALW
B+
C214
0.1U_0402_16V4Z
10U_0805_10V4Z
C218
SI7326DN-T1-E3_PAK1212-8 +3VS
Q17
1
2
5
3
+3VALW to +3VS
C307
680P_0402_50V7K
+3VALW
1
2
3
4
GND
GND
1
R242
10K_0402_5%
Q16
SSM3K7002FU_SC70-3
C281
0.1U_0402_16V4Z
2
G
1
2
3
4
5
6
LID_SW#
LID_SW#
/x
/
1
EC_ON
EC_ON
19
D
JPWR1
1
2
R254 0_0402_5%
PR@
C282
0.1U_0402_16V4Z
C213
Security Classification
2008/12/19
2009/12/15
Deciphered Date
Title
DC/DC interface/LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
T20 schematic
Sheet
1
21
of
33
VIN
VIN
DC_IN_S1
PL1
SMB3025500YA_2P
1
2
PQ1
PR1
68_1206_5%
PJP1
PD2
VS
1
PC5
0.22U_0603_25V7K
@ SINGA_2DW -0005-B03
PC6
0.1U_0603_25V7K
PR3
100K_0402_1%
PC4
100P_0402_50V8J
100P_0402_50V8J
N1
1
LL4148_LL34-2
1000P_0402_50V7K
PC3
1000P_0402_50V7K
PC1
PC2
-
BATT+
PR2
68_1206_5%
BSS84_SOT23-3
DC301001M80
5A_24VDC_429007.W RML
PF1
PD1
LL4148_LL34-2
2
PR4
22K_0402_1%
om
p.
su
/x
/
51_ON#
PJ1
@ JUMP_43X79
2 2
1 1
+3VALW
+1.8VSP
PJ2
@ JUMP_43X79
2 2
1 1
+1.8VS
+5VALW P
PJ3
@ JUMP_43X79
2 2
1 1
+5VALW
RTC Battery
PBJ1
PR5
560_0603_5%
1
2
PR6
560_0603_5%
1
2
+RTCBATT
@ MAXEL_ML1220T10
SP093MX0000
B
p:
//
m
+3VALW P
yc
tt
Security Classification
2005/10/17
Issued Date
Deciphered Date
2006/10/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
DCIN/DETECTOR
Size
Document Number
Rev
0.1
T20 schematic
Date:
Sheet
1
22
of
33
PD8
PJSOT24C_SOT23-3
PR7
1K_0402_1%
PR8
47K_0402_1%
PC7
1000P_0402_50V7K
EC_SMB_DA1 19
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
PH1
100K_0402_1%_NCP15W F104F03RC
PR17
19.1K_0402_1%
G718TM1U_SOT23-8
PH2
100K_0402_1%_NCP15W F104F03RC
VS_ON
//
m
2
2
2
1
VCC TMSNS1
yc
EC_SMB_CK1 19
BATT_TEMPA 19
PR15
10.2K_0402_1%
PU1
+3VALW P
PR14
6.49K_0402_1%
2
1
PR12
22K_0402_1%
PR13
33K_0402_1%
PD18
PJSOT24C_SOT23-3
PR16
1K_0402_1%
tt
p:
/x
/
1
PC9
0.1U_0603_25V7K
2
1
VL
PR11
100_0402_1%
PR10
100_0402_1%
BATT+
BATT+
ID
B/I
TS
SMD
SMC
GND
GND
PC8
0.01U_0402_25V7K
PR9
1K_0402_1%
PJP3
Pin9
Pin8
Pin7
Pin6
Pin5
Pin4
Pin3
Pin2
Pin1
BATT+
+3VALW P
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
BATT_S1
9
8
7
6
5
4
3
2
1
om
p.
su
9
8
7
6
5
4
3
2
1
GND
GND
GND
GND
PL2
SMB3025500YA_2P
1
2
@ SUYIN_200045MR009G171ZR
13
12
11
10
VMB
PF2
7A_24VDC_429007.W RML
1
2
Security Classification
2005/10/17
Issued Date
Deciphered Date
2006/10/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
BATTERY CONN.
Size
Document Number
Custom
Date:
Rev
0.1
T20 schematic
Sheet
1
23
of
33
P2
B+
P3
AON7403L_DFN8-5
PQ4
5
CSOP_17006
CSON_17006
BST
2
1
PC26
10U_1206_25V6M
2
1
1
2
1
S
PQ13
SSM3K7002FU_SC70-3
Vin Detector
ACPRN
High 18.089V
Low 17.44V
MAXIM@
PR53
16.9K_0402_1%
MAXIM@
PC59 4.7U_0805_6.3V6K
2
1
+3VALW
ICHG_SET
12
DL_CHG_17006
ISET
CSSN
PQ33 MAXIM@
DTC115EUA_SC70-3
10
MAXIM@ PR51
100K_0402_1%
11
ICHG_SET
FSTCHG
ACIN:
ACIN>2.1V => ACOK# --> Low
PR21 = 191k-ohm
PR25 = 24.9k-ohm
VIN = 18.2V
PQ34 MAXIM@
DTC115EUA_SC70-3
ACPRN
CSIN_17006
BATT+
CSIP_17006
PGND
CSSP
BATT
PC102 MAXIM@
.1U_0402_16V7K
MAXIM@ PR97
7.15K_0402_1%
IINP
DLO
CSIN
Issued Date
Security Classification
2008/12/19
2009/12/15
Deciphered Date
Title
Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
PC107
10U_1206_25V6M
2
1
1
2
PACIN
PR53 ISL@
20K_0402_1%
14
13
19
BST_CHG_17006
AGND
ACIN
PR50 ISL@
10K_0402_1%
LX
DHI
DH_CHG_17006
PR49
10K_0402_1%
1
2
2
G
PR47 MAXIM@
2.2_0603_5%
15
MAXIM@
PR76
10K_0402_1%
ISL@ PR48
100K_0402_1%
2
PC106 MAXIM@
0.68U_0603_10V6K
BST_CHGA_17006
16
17
ACIN
VCTL
DCIN
MAXIM@
PR77
10K_0402_1%
LDO_17006
ADP_I
0_0603_5%
PR109 MAXIM@
1
2 LX_CHG
LX_CHG_17006
tt
2
ICHG=(240m/50m)*(VISET/4.2)
PR39 = 137k-ohm
IREF = 3.296V => ICHG = 1.569A
IREF = 0.5223V => ICHG = 0.249A
Ki = 2.09
6251VDD
ACSETIN
MAXIM:
VIINP=Iin*Rcs_in*2.8m*PR97
Intersil:
ICM=19.9*Iin*Rcs_in
=>PR97=19.9/2.8m=7.107k-ohm
so if ADP_I=1V
=>for Intersil
Iin=1.005A
=>for MAXIM
Iin=0.999A
T%=(1.005-0.999)/1.005*100=0.6%
21
TP
1
2
MAXIM@ PC103
1U_0603_25V6K
MAXIM@
PU8
PC29
@ 680P_0603_50V8J
LDO_17006
p:
VAA_17006
DCIN
ACOK#
3.3V
1.9V
4.35V
20
4.2V
18
0V
CC
CHGVADJ
4V
19
Vcell
VAA_17006 2
1
MAXIM@ PC101
1U_0402_6.3V6K
CHGVADJ=(Vcell-4)*9.45
PC60
MAXIM@
0.01U_0402_25V7K
2
1
2
B
CC = 0.25A~1.575A
Ichg = 0.165/0.05 * Vchlim/3.3
Vchlim = IREF*100/(110+100)
IREF = 2.09*Icharge = 0.5223V~3.296
Ki = 2.09
//
m
ISL@ PR46
31.6K_0402_1%
VAA
CHGVADJ
DL_CHG_6251
ISL@ PR43
20K_0402_1%
CP mode
Vaclim=2.39*(20K//152K/(24.9K//152K+20K//152K))=1.0812V
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)=1.4524
BATT+
PQ12
AON7408L_DFN8-5
PR38
@ 4.7_1206_5%
DL_CHG_6251 1
2
0_0603_5%
PR126 ISL@
PR44 ISL@
4.7_0603_5%
PC30 ISL@
4.7U_0805_6.3V6K
6251aclim
ISL@ PR45
15.4K_0402_1%
1
2
PD7 ISL@
RB751V-40_SOD323-2
26251VDD
yc
1
PR41 ISL@
24.9K_0402_1%
6251VREF 1
2
Iada=0~1.579A(30W)
CP= 92%*Iada; CP=1.4526A
0_0603_5%
PR124 MAXIM@
DL_CHG_170061
2
PL3
10UH_FMJ-0630T-100_3A_20%
PR37 0.05_1206_1%
CHG 1
1
2
4
14
13
6251VDDP
MAXIM@
PR39
137K_0402_1%
12
PR40
ISL@ PC25
2.2_0603_5%
0.1U_0603_25V7K
BST_CHG 2
1 BST_CHGA 2
1
DH_CHG_6251
2 PACIN
G
PQ9
SSM3K7002FU_SC70-3
PQ8
AON7408L_DFN8-5
3
2
1
15
LX_CHG
1
2
0_0603_5%
PR127 ISL@
LX_CHG_6251
D
PC20
0.1U_0603_25V7K
3
2
1
2
1
UGATE
16
PR42
100K_0402_1%
/x
/
2
1
ACPRN
23
22
CSON
ACPRN
CHLIM
DH_CHG
24
DCIN
NC
27
25
28
26
VDD
ACSET
PHASE
ACLIM
VREF
DH_CHG_6251 1
2
0_0603_5%
PR123 ISL@
PR34 ISL@
2.2_0402_5%
17
NC
18
NC
ICM
PC28
0.01U_0402_25V7K
2
1
ACOFF
IREF
ACOFF
PR39 ISL@
110K_0402_1%
2
1
PQ11
DTC115EUA_SC70-3
19
1 2
ICHG_SET
VCOMP
20
2
1SS355_SOD323-2
ISL6251AHRZ-T_QFN28_5X5
0_0603_5%
PR122 MAXIM@
DH_CHG_17006 1
2
6251VREF
CSOP
om
p.
su
ADP_I
ADP_I
CSIP
11
PR35
22K_0402_1%
PACIN 1
2
CSIN
ICOMP
PQ7
DTC115EUA_SC70-3
PC23
.1U_0402_16V7K
CSIN_IN
2
1
PR32 ISL@
20_0402_5%
CSIP_IN
1
2
21
BOOT
ISL@ PC24
ISL@ PR36
.1U_0402_16V7K 47K_0402_1%
1
2
1
2
CELLS
VDDP
LGATE
PGND
PR33 6.81K_0402_1%
1
2
ISL@
SSM3K7002FU_SC70-3
GND
PQ10
ACOFF
1SS355_SOD323-2
PR27
200K_0402_1%
1
2 VIN
2
CSON
PR117 MAXIM@
0_0402_5%
CSOP_170061
2
CSOP
VADJ
EN
2
G
10
1
C
29
TP
ISL@
PU2
NC
2S: Float
3S: GND
VIN
PD6
ISL@ PR30
20_0402_5%
1
2
PC19 ISL@
0.047U_0402_16V7K
1
2
PR31 ISL@
CSOP_IN
20_0402_5%
CSON_IN
ACSETIN
PR23
10K_0402_1%
ISL@ PR29
100K_0402_1%
1
PR28
150K_0402_1%
ISL@ PC18
0.22U_0603_25V7K
2
1
DCIN
47K_0402_1%
PD5
1
ISL@ PC16
2.2U_0603_6.3V6K
2
1
FSTCHG
6251VDD
PQ6
SSM3K7002FU_SC70-3
PR119 MAXIM@
0_0402_5%
1
2CSIP_17006
PC17
1000P_0402_50V7K
PR115 MAXIM@
0_0402_5%
CSON_170061
2
2
G
ISL@ PR25
14.3K_0402_1%
PR24
10_1206_5%
DTC115EUA_SC70-3
3
PQ5
PR118 MAXIM@
1K_0402_1%
1
2 CSIN_17006
MAXIM@
PR25
24.9K_0402_1%
DL_CHG
1
2
PR22
ACSETIN
PR21
191K_0402_1%
PC27
10U_1206_25V6M
2
1
1
1
PD4
1SS355_SOD323-2
1
2
3
VIN
B+
CSIN
CSIP
PR20
200K_0402_1%
2
PR19
47K_0402_1%
PC10
5600P_0402_25V7K
1
2
PQ3
DTA144EUA_SC70-3
PC15
0.1U_0603_25V7K
@ JUMP_43X118
PJ5
2
B340A_SMA2
CHG_B+
PR18 0.05_1206_1%
4
PC14
0.1U_0402_25V6
2
1
PC13
2200P_0402_50V7K
2
1
PC12
4.7U_0805_25V6-K
2
1
PC11
4.7U_0805_25V6-K
2
1
PC56
10U_1206_25V6M
2
1
VIN
1
2
3
PC31
10U_1206_25V6M
2
1
PQ2
AON7403L_DFN8-5
PD3
Rev
0.1
T20 schematic
Sheet
1
24
of
33
PQ19
SSM3K7002FU_SC70-3
2
G
S
BOOT1
22
UGATE2
UGATE1
21
UG_5V
11
PHASE2
PHASE1
20
LX_5V
12
LGATE2
LGATE1
19
LG_5V
Ipeak = 1.19 A
Imax = 0.84 A
F = 300k Hz
Total Capacitor = 150 uF
ESR = 35m ohm
PC47
4.7U_0805_10V6K
B++
2VREF_8205
PC44
.1U_0402_16V7K
2
1
3
2
1
+
PC43
@ 680P_0603_50V8J
VL
PR66
@ 0_0402_5%
RT8205EGQW _W QFN24_4X4
PC42
150U_B2_6.3VM_R35M
+5VALWP
PR63
@ 4.7_1206_5%
PQ17
AON7702L_DFN8-5
4
NC
18
VIN
VREG5
17
GND
PL5
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
16
3
2
1
BOOT2
13
PC104
0.1U_0402_25V6
2
1
1
2
23
PC36
4.7U_0805_25V6-K
PC105
68P_0402_50V8J
2
1
/x
/
24
PC35
2200P_0402_50V7K
2
1
4.7U_0805_25V6-K
PC82
2
1
ENTRIP1
2
FB1
REF
ENTRIP2
TONSEL
ENTRIP1
VO1
PGOOD
PQ15
AON7408L_DFN8-5
PGOOD
10
yc
PR65
100K_0402_5%
PR59
75K_0402_1%
2
PC48
0.1U_0603_25V7K
tt
B++
p:
1
2
G
PR61
PC39
2.2_0603_5%
.1U_0402_16V7K
BST_5V 1
2BST5
1
2
PQ18
SSM3K7002FU_SC70-3
VREG3
EN
ENTRIP2
PC46
1U_0402_6.3V6K
1
2
3
B+
PR64
499K_0402_1%
1
2
PC45
2 @ 680P_0603_50V8J
VO2
14
15
LG_3V
P PAD
om
p.
su
LX_3V
PQ16
AON7702L_DFN8-5
ENTRIP1
PR67
100K_0402_1%
2
1
VL
1
2
3
PC38
PR60
.1U_0402_16V7K
2.2_0603_5%
1
2BST3 1
2 BST_3V
//
m
Ipeak = 2.72 A
Imax = 1.91 A
F = 375 KHz
Total Capacitor = 150 uF
ESR = 35m ohm
25
UG_3V
PR62
@ 4.7_1206_5%
PC41
150U_B2_6.3VM_R35M
1
2
PC40
@.1U_0402_16V7K
+3VALWP
PU3
PL4
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
PR58
75K_0402_1%
1
2
ENTRIP2
PQ14
AON7408L_DFN8-5
PR57
19.6K_0402_1%
1
2
PC37
4.7U_0805_10V6K
1
2
PC81
4.7U_0805_25V6-K
1
2
PC34
4.7U_0805_25V6-K
1
2
+3VLP
PC33
2200P_0402_50V7K
1
2
PC57
0.1U_0402_25V6
2
1
PC58
68P_0402_50V8J
B+
PR56
20K_0402_1%
1
2
PJ4
@ JUMP_43X79
2 2
1 1
PR55
30K_0402_1%
1
2
FB2
B++
PR54
13K_0402_1%
1
2
SKIPSEL
PC32
1U_0603_10V6K
2VREF_8205
VS_ON
PQ20
DTC115EUA_SC70-3
1
2
2
@ PC49
0.01U_0402_16V7K
PR68
100K_0402_1%
PR69
40.2K_0402_1%
VS
Security Classification
2008/12/19
Issued Date
Deciphered Date
2009/12/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
3VALW_MBP/5VALWP
Size
Document Number
Custom
Date:
Rev
0.1
T20 schematic
Sheet
1
25
of
33
EN_VDD_1V8
SY8033BDBC_DFN10_3X3
PC55
0.47U_0402_10V4Z
PC51
68P_0402_50V8J
PR72
51K_0402_1%
+1.8VSP
11
PR73
.047U_0402_16V K
PC52
680P_0603_50V8J
FB_SY8033B
1 2
FB
EN
SVIN
om
p.
su
PR70
4.7_1206_5%
NC
PR71
22K_0402_1%
LX
NC
EN_SY8033B
PVIN
EN_VDD_1V8
1
20
PC50
22U_0805_6.3VAM
TP
9
@ JUMP_43X39
ON
PC54
22U_0805_6.3VAM
LX_SY8033B
OFF
PC53
22U_0805_6.3VAM
LX
PVIN
10
+1.8VS
PL6
1UH_FMJ-0630T-1R0 HF_11A_20%
1
2
PU4
2
PG
PJ7
1
+5VALW
/x
/
VO=0.6 (1+51/24.9)=1.83V
PR74
24.9K_0402_1%
//
m
yc
tt
p:
Issued Date
Security Classification
2008/12/19
Deciphered Date
2009/12/15
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
+1.8VS
Rev
0.1
T20 schematic
Sheet
26
of
33
PU6D
LED_PWM N10
PWM
PC62
10U_0805_6.3V6M
K9
DIG_PWM N11
DIG_PWM2 F4
TPS658621AZGUR_BGA169
PC66
10U_0805_6.3V6M
PC65
10U_0805_6.3V6M
+VDD_V2V2 =2.2V
MAX current=0.025A
A1
B1
C1
C2
C3
D3
L0_1
L0_2
VIN_SM0_1
VIN_SM0_2
VIN_SM0_3
VIN_SM0_4
VIN_SM0_5
VIN_SM0_6
D1
D2
+VDD_SM0_L
SM0
C4
1
TPS658621_SM0
PR78
PGND0_1 E1
PGND0_2 E2
PGND0_3 E3
0_0402_5%
PC69
10U_0805_6.3V6M
om
p.
su
PU6F
VIN_CHG_1
VIN_CHG_2
VIN_CHG_3
K11
ISET
PC72
10U_0805_6.3V6M
H11
H12
H13
VTSBIAS M10
CHG_STAT L2
G3
H1
H2
H3
VIN_SM1_1
VIN_SM1_2
VIN_SM1_3
VIN_SM1_4
L1_1
L1_2
G1
G2
+1.0VS_SM1_L
SM1
C6
1
TPS658621_SM1
PL8
1.5UH_VLS252012T-1R5N1R4_1.5A_30%
2 +1.0VS_SM1
PR79
1
PGND1_1 F1
PGND1_2 F2
PGND1_3 F3
PU6B
J13
+VDD_SM0=1.2V
MAX current=0.6A
PC73
10U_0805_6.3V6M
PC74
10U_0805_6.3V6M
+1.0VS_SM1
0_0402_5%
+VDD_VREF1V25 =1.25V
MAX current=0.01A
+5VS_SYS
+1.2VS_SM0
PC70
10U_0805_6.3V6M
PC68
TPS658621AZGUR_BGA169
10U_0805_6.3V6M
2.2U_0402_6.3V6M
1U_0402_6.3V6K
TS
+1.2VS_SM0
PC71
+5VS_SYS
/x
/
TPS658621AZGUR_BGA169
PC67
PL7
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
1
2
PU6G
+VDD_AVDD6 =5V
MAX current=0.01A
+1.25VS_VREF
+1.25VS_VREF
1
VREF1V25 J12
+2.2VS
+2.2VS
J11
V2V2
+5VS_AVDD6
2
K13
1
2
PC64
0.47U_0603_16V7K
AVDD6
TNOPOWER
A3
+5VS_AVDD6
PU6C
1
TPS658621_TNOPOWER
TPS658621AZGUR_BGA169
BAT_1
BAT_2
BAT_3
BAT_4
RED2 K8
GREEN2 L8
BLUE2 M8
+VDD_SYS=5V
MAX current=1A
PC63
10U_0805_6.3V6M
G10
G11
G12
G13
A11
A12
A13
B11
B12
B13
C11
USB_1
USB_2
USB_3
USB_4
+5VS_SYS
1
USB1_VBUS_DETE13
F11
F12
F13
SYS_1
SYS_2
SYS_3
SYS_4
SYS_5
SYS_6
SYS_7
TP1
RED1 L9
GREEN1 M9
BLUE1 N9
+5VS_SYS
2
1
PC61
2.2U_0603_10V6K
PU6H
AC_1
AC_2
AC_3
AC_4
AC_5
C12
C13
D11
D12
D13
+5VALW
PC75
10U_0805_6.3V6M
+VDD_SM1=1V
MAX current=1.5A
TPS658621AZGUR_BGA169
SM3_SW M12
FB3
L13
L12
PGND3_2
PGND3_1
SM3IG
N12
K12
PC78
10U_0805_6.3V6M
A10
B10
C10
SM2
E12
TPS658621_SM2
PGND2_1 A8
PGND2_2 B8
PGND2_3 C8
PR80
2
PC76
10U_0805_6.3V6M
0_0402_5%
+3.7VS_SM2
1
VIN_SM2_1
VIN_SM2_2
VIN_SM2_3
PL9
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
+3.7VS_SM2
1
2
+VDD_SM2=3.7V
MAX current=0.75A
PC77
10U_0805_6.3V6M
PC79
10U_0805_6.3V6M TPS658621AZGUR_BGA169
PMU #1
tt
p:
TPS658621AZGUR_BGA169
+5VS_SYS
+3.7VS_SM2_L
BOOST Converter
A9
B9
C9
M13
N13
L2_1
L2_2
L2_3
L3_1
L3_2
SM3
L11
PU6E
PU6A
//
m
yc
TPS658621AZGUR_BGA169
Issued Date
Security Classification
2008/12/19
Deciphered Date
2009/12/15
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
PMU#1
Rev
0.1
T20 schematic
Sheet
27
of
33
PU6P
TPS658621_XTAL1
TPS658621_XTAL1
M6
XTAL1
XTAL2
TPS658621_XTAL2
TPS658621_XTAL2
N6
TPS658621AZGUR_BGA169
PU6L
ANLG1
ANLG2
ANLG3
0.01A
ADC_REF K3
AGND2
K4
+2.6VS_ADC_REF
M1
L3
M2
TPS658621AZGUR_BGA169
PC80
4.7U_0603_10V6K
PU6O
CLK_32K_IN 7
COMP
N1
PC100
@10P_0402_25V8K
+1.8VS_LDO4
C7
NORTC*
D4
T4
PR82
10K_0402_1%
TPS658621_NORTC*
NOPOWER* M11
INT*
PAD
50OHM
T1PAD
SM1PG A5
T2PAD
T6PAD
M3
N3
M4
N4
T3PAD
T7PAD
T5PAD
TPS658621AZGUR_BGA169
SYS_RESET# 7,12,17
2
PC83
0.1U_0402_25V6
OUT32K
V32K
SM0PG B4
GPIO1
GPIO2
GPIO3
GPIO4
PU6K
D7
+1.8VS_LDO4
PG_VDDIO_SYS
PG_VDDIO_SYS
LDO4PG L1
0_0402_5%
L10
PWR_INT# 7
TPS658621AZGUR_BGA169
+3.3VS_RTC
PU6N
SM1EN
9,19
SYSTEM_RESET#
HOT_RST*
TPS658621AZGUR_BGA169
PR86
@100K_0402_1%
1
PR88
4
2 0_0402_5%
1
2
1
PR87
SCLK
SDAT
TPS658621AZGUR_BGA169
M7
PSCLK J3
PSDAT J4
2 0_0402_5%
1
2
1
PR90
+2.2VS
+2.2VS
0_0402_5%
1
2
1
1
1
2
LDO9
PC87
2.2U_0402_6.3V6M
PC86
2.2U_0402_6.3V6M
PC88
2.2U_0402_6.3V6M
K1
K2
LDO8
Imax=0.15A
PC85
2.2U_0402_6.3V6M
PC92
2.2U_0402_6.3V6M
LDO7
PC91
2.2U_0402_6.3V6M
PC93
2.2U_0402_6.3V6M
3
+2.85VS_LDO6
+3.3VS_LDO7
Imax=0.1A
+1.8VS_LDO8
+2.85VS_LDO9
Imax=0.1A
Imax=0.1A
PC97
2.2U_0402_6.3V6M
Imax=0.13A
PC96
2.2U_0402_6.3V6M
PC98
2.2U_0402_6.3V6M
PC99
2.2U_0402_6.3V6M
PU6M
A4
B5
C5
AGND3_1
AGND3_2
AGND3_3
K6
DGND1
D6
DGND2DT
tt
p:
0_0402_5%
PR89
PU6I
H4
J2
//
m
+1.8VS_LDO4
7 PWR_I2C_SCL
7 PWR_I2C_SDA
G4
yc
PR85
100K_0402_1%
A2
VIN_LDO9
A7
LDO6
Imax=0.1A
TPS658621AZGUR_BGA169
PC95
2.2U_0402_6.3V6M
CPU_PWR_REQ
N8
L7
LDO5
Imax=0.01A
E11
2.2U_0402_6.3V6M
LDO4
Imax=0.01A
+3.3VS_LDO3
+1.8VS_LDO4
+2.85VS_LDO5
Imax=0.03A
SM0EN
B6
Imax=0.04A
SYNCEN
F10
B7
LDO3
B3
E10
+3.7VS_SM2
LDO2
+1.1VS_LDO1
+1.2VS_LDO2
+1.8VS_LDO4
PC94
L6
+2.2VS
1
100K_0402_1%
LDO4EN
VIN_LDO678
M5
LDO1
2
CORE_PWR_REQ
RESUME
B2
VIN_LDO4
J1
LDO0
EC_RESMUE
2.2U_0402_6.3V6M
PU6J
19
N7
+3.7VS_SM2
PC90
PR84
VIN_LDO23
om
p.
su
1
2.2U_0402_6.3V6M
A6
VIN_LDO01
N8
+3.7VS_SM2
PC89
2
2.2U_0402_6.3V6M
+3.7VS_SM2
RTCOUT H10
N5
PC84
Imax=0.01A
+3.3VS_LDO0
2
ICPIN
LAYOUT
+3.7VS_SM2
/x
/
AGND1
J10
HSK_1
HSK_2
HSK_3
HSK_4
HSK_5
HSK_6
HSK_7
HSK_8
HSK_9
HSK_10
HSK_11
HSK_12
HSK_13
HSK_14
HSK_15
HSK_16
HSK_17
HSK_18
HSK_19
HSK_20
HSK_21
HSK_22
HSK_23
HSK_24
HSK_25
HSK_26
HSK_27
HSK_28
HSK_29
HSK_30
HSK_31
HSK_32
HSK_33
HSK_34
HSK_35
HSK_36
D5
D8
D9
D10
E4
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K5
K7
K10
L4
L5
N2
TPS658621AZGUR_BGA169
PMU #2
Issued Date
Security Classification
2008/12/19
Deciphered Date
2009/12/15
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
PMU#2
Rev
0.1
T20 schematic
Sheet
28
of
33
Rev.
PG#
0.1
24
EMI request
0.1
24,25
Design change
0.1
Modify List
Phase
3/28
DVT
3/28
DVT
25
3/28
DVT
0.1
28
4/7
DVT
0.2
28
4/20
PVT
Design change
0.2
26
4/20
PVT
Design change
0.2
26
4/20
PVT
Design change
0.2
26
4/20
PVT
Design change
0.2
28
4/20
PVT
10
ME height limit
0.2
25
4/20
PVT
11
Thermal request
0.2
23
4/29
PVT
12
Thermal request
0.2
23
4/29
PVT
13
0.3
26
6/15
PreMP
/x
/
14
15
yc
16
17
//
m
18
19
20
B
Date
om
p.
su
Fixed Issue
21
p:
22
tt
23
Issued Date
Security Classification
2009/10/09
Deciphered Date
2010/10/09
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PIR-PWR
Size
C
Date:
Document Number
Rev
0.1
PAZ00
Wednesday, July 21, 2010
Sheet
1
29
of
33
Item
Fixed Issue
PAGE
Modify List
Date
Phase
recovery button
2010/03/15
01EVT
T20 GPIO
2010/03/15
01EVT
2010/03/15
01EVT
13
2010/03/15
01EVT
14,17
28
2010/03/15
01EVT
Sirius Spec.
28
2010/03/15
01EVT
EC common design
17
add KSO1/KSO2 pull high, debug TX pull down, TP CLK/DAT pull high.
2010/03/15
01EVT
17,28
add HDMI_HPD
2010/03/15
01EVT
TP new module
17,18
reserve both +5V and +3V for TP_PWR, change JTP1 from 6 pin to 4 pin.
2010/03/15
01EVT
10
14
2010/03/15
01EVT
11
16
2010/03/15
01EVT
2010/03/15
01EVT
2010/03/16
01EVT
2010/03/16
01EVT
2010/03/16
01EVT
2010/03/19
01EVT
2010/03/19
01EVT
5,6,7,11,
13,14,16,17
om
p.
su
/x
/
12
13
14
15
13
add C263~C271
16
17
add R186
17
21
add Q21,R226,R268,R298
18
Keyboard LED
19.20
add C272,R224
2010/03/19
01EVT
19
7,19,20
add TEMP_THERM#
2010/03/19
01EVT
20
all
2010/03/19
01EVT
21
2010/03/19
01EVT
22
19,22
2010/03/19
01EVT
23
16
add R197~199,R204
2010/03/19
01EVT
24
EMI request
add R206,C277,C278,R207
2010/03/19
01EVT
25
Nvidia request
16
add R299
2010/03/19
01EVT
26
2010/03/24
01EVT
27
cross talk
19,22
add C281,C282,C283,C284
2010/03/24
01EVT
28
17
2010/03/24
01EVT
add Q23
yc
16,19,20
,21
//
m
5,8,9
tt
p:
Security Classification
2009/08/28
Issued Date
2010/08/28
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
LA-5952P
Wednesday, July 21, 2010
Sheet
1
30
of
33
Item
Fixed Issue
PAGE
Modify List
Date
Phase
29
add R79,R229,C279,C280
2010/04/12
PVT
30
17
2010/04/12
PVT
31
19
2010/04/12
PVT
32
Y1 change to 9H03200413
2010/04/14
PVT
33
18
2010/04/14
PVT
34
HP issue
17
2010/04/14
PVT
35
EMI request
17
Change R187,R188,R189,R190 to L
2010/04/14
PVT
36
12
2010/04/15
PVT
37
2010/04/15
PVT
38
EMI request
2010/04/15
PVT
39
ME request
2010/04/16
PVT
40
2010/04/16
PVT
41
Q4 Update
14
2010/04/16
PVT
42
U21 Update
21
2010/04/16
PVT
43
R219 no need
19
Bypass R219
2010/04/16
PVT
44
18
2010/04/16
PVT
45
Vendor Suggest
16
2010/04/16
PVT
46
SMT Suggest
18
2010/04/16
PVT
47
SMT Suggest
2010/04/16
PVT
48
19
2010/04/16
PVT
49
15
2010/04/16
PVT
50
8 20
2010/04/16
PVT
51
19
2010/04/16
PVT
52
21
2010/04/17
PVT
53
13
2010/04/17
PVT
54
Uninstall R63 ,add R1262 and checge Voltage to +5Vs for USB leakage issue
2010/04/19
PVT
55
NVIDIA suggest
15
2010/04/19
PVT
56
19
2010/04/19
PVT
om
p.
su
//
m
yc
/x
/
tt
p:
Security Classification
2009/08/28
Issued Date
2010/08/28
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
LA-5952P
Wednesday, July 21, 2010
Sheet
1
31
of
33
Fixed Issue
PAGE
57
NVIDIA suggest
18
58
59
13
Modify List
Date
Phase
NV review result(EN_VDDIO_SD add pull down R1266, GPIO_PU3 add pull down R1265 100K ohm
2010/04/19
PVT
15
2010/04/19
PVT
D13
19
2010/04/19
PVT
60
NVIDIA suggest
14
2010/04/19
PVT
61
19
2010/04/20
PVT
62
15
2010/04/20
PVT
63
NVIDIA suggest
06
2010/04/20
PVT
64
EC PWR
19
2010/04/20
PVT
65
17
2010/04/21
PVT
66
8 17
2010/04/21
PVT
67
6 8 21
2010/04/21
PVT
68
20
2010/04/22
PVT
69
16
2010/04/26
PVT
70
NVIDIA suggest
19
Add D18
D18
18reserve R1295
R1295
1295R1296
1296R1297.
1297.
2010/04/27
PVT
71
NVIDIA suggest
14
2010/04/29
PVT
72
SD PWR change
16
2010/04/30
PVT
73
EMI suggest
14
2010/04/30
PVT
74
Thermal status on S3
2010/05/03
PVT
75
2010/05/03
PVT
76
13
2010/05/04
PVT
77
WiFi PWR.
14
p:
Item
2010/05/04
PVT
78
ME LED issue
20
2010/05/05
PVT
79
EMI issue
21
2010/05/05
PVT
80
Cost down
19
2010/05/06
PVT
81
NV suggest
09
2010/05/26
PVT
82
EVENT_LED issue
20
EVENT_LED change PWR form +5Vs to +5Valw,R276 change to 100 ohm for EVENT_LED can't light on S3 issue.
2010/05/26
PVT
83
ESD suggest
17
2010/05/26
PVT
84
22
2010/05/26
PVT
om
p.
su
//
m
yc
/x
/
tt
Security Classification
2009/08/28
Issued Date
2010/08/28
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
LA-5952P
Wednesday, July 21, 2010
Sheet
1
32
of
33
Item
Fixed Issue
PAGE
Modify List
Date
Phase
85
Cost down
2010/05/26
PVT
86
12
2010/05/27
PVT
87
12
2010/05/27
PVT
88
12
2010/05/27
PVT
89
17
2010/05/27
PVT
90
12
2010/05/27
PVT
91
Power consumption
19
2010/06/04
Pre-MP
92
Toshiba suggest
17
2010/06/04
Pre-MP
93
EMI issue
17
2010/06/04
Pre-MP
94
3G W_DISABLE# issue
15
2010/06/04
Pre-MP
95
12
Change PWR to +3VS_S3 (remove R93, install R1313 )for eMMC cold boot issue (Pre-MP 7/8)
2010/07/08
Pre-MP
96
17
2010/07/08
Pre-MP
97
ESD issue
2010/07/08
Pre-MP
98
2010/07/08
Pre-MP
99
20
2010/07/08
Pre-MP
100
19
2010/07/08
Pre-MP
101
20
2010/07/08
Pre-MP
102
RF issue
21
Change R121
R121
121R122 to SM01000
SM01000ER
01000ER00
ER00
2010/07/15
Pre-MP
103
RoHS issue
21
2010/07/15
Pre-MP
//
m
yc
om
p.
su
/x
/
tt
p:
Security Classification
2009/08/28
Issued Date
2010/08/28
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
0.1
LA-5952P
Wednesday, July 21, 2010
Sheet
1
33
of
33