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OWH000201 UMG8900 Hardware Data Configuration ISSUE2.2
OWH000201 UMG8900 Hardware Data Configuration ISSUE2.2
OWH000201 UMG8900
Hardware Data
Configuration
ISSUE 2.2
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Page 2
References
Page 3
Page 4
Start
Start
Page 5
No
Page 6
No.
Item
Description
Board No.
Cascading plan
Page 7
Page 8
Summary
Page 9
Page 10
Page 11
Page 12
Configuring Frames
Related MML Commands
Command
Function
ADD FRM
Add a frame
RMV FRM
Delete a frame
MOD FRM
Modify a frame
LST FRM
Query a frame
RST FRM
Reset a frame
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Default configuration :
> The OMU and NET in the main control frame and the MPU
and NET in other frames are configured by default. You do
not need to configure these boards and cannot delete them.
Page 17
Work modes :
> 1+1 backup :OMU, MPU, NET, CLK, TNU, TCLU, CMU,
RPU, ASU, BLU
> Load sharing :PPU, E8T, E1G, P4L, P1H, A4L, EAC, TAC,
TCU, ECU, SPF, E32, T32, FLU
> Load sharing or 1+1 backup :S2L
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Configuring Boards
Related MML Commands:
Command
Function
ADD BRD
Add a board
RMV BRD
Delete a board
MOD BRD
Modify a board
LST BRD
Query a board
RST BRD
Reset a board
Page 21
summary
Page 22
Page 23
Two-frame Cascading
MPU
MPU
Service frames
Front slot
TCLU
MNET
MNET
TCLU
Back slot
TDM
GE
TNU
MNET
MNET
TNU
CLK
CLK
OMU
OMU
FE
Back slot
Front slot
Page 24
Nine-frame Cascading
Page 25
Page 26
Cascading Configuration
Related MML Commands:
Command
Function
ADD FRMLNK
RMV FRMLNK
LST FRMLNK
Page 27
summary
Page 28
Page 29
CLOCK SYSTEM
The UMG8900 clock system provides can provide gateway exchange and
local exchange with Stratum-3 or Stratum-2 Clock
The CLK board can extract CLK Source from:
> Two-channel 8 kHz line clock
TDM interface boards, PCM
> 2.048 MHz and 2.048 Mbits/s clock
from BITS, Building Integrated Timing Supply System
> GPS/GLONASS:
Global Positioning System/Global Navigation Satellite System .
Page 30
CLOCK SYSTEM
z
Page 31
SSM
z
SSM (Synchronization Status Message) , referring the level of the reference source
For E1 signal, G.704 use Sa4Sa8 of TS0 in odd frame to transfer SSM
For T1 signal, G.704 use the fist bit of 4kbit/s data link to transfer SSM
16 Frame
Multi-frame
32 Timeslot
Odd frame
Time Slot 0
8 bits
Page 32
SSM
z
SSM code consist of 4 bit, one multi-frame consist of 8 odd frame and 8 even
frame. Each odd frame provide one bit to transfer SSM code and one multiframe can transfer 2 SSM code. In fact , the first 4 odd frame repeat the first 4
odd frame SSM code.
SSM Code
Meaning
0010
0100
1000
1011
0000
1111
Priority: PRCTNCLNCSECSTUDUS
HUAWEI TECHNOLOGIES CO., LTD.
Page 33
GPS
1.5GHz
2048kbit/s
2048kHz
1.5GHz
8kHz
C C
L L
K K
N N
E E
T T
E E
3 3
2 2
service frames
central switching frame
B B
L L
U U
N
E
T
N
E
T
E E
3 3
2 2
N N
E E
T T
Page 34
Configure reference
source?
Yes
Configure reference
source
Configure the CLK
boards
Yes
No
Page 35
Manual selection?
Yes
Yes
Yes
No
Under SSM control?
No
Without the same priority?
No
Select in the order of
GPS, LINE1, LINE2 and EXT
End
Page 36
Function
MOD CLKSRC
Page 37
Function
MOD CLK
Page 38
Command
Function
SET LINECLK
Page 39
After clock configuration, you can query clock data configuration including
phase-lock status by the command DSP CLK. The value of phase-lock
status can be:
> Free running: Indicates that the CLK board outputs free running clock
generated by its crystal.
> Fast tracking: Indicates that the CLK board is tracking reference source
clock fast and is an instantaneous status usually when the system just
connects the reference source.
> Locked: Indicates that the CLK board has locked primary reference
source and outputs clock signals aligned with reference source.
> Holdover: Indicates that the CLK board outputs clock signals based on
the locked status when reference source is missing.
Page 40
summary
Page 41
Course summary
summary
Page 42
Thank You
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