74LVC08A: 1. General Description

74LVC08A
Quad 2-input AND gate

Rev. 6 16 December 2011
Product data sheet
1. General description
The 74LVC08A provides four 2-input AND gates.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC08AD
40 C to +125 C
SO14
plastic small outline package; 14 leads;

body width 3.9 mm
SOT108-1
74LVC08ADB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads;

body width 5.3 mm
SOT337-1
74LVC08APW
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;

body width 4.4 mm
SOT402-1
74LVC08ABQ
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74LVC08A
NXP Semiconductors
4. Functional diagram
1
&
&
2
1
1A
1B
2A
2B
3A
10
3B
12
4A
13
4B
1Y
3
4
2Y
3Y
A
Y
&
10
4Y
mna221
11
12
mna222
&
11
13
mna223
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LVC08A
1A
terminal 1
index area
14 VCC
74LVC08A
14 VCC
1B
13 4B
1B
13 4B
1Y
12 4A
1Y
12 4A
2A
11 4Y
2B
2Y
1A
10 3B
2Y
3A
GND
3Y
GND(1)
10 3B
9
2B
3Y
11 4Y
GND
2A
3A
001aac946
Transparent top view
001aac945
(1) This is not a supply pin. The substrate is attached to

this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 4. Pin configuration SO14 and (T)SSOP14
74LVC08A
Product data sheet
Fig 5. Pin configuration DHVQFN14
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
2 of 15
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5.2 Pin description

Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data output
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8,11
data input
GND
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nY
[1]
H = HIGH voltage level; L = LOW voltage level; X = dont care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO > VCC or VO < 0 V
VO
output voltage
output HIGH or LOW-state
IO
output current
VO = 0 V to VCC
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
[1]
Min
Tamb = 40 C to +125 C
[2]
[3]
Max
Unit
0.5
+6.5
50
mA
0.5
+6.5
50
mA
0.5
VCC + 0.5
50
mA
100
mA
100
mA
500
mW
65
+150
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO14 packages: above 70 C derate linearly with 8 mW/K.

For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC08A
Product data sheet
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8. Recommended operating conditions

Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
1.65
3.6
1.2
5.5
VCC
40
+125
VCC = 1.65 V to 2.7 V
20
ns/V
VCC = 2.7 V to 3.6 V
10
ns/V
functional
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
output HIGH or LOW-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
VOL
II
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output
voltage
LOW-level
output
voltage
40 C to +85 C
Conditions
VCC = 1.2 V
Product data sheet
Unit
Min
Max
Min
Max
1.08
1.08
0.65 VCC
0.65 VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
VCC = 2.7 V to 3.6 V
2.0
2.0
VCC = 1.2 V
0.12
0.12
VCC = 1.65 V to 1.95 V
VCC = 1.65 V to 1.95 V
0.35 VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.35 VCC V
VCC 0.2
VCC 0.3
IO = 4 mA; VCC = 1.65 V
1.2
1.05
IO = 8 mA; VCC = 2.3 V
1.8
1.65
IO = 12 mA; VCC = 2.7 V
2.2
2.05
IO = 18 mA; VCC = 3.0 V
2.4
2.25
IO = 24 mA; VCC = 3.0 V
2.2
2.0
IO = 100 A;
VCC = 1.65 V to 3.6 V
0.2
0.3
IO = 4 mA; VCC = 1.65 V
0.45
0.65
IO = 8 mA; VCC = 2.3 V
0.6
0.8
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
IO = 12 mA; VCC = 2.7 V
0.4
0.6
IO = 24 mA; VCC = 3.0 V
0.55
0.8
0.1
20
input leakage VCC = 3.6 V; VI = 5.5 V or GND

current
74LVC08A
40 C to +125 C
Typ[1]
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Table 6.
Static characteristics continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;

IO = 0 A
0.1
10
40
ICC
additional
supply
current
per input pin;

VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
500
5000
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
4.0
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics

Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
propagation delay
tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
11.0
ns
VCC = 1.65 V to 1.95 V
0.5
4.2
9.0
0.5
10.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.5
6.9
1.0
8.0
ns
VCC = 2.7 V
1.5
2.5
4.8
1.5
5.6
ns
VCC = 3.0 V to 3.6 V
1.0
2.3
4.1
1.0
4.8
ns
1.0
1.5
ns
VCC = 1.65 V to 1.95 V
4.4
VCC = 2.3 V to 2.7 V
7.7
pF
VCC = 3.0 V to 3.6 V
10.5
pF
nA, nB to nY; see Figure 6
[2]
VCC = 1.2 V
tsk(o)
power dissipation
capacitance
CPD
[1]
output skew time
40 C to +125 C Unit
Typ[1]
VCC = 3.0 V to 3.6 V
[3]
per gate; VI = GND to VCC
[4]
pF
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LVC08A
Product data sheet
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11. AC waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
mna224
VM = 1.5 V at VCC 2.7 V

VM = 0.5 VCC at VCC < 2.7 V
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. The input nA, nB to output nY propagation delays
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
PULSE
GENERATOR
VI
VO
DUT
RT
CL
RL
001aaf615
Test data is given in Table 8. Definitions for test circuit:

RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
Fig 7.
Test circuit for measuring switching times
74LVC08A
Product data sheet
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NXP Semiconductors
Table 8.
Test data
Supply voltage
Input
Load
VI
tr, tf
CL
RL
1.2 V
VCC
2 ns
30 pF
1 k
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
2.7 V
2.7 V
2.5 ns
50 pF
500
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
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Product data sheet
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12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
1
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35

0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT108-1 (SO14)
74LVC08A
Product data sheet
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NXP Semiconductors
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
L
7
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 9. Package outline SOT337-1 (SSOP14)

74LVC08A
Product data sheet
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74LVC08A
NXP Semiconductors
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
c
y
HE
v M A
14
Q
(A 3)
A2
A1
pin 1 index
Lp
L
7
e
detail X
w M
bp
2.5
5 mm
scale
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (2)
HE
Lp
Z (1)
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 10. Package outline SOT402-1 (TSSOP14)

74LVC08A
Product data sheet
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NXP Semiconductors
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
A1
E
detail X
terminal 1
index area
terminal 1
index area
e1
e
2
y1 C
v M C A B
w M C
Eh
e
14
13
9
Dh
2.5
5 mm
scale
UNIT
mm
A(1)
max.
A1
0.05
0.00
0.30
0.18
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
y1
0.5
0.3
0.1
0.05
0.05
0.1
Note
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 11. Package outline SOT762-1 (DHVQFN14)

74LVC08A
Product data sheet
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NXP Semiconductors
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history

Table 10.
Revision history
Document ID
Release date
Data sheet status
74LVC08A v.6
20111216
Product data sheet
Modifications:
Change notice
Supersedes
74LVC08A v.5
The format of this document has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.
74LVC08A v.5
20030224
Product specification
74LVC08A v.4
74LVC08A v.4
20021030
74LVC08A v.3
74LVC08A v.3
20020308
74LVC08A v.2
74LVC08A v.2
19970630
74LVC08A v.1
74LVC08A v.1
19970630
74LVC08A
Product data sheet
12 of 15
74LVC08A
NXP Semiconductors
15. Legal information

15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term short data sheet is explained in section Definitions.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customers own risk.
Applications Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customers sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customers applications and
products planned, as well as for the planned application and use of
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customers applications or products, or the application or use by customers
third party customer(s). Customer is responsible for doing all necessary
testing for the customers applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customers third party
customer(s). NXP does not accept any liability in this respect.
Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
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applying the customers general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes NXP Semiconductors reserves the right to make

changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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construed as an offer to sell products that is open for acceptance or the grant,
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may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
74LVC08A
Product data sheet
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Non-automotive qualified products Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors specifications such use shall be solely at customers

own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors
standard warranty and NXP Semiconductors product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC08A
Product data sheet
14 of 15
74LVC08A
NXP Semiconductors
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 December 2011
Document identifier: 74LVC08A

74LVC08A: 1. General Description

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74LVC08A

Quad 2-input AND gate

Product data sheet

2. Features and benefits

5 V tolerant inputs for interfacing with 5 V logic

plastic small outline package; 14 leads;

plastic shrink small outline package; 14 leads;

plastic thin shrink small outline package; 14 leads;

DHVQFN14 plastic dual in-line compatible thermal enhanced very

Quad 2-input AND gate

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram for one gate

Transparent top view

(1) This is not a supply pin. The substrate is attached to

Fig 4. Pin configuration SO14 and (T)SSOP14

Product data sheet

Fig 5. Pin configuration DHVQFN14

All information provided in this document is subject to legal disclaimers.

Rev. 6 16 December 2011

NXP B.V. 2011. All rights reserved.

Quad 2-input AND gate

5.2 Pin description

H = HIGH voltage level; L = LOW voltage level; X = dont care

input clamping current

output clamping current

VO > VCC or VO < 0 V

output HIGH or LOW-state

total power dissipation

For SO14 packages: above 70 C derate linearly with 8 mW/K.

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 16 December 2011

NXP B.V. 2011. All rights reserved.

Quad 2-input AND gate

8. Recommended operating conditions

Recommended operating conditions

VCC = 1.65 V to 2.7 V

VCC = 2.7 V to 3.6 V

input transition rise and fall rate

output HIGH or LOW-state

Product data sheet

VCC = 2.3 V to 2.7 V

VCC = 2.7 V to 3.6 V

VCC = 1.65 V to 1.95 V

VCC = 1.65 V to 1.95 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V to 3.6 V

IO = 4 mA; VCC = 1.65 V

IO = 8 mA; VCC = 2.3 V

IO = 12 mA; VCC = 2.7 V

IO = 18 mA; VCC = 3.0 V

IO = 24 mA; VCC = 3.0 V

IO = 4 mA; VCC = 1.65 V

IO = 8 mA; VCC = 2.3 V

IO = 12 mA; VCC = 2.7 V

IO = 24 mA; VCC = 3.0 V

input leakage VCC = 3.6 V; VI = 5.5 V or GND

All information provided in this document is subject to legal disclaimers.

Rev. 6 16 December 2011

NXP B.V. 2011. All rights reserved.

Quad 2-input AND gate

VCC = 3.6 V; VI = VCC or GND;