CMOS Inverter

VDD

0
1

OFF

A=1

Y=0

ON
A

0: Introduction

GND
Slide 1

CMOS Inverter
A

VDD
ON
A=0

Y=1

OFF
A

0: Introduction

GND
Slide 2

CMOS NAND Gate

A

0: Introduction

Y
A
B

Slide 3

CMOS NAND Gate

A

0: Introduction

ON
A=0
B=0

Slide 4

ON
Y=1
OFF
OFF

CMOS NAND Gate

A

0: Introduction

OFF
A=0
B=1

Slide 5

ON
Y=1
OFF
ON

CMOS NAND Gate

A

0: Introduction

ON
A=1
B=0

Slide 6

OFF
Y=1
ON
OFF

CMOS NAND Gate

A

0: Introduction

OFF
A=1
B=1

Slide 7

OFF
Y=0
ON
ON

CMOS NOR Gate

A

0: Introduction

A
B
Y

Slide 8

3-input NAND Gate

Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

0: Introduction

Slide 9

3-input NAND Gate

Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
Y

A
B
C

0: Introduction

Slide 10

STICK DIAGRAM

Stick Diagram Colour Code

P diffusion

Yellow/Brown

N diffusion

Green

Polysilicon

Red

Contacts

Black

Metal1

Blue

Metal2

Magenta/Purple

Metal3

Cyan/L.Blue

Component

Colour

Use

metal 1
metal 2
polysilicon

Power and signal wires

n-diffusion

Signal wires,source and drain of

transistors

p-diffusion

Signal wires,source and drain of

transistors

contact
via

Signal connection

Power wires
Signal wires and transistor
gates

Connection between metals

CMOS Joining Rules

NMOS transistor

PMOS transistor

INVERTER- STICK DIAGRAM

Step 1

Two horizontal wires are used for connection with VSS and
metal2, but metal1can be use instead.

VDD. This is done in

Step 2
Two vertical wires (pdiff and ndiff) are used to represent the
n-transistor (green).

p-transistor (yellow) and

Step 3
The gates of the transistors are joined with a
polysilicon wire, and connected to the input.

Step 4
The drains of two transistor are then connected with
metal1 and joined to the output. There cannot be direct
connection from n-transistor to p-transistors.
.

Step 5
The sources of the transistors are next connected to
VSS and VDD with metal1. Notice that vias are used, not
contacts

Alternative inverter
metal1 is used instead of metal2 to connect VSS
and VDD supply

NAND Gate

NOR Gate

Stick Diagram using nMOS

2-input NOR Gate

2-input NAND Gate