`timescale 1ns/10ps

module DRAM (DataIn,DataOut,MW,AddIn,clk);

input [15:0] DataIn,AddIn;
input clk,MW;
output [15:0] DataOut;
wire [31:0] M0, M1; //dbg
reg
[31:0]m[1023:0];
assign M0 = m[0];
assign M1 = m[1];
initial m[0] = 16'h000A; //numero del que se calculara la raiz c
uadrada
always @ (posedge clk)
if (MW) m[AddIn] <= #10 DataIn;
assign #10 DataOut = m[AddIn];
endmodule