/*`include "RAM.

v"
`include "control.v"
`include "maquina_total.v"
`include "ruta_datos.v"*/
`timescale 1ns/10ps
module testbench;
reg clock;
maquina cp(clock);
initial begin
clock=1'b0;
fork
repeat(120)
begin
#35
end

clock=!clock;

join
$finish;
end
initial
begin
$dumpfile("4.vcd");
$dumpvars(0, testbench);
end
endmodule