ANNA UNIVERSITY: CHENNAI-600025

B.E DEGREE EXAMINATION, APRIL 2014

Regulations-R-2008
SIXTH SEMESTER
B.E ELECTRONICS AND COMMUNICATION ENGINEERING
EC 2357 - VLSI DESIGN LAB
Time:3 Hours

Maximum marks : 100

1) a) Design and simulate a 8-bit ripple carry adder using Verilog and verify its
functionality using a test bench.
(50)
b) Design and simulate a CMOS inverter using a layout tool and extract its
parasitics.
(50)

2) a) Design and simulate a 4-bit array multiplier using Verilog and verify its
functionality using a test bench.
b) Design and simulate a 4-bit up counter using Verilog.

(50)
(50)

3) a) Design and simulate a 3 to 8 decoder using Verilog and verify its functionality
using a test bench.
(50)
b) Design and simulate a Mod-10 up counter using Verilog.

4) a) Design and simulate a 4 to 1 multiplexer using Verilog and verify its

functionality using a test bench.

(50)

(50)

b) Design and synthesize a 4-bit adder using Verilog and show the synthesize
report for a Virtex series FPGA.
(50)

5) a) Design and simulate a 4-bit PRBS generator using Verilog.

(50)

b) Design and simulate a CMOS inverter using a layout tool and extract its
parasitics.
(50)

6) a) Design and simulate a 8-bit accumulator using Verilog.

(50)

b) Design and simulate a MOS differential amplifier using SPICE and determine
its gain.
(50)

7) a) Design and simulate a Mod-12 up counter using Verilog.

(50)

b) Design and simulate a MOS differential amplifier using SPICE and determine
its bandwidth.
(50)

8) a) Generate an automatic layout for a 10-bit number controlled oscillator using

SPICE.
(50)
b) Perform the layout extraction for the 10-bit number controlled oscillator. (50)

9) a) Design and simulate a 10-bit number controller oscillator using SPICE. (50)
b) Generate the synthesize report for 10-bit number controlled oscillator.

(50)

10) a) Design and simulate a 2 to 4 decoder using Verilog and verify its functionality
using a test bench.
(50)
b) Design and simulate a CMOS inverter from its schematic representation and
generate its layout.
(50)

11) a) Design and simulate a 3 to 8 decoder using Verilog.

b) Realize the same 3 to 8 decoder on a FPGA.

12) a) Design and simulate a 1 to 4 de-multiplexer using Verilog.

b) Realize the same 1 to 4 de-multiplexer on a FPGA.

(50)
(50)

(50)
(50)

13) a) Design and simulate of a 4-bit Johnson counter.

b) Design a CMOS inverter using SPICE and generate its netlist.

(50)
(50)

14) a) Design and simulate a MOS differential amplifier using SPICE and determine
its CMRR.
(50)
b) Design and simulate a 1 to 4 de-multiplexer using Verilog. Generate the
Synthesis report for a Virtex FPGA.
(50)
15) a) Design and simulate a 8-bit ripple carry adder using Verilog and verify its
functionality using a test bench.
(50)
b) Design a 2 to 4 decoder using Verilog and generate its synthesis report for a
Virtex FPGA.
(50)

16) a) Design and simulate a MOS differential amplifier using SPICE and determine
its gain and bandwidth.
(50)

b) Design and simulate a 4 to 1 multiplexer using Verilog.

17) a) Design and simulate a decade counter using Verilog.

(50)

(50)

b) Generate the synthesis report for the above decade counter on a Virtex FPGA.
(50)

18) a) Design and simulate a 3-bit PRBS generator using Verilog.

(50)

b) Realize the same 3-bit PRBS generator on a FPGA.

(50)

19) a) Design and simulate a CMOS inverter using SPICE.

(50)

b) Design and simulate a 4-bit ring counter using Verilog.

(50)

20) a) Design and simulate a 10-bit number controlled oscillator using standard cell
approach.
(50)
b) Design a CMOS inverter using SPICE and generate its layout.

(50)