DIGITAL INTEGRATORS SUMMARY ia project describes techniques for digital ‘nose NTs The object This Prose ece de to design digital integrators 08, t2 fnterconnect of (the Projects to solve # second-order differential equarion ve othe FiguRE EI-1 Digital integrationDIGITAL INTEGRATION ‘As show in Figure El-1, an integral /¥(e)d¢ may be approximated by a sun of rectangle areas, 1¥(¢)it. The width of each rectangle is the iteration period, St, and the height of each rectangle ie the value of YG) where’ ¢ {8 4 puleiple of 2. The Iteration period St {a the smallest quantun of time and hence ic is represented as one unit digitally. Thus the area of each rect angle is numerically equal to its height. Keeping this in mind ve can now describe « digital integracor. As shown in Figure El-2y the device has two registers Y and 1 that contain signed quantities. The Vregister holds the current value of the function Y(z), and the T register accumulates the integral. During each iteration period, two operations take place. D The ¥ register is updated to hold the new value of the funetion Y(t). 2) The new value of the ¥ register is added to the I register to form the current value of the integral. Notice that the I register has twice as many bits as the Y register. Since the integral accumulates quickly uhen Y is large, I must be large enough to prevent overflow. The wost significant n bits of I contain the usable integral with n bits of significance. Thie ie somevhat akin to the 2n-bit product of two n-bit numbers, in which the precision of the product is really only m bits, not 2n bits. The reason for choosing exactly 2n bits for I vill become apparent Later. Practical digital integrators use an incremental representation to increase speed snd simplify interconnections. Hence, instead of speci- fying a completely new value of Y in step (1) at each iteration period, only a AY increment of +1, -1, or 0 {s specified. That is, the value of Y changes by at most 1 or 1 at each mtep. The Y register can then be a counter that at each iteration period either counts up, counts down or remains the sane. n bits sh 1 REGISTER an bits FIGURE E1-2 Digital integratorY REGISTER overflow trom & 4 H REGISTER of next Integrator FIGURE 1-3. Incremental digital integrator We see that the input of 2 digital integrator is in an increnental form. For integrators to be interconnected to solve differential equations, the outputs must also have an incremental form. Consider the integrator of Figure E1-2 as re-draun in Figure £l-3. The register has n bits and the I register is divided into an "bit low order part R and an n-bit high order part H that contains the most significant bits and sign of the accumulated integral. Each tine the Y register is added to R, the high order part can change by at most. +L or -1. Hence the overflow from the R register is the incremental output of the integrator. It indicates how mich the accumulated inte~ gral changes at each step. Instead of providing an H register in each integrator, the incremental output {2 accumulated in the Y register of @ succeeding integrator when integrators are interconnected £0 solve equations. In this project you will build digital integrators that operate as described above. A single digital integrator consists of the eir- cuitry in the right half of Figure El-3 ~ an 7-bit up/doun counter, mbit adder, and n-bit register ~ plus a enall anount of combinational circuitry to generate the incremental output. The number in the Y register will be assumed to be a two's-comple- ment number. The incremental output that should be produced depends fon the sign of Y and the carry out of the "bit adder, as summarized in the following table Sign of Output carry Incremental Oueput + ° ° + 1 a - oASSIGNMENT @) ©) FIGURE EI-4 Integrator symbols. that this table describes the correct behavior should be verified by Tost sdcring the perfornance of the integrator of Figure El-2 and ex- cates the sige bit of ¥ co sake it a to's-complenent number with 2n bits, The symbol for the digital integrator is shown 4n Figure F1-4(a), where sie the time quantum, AY is the incremental Y input, 2 is wpeTacrenental output, Y 1s the accumulated input, and Yo is the cae nee yt ta possible to perform a eign tavfrston by AaieBing the + and -1 increnental signals, and Pigore El-4(b) 48 TNePEynbol for such en averting integrator. The output of an inte see amie the ineegral of ite input; equivalently, the Sapur te the derivative of the output. 1. Design and construct anB-bit integrator. Use an 8-bit up/down counter anS-bit adder, and an8-bit register as the basic components eeetTi aise need a small azount of combinational circuitry for de~ veep the Inciewentel oueput. Xf 76191n are used for the up/down ering SMtnen che format of the incremental output can be directly Sapatibie wich the 74191 count inpucs. That is, 4£ can consist of seeretgeale that mey be connected directly to the enable and up/down SMouteror the counter in che next integrator, You should provide s sre button and eight toggle svicches for initializing the Y register Push tearing the K register, an input for the At clock, and eight Taps for the counter output (x). To afd you in the rest of the pro- Jere Sake up a clock controller such as described in Project 81 or Use a pulse burst generator. a stat = we tae FIGURE E1-5 Exponential loop. FIGURE E1-6 Negative exponential loop.Using an initial condition of yy = +32, plot the output of the Integrator from ¢ = 0 to t = 345 in steps of 15. Plot the exact 1/256 values of 322/256 given tn Table E1-1 and compare. AWL. Wee an initial condition of ve verily chat yout ". dk y= 0, at shown in Figure £1-6. Use the snttéal condition ig = 127 and plo the intepeatr output for # = 0 co 6+ 245 An ater of 15. Plot the exact values of 127¢7F/256 given in Table El-1 and compare. Hook up your integrator to invert and solve the equation V. Build an integrator that replaces the adders and registers of Figure Fl-3 with a 6-bit binary rate multiplier, (Leave the existing Integrator intact.) Repeat Assignments I1 and IV with the BRA-based integrator and compare and conment on the results. VI. Suppose you had to build a 12-bit integrator. What ICs would you need for a BRM-based integrator and for a register/adder integra tor? What are the trade-offs? VIT. Dismantle the BRN-based integrator and build another register! adder integrator. Connect the two integrators in a sine-cooine loop ay to solve £4 + y = 0 ae shown in Figure E1-7. sate e ‘The first integrator has an Initial condition of 0 and the second has initial condition yoy the amplitude of the sine wave output. The accumulated integral in integrator 1 after / steps is approximately Yq #in(/256); and in integrator 2 the approximate function -co¢(/256) is accumulated. 40 FIGURE E1-7 Sine-cosine loop.TABLE El-2 Sines and Cosines ee ” ° 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720 750 780 810 ee 0. ue 23. 4 45. 55. 64. Be 80. a7. 92. 96. 98. 99. 99. 98. 95. a. 85. 19. 7. 62. 53. 43. 32. au. Es 2. 200 ein (1/256) eee ° 7 2 4 2 3 7 1 6 o 1 a 6 9 8 3 4 3 a 3 6 9 4 2 5) o 5 a 100 co9 (1/256) 100.0 99.3 97.2 93.9 89.2 83.3 16.3 68.2 59.2 49.3 38.8 27.8 16.4 47 -1.0 “18.6 30.0 40.9 31.3 61.0 69.8 “1.7 BAS 90.8 94.6 -97.8 99.6 99.9plot the accumvlated cosine integral for f= 0 te + = 810 in crepe of bo with an initial condition yp = 100. The exact values Oy Be ese taya5e) and 100 win(f/256) Care given in Table El-2- Fioe he quact value of the cosine and computes IIT. Error analysis of the sine-cosine Loop shows hat che acteb accumulated integrals in Assignment VIT have the fore 1, RY sin Na 1 = cos Wa 2 vnere k= (1+ 1/N2)4, a= tan” 1/M, and Mm 256-_ Hence The where i 7 { sheegrals’ drift from the correct integrals in pork anplic scumand phase over periods of several cycles. ane anion of the equation W/256 = 20 is ¥ = 16085, 9 that root stone are needed for 10 cycles of the sine vave: | Wet 1608S steps alehon of ig = 100, observe the drift for 10 eyetes of the sine vave by making 10685 steps. The computed value of Kt sine wave PY ce the amplitude of the eine wave after 10 cyctes sosi 1.230 an netre he phase drift, on che echer hand, £8 not observable after this Few cycles. ax, The integrator loop designed above io of the “stmultaneoss, vornniy, tecause all of the integrators change at the cane TRE, wartety: (Bin pcheme can also be used, in which one inuepeeter Comte Cemuemesel cher Hedify your sine-cosine Soop fo wake, tt sequentisl before the ag two clocks and updating one integrator vith the £0 OF erst he orher vith the second, as shown in Figure El-O; tenets chock and theegrater is updated, then the second, then the tires: 0 irae seetgele of the sequential achene indicates that ab? err aera TRtzoidol or bounded, so tat chis achene does vor Synlbit are either cifeplicude deifts of the simultaneous schee, Verify the Phase anning the new sine-cosine loop for @ ong tine, ook up an 8-bit DAC to the sine vave integral (invert, the sist Feet cera leone a tinned ton )) ofan) beer fect oar ee tay tae ie to wet © Peyagienting DAC eettting, wher Ss che enallest 1 “7 opchlLoscoPe: geen will work? What is the ceal-tine frequency of the ‘Sine wave for this 2? ia eer che Frequency of the system so that DAC settling Se Oss ¢ probion., Hook up an analog sine wave generator £0 the second scope Prapnel and compare the tuo vaveforms, al 1 we LI i FIGURE 1-8 Two-phase clockEL = DIGITAL INTEGRATORS 143 FIGURE E1-9 Danped sine-cosine loop XL, Modify your system co produce damped sine waves by solving 2 the equation £Y + 244 + y= 0, as shown schematically in Figure E1-9, det at Im Figure £1-9, integrator 3 performs multiplication by a constant. ‘The Y register of integrator 3 is initially loaded with the constant B and does not change during the integration (the AY input is not used). Whenever +1 increments are produced by integrator 1, integrator 3's ¥ register is added its R register; when -1 increments are produced, -¥ is added to R. The incremental output of integrator 3 is derived from the overflow of R in the usual manner- Implenent integrator 3 as a 4-bit integrator. Since the Y-register does not change, you may simply use 4 toggle switches or @ wired con nection to set the value of by ‘The AY inpuc of integrator 1 must respond to the outputs of both integrators 2 and 3. Therefore you will need circuitry to combine the two outputs. You may want to implement a two-phase system in which integrator 1 responds first to the output of integrator 2 and then to integrator 3. The overall systen operation may be simultaneous oF sequential, Provide sone circuitry for resetting the initial conditions auto- matically when the output amplitude becomes small, Then display the output on the oscilloscope. Observe the exponential decay and the frequency of the output for various values of b. What is the solution of the differential equation being emulated?