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Kin trc my tnh

Ni dung hc phn

Chng 6
B X L TRUNG TM

(Central Processing Unit - CPU)

Nguyn Kim Khnh

Trng i hc Bch khoa H Ni

5 September 2009

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Chng 1. Gii thiu chung

Chng 2. C bn v logic s
Chng 3. Tng quan v h thng my tnh
Chng 4. Kin trc tp lnh
Chng 5. S hc my tnh
Chng 6. B x l trung tm
Chng 7. B nh my tnh
Chng 8. H thng vo-ra
Chng 9. My tnh song song

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6.1. T chc ca CPU

Ni dung

1. Cu trc c bn ca CPU

6.1. T chc ca CPU

6.2. Thit k n v iu khin
6.3. K thut ng ng lnh
6.4. Cu trc b x l tin tin
6.5. Cc kin trc song song mc lnh
6.6. B x l a lung v a li

Nhim v ca CPU:

5 September 2009

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Nhn lnh (Fetch Instruction): CPU c lnh t b

nh.
Gii m lnh (Decode Instruction): xc nh thao tc
m lnh yu cu.
Nhn d liu (Fetch Data): nhn d liu t b nh
hoc cc cng vo-ra.
X l d liu (Process Data): thc hin php ton s
hc hay php ton logic vi cc d liu.
Ghi d liu (Write Data): ghi d liu ra b nh hay
cng vo-ra

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Bi ging Kin trc my tnh

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S cu trc c bn ca CPU

Cc thnh phn c bn ca CPU

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n v iu khin (Control Unit - CU)

n v s hc v logic (Arithmetic and
Logic Unit - ALU)
Tp thanh ghi (Register File - RF)
n v ni ghp bus (Bus Interface Unit BIU)
Bus bn trong (Internal Bus)

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2. n v s hc v logic

M hnh kt ni ALU

Chc nng: Thc hin cc php ton

s hc v php ton logic:

5 September 2009

S hc: cng, tr, nhn, chia, tng, gim,

o du
Logic: AND, OR, XOR, NOT, php dch bit.

Bi ging Kin trc My tnh

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5 September 2009

Bi ging Kin trc My tnh

Bi ging Kin trc my tnh

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3. n v iu khin

M hnh kt ni n v iu khin

Chc nng

iu khin nhn lnh t b nh a vo

thanh ghi lnh
Tng ni dung ca PC tr sang lnh k
tip
Gii m lnh c nhn xc nh thao
tc m lnh yu cu
Pht ra cc tn hiu iu khin thc hin lnh
Nhn cc tn hiu yu cu t bus h thng v
p ng vi cc yu cu .

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Cc tn hiu a n n v iu khin

Cc tn hiu pht ra t n v iu khin

Clock: tn hiu nhp t mch to dao

ng bn ngoi.
M lnh t thanh ghi lnh a n
gii m.
Cc c t thanh ghi c cho bit trng
thi ca CPU.
Cc tn hiu yu cu t bus iu khin

5 September 2009

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Nguyn Kim Khnh - HBKHN

Cc tn hiu iu khin bn trong CPU:

Cc tn hiu iu khin bn ngoi CPU:

11

iu khin cc thanh ghi

iu khin ALU

5 September 2009

iu khin b nh
iu khin cc m-un vo-ra

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Bi ging Kin trc my tnh

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2. Hot ng ca chu trnh lnh

Gin trng thi chu trnh lnh

Chu trnh lnh

Nhn lnh
Gii m lnh
Nhn ton hng
Thc hin lnh
Ct ton hng
Ngt

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Nhn lnh

5 September 2009

S m t qu trnh nhn lnh

CPU a a ch ca lnh cn nhn t b

m chng trnh PC ra bus a ch
CPU pht tn hiu iu khin c b nh
Lnh t b nh c t ln bus d liu
v c CPU copy vo thanh ghi lnh IR
CPU tng ni dung PC tr sang lnh
k tip

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5 September 2009

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Bi ging Kin trc my tnh

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Gii m lnh

Nhn d liu

Lnh t thanh ghi lnh IR c a

n n v iu khin
n v iu khin tin hnh gii m lnh
xc nh thao tc phi thc hin
Gii m lnh xy ra bn trong CPU

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CPU a a ch ca ton hng ra bus

a ch

CPU pht tn hiu iu khin c

Ton hng c c vo CPU

Tng t nh nhn lnh

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Nhn d liu gin tip

CPU a a ch ra bus a ch

CPU pht tn hiu iu khin c

S t nhn ton hng gin tip

Ni dung ngn nh c c vo CPU,

chnh l a ch ca ton hng
a ch ny c CPU pht ra bus a
ch tm ra ton hng

CPU pht tn hiu iu khin c

Ton hng c c vo CPU

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Bi ging Kin trc my tnh

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Thc hin lnh

Ghi ton hng

C nhiu dng tu thuc vo lnh

C th l:

5 September 2009

c/Ghi b nh
Vo/Ra
Chuyn gia cc thanh ghi
Thao tc s hc/logic
Chuyn iu khin (r nhnh)
...

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CPU a a ch ra bus a ch

CPU a d liu cn ghi ra bus d liu

CPU pht tn hiu iu khin ghi

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D liu trn bus d liu c copy n

v tr xc nh

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S m t qu trnh ghi ton hng

Ngt

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Ni dung ca b m chng trnh PC (a

ch tr v sau khi ngt) c a ra bus d
liu
CPU a a ch (thng c ly t con tr
ngn xp SP) ra bus a ch
CPU pht tn hiu iu khin ghi b nh
a ch tr v trn bus d liu c ghi ra v
tr xc nh ( ngn xp)
a ch lnh u tin ca chng trnh con
iu khin ngt c np vo PC

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Bi ging Kin trc my tnh

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S m t chu trnh ngt

6.2. Thit k n v iu khin

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n v iu khin vi chng trnh

(Microprogrammed Control Unit)
n v iu khin ni kt cng
(Hardwired Control Unit)

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n v iu khin vi chng trnh

n v iu khin vi chng trnh (tip)

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B nh vi chng trnh (ROM) lu tr

cc vi chng trnh (microprogram)
Mt vi chng trnh bao gm cc vi
lnh (microinstruction)
Mi vi lnh m ho cho mt vi thao tc
(microoperation)
hon thnh mt lnh cn thc hin
mt hoc mt vi vi chng trnh
Tc chm

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Bi ging Kin trc my tnh

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n v iu khin ni kt cng

n v iu khin ni kt cng (tip)

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6.3. K thut ng ng lnh (Instruction

Pipelining)

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S dng mch cng gii m v to

cc tn hiu iu khin thc hin lnh
Tc nhanh
n v iu khin phc tp

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Biu thi gian ca ng ng lnh

Chia chu trnh lnh thnh cc cng on v cho

php thc hin gi ln nhau (nh dy chuyn lp
rp)
Chng hn c 6 cng on:

Nhn lnh

(Fetch Instruction - FI)

Gii m lnh

(Decode Instruction - DI)

Tnh a ch ton hng (Calculate Operand Address-CO)

Nhn ton hng

(Fetch Operands - FO)

Thc hin lnh

(Execute Instruction - EI)

Ghi ton hng

(Write Operands - WO)

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5 September 2009

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Bi ging Kin trc my tnh

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Cc Hazard (tr ngi) ca ng ng lnh

6.4. Cu trc chung ca cc b x l tin tin

Hazard cu trc: do nhiu cng on

dng chung mt ti nguyn
Hazard d liu: lnh sau s dng d
liu kt qu ca lnh trc
Hazard iu khin: do r nhnh gy ra

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5 September 2009

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Cc n v x l d liu

Bi ging Kin trc My tnh

B nh cache

Cc n v s nguyn
Cc n v s du phy ng
Cc n v chc nng c bit

c tch hp trn chip vi x l

Bao gm hai mc cache:

n v x l d liu m thanh
n v x l d liu hnh nh
n v x l d liu vector

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Cache lnh

Cache d liu

gii quyt xung t khi nhn lnh v d liu

5 September 2009

Cache L1 gm hai phn tch ri:

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Cache L2: chung cho lnh v d liu

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Bi ging Kin trc my tnh

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n v qun l b nh

6.5. Cc kin trc song song mc lnh

Chuyn i a ch o thnh a ch vt l
Cung cp c ch phn trang/phn on
Cung cp ch bo v b nh

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Siu ng ng (Superpipeline &

Hyperpipeline)
Siu v hng (Superscalar)
VLIW (Very Long Instruction Word)

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Superpipeline

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Superscalar

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VLIW (Very Long Instruction Word)

6.6. B x l a li (multicores)

Thay i ca b
x l:

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NKK-HUT

5 September 2009

Tun t
Pipeline
Siu v hng
a lung
a li

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Cc dng t chc b x l a li

Intel - Core Duo (1)

2006
Two x86 superscalar, shared L2 cache
Dedicated L1 cache per core

Thermal control unit per core

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Manages chip heat dissipation

Maximize performance within constraints
Improved ergonomics

Advanced Programmable Interrupt Controlled

(APIC)

5 September 2009

32KB instruction and 32KB data

5 September 2009

Inter-process interrupts between cores

Routes interrupts to appropriate core
Includes timer so OS can interrupt core
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Intel - Core Duo (2)

Power Management Logic

Monitors thermal conditions and CPU activity

Adjusts voltage and power consumption
Can switch individual logic subsystems

2MB shared L2 cache

Dynamic allocation
MESI support for L1 caches
Extended to support multiple Core Duo in SMP

Intel Core Duo (3)

L2 data shared between local cores or external

Bus interface

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Intel Core i7

Intel x86 Multicore Organization - Core i7

November 2008
Four x86 SMT processors
Dedicated L2, shared L3 cache
Speculative pre-fetch for caches
On chip DDR3 memory controller

Three 8 byte channels (192 bits) giving 32GB/s

No front side bus

QuickPath Interconnection

5 September 2009

Cache coherent point-to-point link

High speed communications between processor chips
6.4G transfers per second, 16 bits per transfer
Dedicated bi-directional pairs
Total bandwidth 25.6GB/s
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ARM11
MPCore
Block
Diagram

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Ht chng 6

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13