Real Time Embedded Systems

EE Department

COMSATS Institute of Information

Technology, Lahore.

Real Time Embedded Systems

(Lab 6)
Develop an application to use I/O ports in a
Nios II based embedded system
Name ___________________________

Regd. Number_____________________

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Develop an application to use I/O ports in a Nios II based embedded system

Objectives:

In this Lab you will be able to learn:

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How I/O ports are implemented in a Nios II System

How application is developed to use I/O ports

The complete implementation of the embedded system design that

based on the Nios II processor

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Real Time Embedded Systems

Introduction
This lab introduces you to the complete embedded system development flow for the Nios II
processor. Using the Quartus II software and the Nios II Embedded Design Suite (EDS), you
build a Nios II hardware system design and create a software program that runs on the Nios II
system and interfaces with components on Altera development board.
The design task you build in this lab demonstrates a small Nios II system for control
applications, that displays character I/O output and blinks LEDs in a binary counting pattern.
This Nios II system can also communicate with a host computer, allowing the host computer to
control logic inside the FPGA.
The Nios II system design contains the following components:

Nios II/s processor core

On-chip memory

Timer

JTAG UART

8-bit parallel I/O (PIO) pins to control the LEDs

System identification component

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Real Time Embedded Systems

Figure 1is a block diagram showing the relationship among the host computer, the target board,
the FPGA, and the Nios II system.

Figure 1: Relationship among the different sections

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Real Time Embedded Systems

The following steps are involved to the complete development of embedded system design that
based on the Nios II system.

1. Defining and Generating the System in Qsys

You use Qsys to specify the Nios II processor core(s), memory, and other components
your system requires. Qsys automatically generates the interconnect logic to integrate the
components in the hardware system.
You will use the embedded design suit to build a hardware system that contains the
following components.
o Nios II/s processor core
o On-chip memory
o Timer
o JTAG UART
o 8-bit parallel I/O (PIO) pins to control the LEDs
o System identification component

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EE Department

2. Integrating the Qsys System into the Quartus II Project

After generating the Nios II system using Qsys, you integrate it into the Quartus II
project. Using the Quartus II software, you perform all tasks required to create the final
FPGA hardware design.
In this section you perform the following steps to complete the hardware design:

Instantiate the Qsys system module in the Quartus II project.

Import the input/output ports and connect them to the system

Add IP verification file

Assign pin locations.

Compile the Quartus II project.

Verify timing

3. Download the Hardware Design to the Target FPGA

In this section you download the .sof to the target board.

4. Develop an application using the Nios II SBT for Eclipse

In this section, you start the Nios II SBT for Eclipse and compile a simple C language
program. This section presents only the most basic software development steps to
demonstrate software running on the hardware system you created in previous sections.
In this section, you perform the following actions:

Create a new Nios II application and BSP from template

o Select an application Count Binary from template

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project settings to minimize the memory footprint of the software

Build the project

Run the program on target hardware

Now at this point you have completed building a Nios II hardware system and running software
on it. Through this lab design task, you have familiarized yourself with the steps for developing a
Nios II system:

Defining and generating Nios II system hardware in Qsys

Integrating the Qsys system into a Quartus II project

Compiling the Quartus II project and verifying timing

Creating a new project in the Nios II SBT for Eclipse

Compiling the project

Running the software on target hardware

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Grading Lab 6
Total Marks
Lab performance

Lab participation

Behavior in the Lab

Viva

Total

10

Date

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Obtained Marks

Instructor Signature