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GDM12864HLCM: User's Guide
GDM12864HLCM: User's Guide
GDM12864HLCM
(Liquid Crystal Display Module)
CONTENTS
Mechanical diagram
Absolute maximum ratings
Interface pin connections
Optical characteristics
Electrical characteristics
KS0107B
KS0108B
Write or read cycle
Timing characteristics
Block diagram
Display commands
Reliability and lift time
Operating Principles & Methods
Mechanical diagram
Symbol
Vdd - Vss
Vin
T0p
Tst
Min.
0
0
-20
-25
Max.
6.5
Vdd
70
75
Unit
V
Pin No.
1
2
3
4~11
12
13
14
15
16
17
18
19
20
Symbol
Vdd
Vss
V0
DB0~DB7
CS2
CS1
/RES
R/W
D/I
E
VEE
A
K
Level
5.0V
0V
H/L
L
L
L
H/L
H/L
H, H L
4.2V
0V
Description
Supply voltage for logic and LCD (+)
Ground
Operating voltage for LCD (variable)
Data bit 0~7
Chip select signal for IC2
Chip select signal for IC1
Reset signal
H: read (MUP< module),L: write (MPU >module)
H: data, L: instruction code
Chip enable signal
Operating voltage for LCD (variable)
Backlight power supply
Backlight power supply
Optical characteristics
STN Type display module (Ta=25 , Vdd=5.0V)
Item
Symbol
Condition
Viewing angle
Cr
Tr
Tr
Cr 2
-
Min.
-60
-40
-
Typ.
6
150
150
Max.
35
40
250
250
Unit
deg
ms
ms
Electrical characteristics
Item
Logic
LCD
Logic
LCD
H: level
L: Level
Symbol
Condition
Vdd - Vss
Vdd-V0
Idd
Iee
25
High level
Low level
Vdd-v0
Vih
Vil
Standard value
Min.
Typ.
Max.
4.75
5.0
5.25
9.5
2.5
1.0
9.5
0.7Vdd
Vdd
0
0.3Vdd
Unit
V
mA
Symbol
VDD
VEE
VB
VLCD
Rating
-0.3 ~ +7.0
VDD -19.0 ~ VDD +0.3
-0.3 ~ VDD +0.3
VEE -0.3 ~ VDD +0.3
Unit
V
V
V
V
Note
*1
*4
*1,2
*3,4
*Notes:
*1. Based on VSS = 0V
*2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and V5L)
*3. Applies to V0L, V1L, V4L, and V5L.
*4. Voltage level: VDD V0 V1 V2 V3 V4 V5 VEE
Typ.
450
Max.
5.5
VDD
0.3VDD
0.4
+1.0
585
1.5
1.0
0.2
0.1
600
1500
Unit
Note
*1
*2
A
*1
kHz
k
*3
mA
*4
*5
kHz
Notes
*1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2,
M, and CL2 in the input state.
*2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M, and CL2 in the
output state.
*3. This value is specified about current flowing through VSS.
Internal oscillation circuit: Rf=47k , cf=20pF
Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load.
*4. This value is specified about current flowing through VSS.
Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS
and CL2, M, DIO1 is external clock.
*5. This value is specified about current flowing through VEE, Dont connect to VLCD (V1~V5).
Symbol
VDD
VEE
VB
VLCD
Rating
-0.3 ~ +7.0
VDD -19.0 ~ VDD +0.3
-0.3 ~ VDD +0.3
VEE -0.3 ~ VDD +0.3
Unit
V
V
V
V
Note
*1
*4
*1,3
*2
*Notes:
*1. Based on VSS = 0V
*2. Applies the same supply voltage to VEE. VLCD=VDD-VEE.
*3. Applies to M, FRM, CLK1, CLK2, CL, RESETB, ADC, CS1B, CS2B, CS3, E, R/W, RS and
DB0~DB7.
*4. Applies V0L, V2L, V3L and V5L.
Voltage level: VDD
V0 V1 V2 V3 V4 V5 VEE
Typ.
-
Max.
5.5
VDD
VDD
0.3VDD
0.8
0.4
+1.0
5.0
Unit
7.5
0.1
0.5
*1
*2
*1
*2
*3
*3
*4
*5
2.0
-
Note
*6
k
*8
*7
mA
Notes
*1. CL, FRM, M, RSTB, CLK1, CLK2
*2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7
*3. DB0~DB7
*4. Except DB0~DB7
*5. DB0~DB7 at high impedance
*6. V0, V1, V3, V3, V4, V5
*7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load
*8. VDD-VEE=15.5V
V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L
*7
Symbol
Tc
Twh
Twl
Tr
Tf
Tasu
Tah
Tdsu
Td
Tdhw
Tdhr
Min.
1000
450
450
140
10
200
10
20
Typ.
-
Max.
25
25
320
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write timing
tC
E
tW L
tW H
tR
R/W
tF
t AH
tA S U
t ASU
t AH
CS1,CS2
CS,RS
t DSU
tDHW
DB0~DB7
Read timing
tC
E
tWL
tWH
tR
R/W
tF
tASU
tAH
tASU
tAH
CS1,CS2
CS,RS
tD
tWH
DB0~DB7
MPU Read timing
Block diagram
IC3
COM 1~64
LCD PANEL
SEG1~64
SEG65~128
IC1
IC2
V0
VDD
VSS
IC4
VEE
5 8
DB0~DB7
/RET
CS
R/W E RS
5 8
A
K
+5V
VDD
LCM
Vo
VR
VEE
VSS
GND
*Note
1/64 duty, 1/9 bias
VDD >V1>V2>V3>V4>V5>VEE
Instruction
RS
RW
Read Display
Data
Read data
Write Display
Data
Write data
Status Read
Busy
Set Address
(Y address)
Y address (0~63)
Set Display
Start Line
Set Address
(X address)
Display On/off
1.
DB7
DB6
DB5
ON/
OFF
DB4
Reset
DB3
DB2
DB1
DB0
Page (0~7)
0/1
Function
Reads data (DB[7:0])from
display data RAM to the
data bus.
Writes data (DB[7:0]) into
display data RAM. After
writing instruction, Y
address is incriminated by
1 automatically
Reads the internal status
BUSY
0: Ready
1: In operation
ON/OFF
0: Display ON
1: Display OFF
RESET
0: Normal
1: Reset
Sets the Y address in the Y
address counter
Indicates the display data
RAM displayed at the top
of the screen.
Sets the X address at the X
address register.
Controls the display ON or
OFF. The internal status
and the DDRAM data is
not affected.
0: OFF, 1: ON
Display On/Off
The display data appears when D is 1 and disappears when D is 0.
Though the data is not on the screen with D=0, it remains in the display data RAM.
Therefore, you can make it appear by changing D=0 into D=1.
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
1
1
D
2.
R/W
0
DB7
0
DB6
1
DB5
AC5
DB4
AC4
DB3
AC3
DB2
AC2
DB1
AC1
DB0
AC0
10
3.
4.
R/W
0
DB7
1
DB6
0
DB5
1
DB4
1
DB3
1
DB2
AC2
DB1
AC1
DB0
AC0
5.
DB7
1
DB6
1
DB5
AC5
DB4
AC4
DB7
BUSY
DB6
0
DB5
ON/OFF
DB3
AC3
DB2
AC2
R/W
0
DB4
RESET
DB3
0
DB0
AC0
DB2
0
DB1
0
DB0
0
BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
ON/OFF
When ON/OFF is 1, the display is on.
When ON/OFF is 0, the display is off.
RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
7.
DB1
AC1
Status Read
RS
1
6.
R/W
0
DB1
D1
DB0
D0
DB1
D1
DB0
D0
11
1.
I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active
mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But
RSTB and ADC can operate regardless CS!B-CS3.
2.
Input register
Input register is provided to interface with MPU which is different operating frequency. Input register stores
the data temporarily before writing it into display RAM.
When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is
written into input register. Then writing it into display RAM. Data latched for falling of the E signal and
write automatically into the display data RAM by internal operation.
3.
Output register
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active
mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3
is in active mode and R/W=H , RS=L, status data (busy check) can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in
display data RAM is latched into output register. In second access, MPU can read data which is latched. That
is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read.
RS
R/W
L
H
L
H
4.
Function
Instruction
Status read (busy check)
Data write (from input register to display data RAM )
Data read (from display data RAM to output register)
Reset
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving
instruction from MPU. When RSTB becomes low, following procedure is occurred.
1. Display off
2. Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions
after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction.
The conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item
Reset Time
Rise Time
VDD
Symbol
tRS
tR
Min
1.0
-
Typ
-
Max
200
Unit
us
ns
4.5[V]
t RS
RSTB
tR
0.7VDD
0.3VDD
12
5.
Busy flag
Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in
internal operating .
When busy flag is low, KS0108B can accept the data or instruction.
DB7indicates busy flag of the KS0108B.
Busy Flag
T Busy
1/fCLK<T Busy<3/fCLK
6.
7.
X Page Register
X page register designates pages of the internal display data RAM.
Count function is not available. An address is set by instruction.
8.
Y address counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and
is increased by 1 automatically by read or writes operations of display data.
9.
13