Scribd Logo
Upload

Welcome to Scribd!

  • Iscas 89 Info

    Uploaded by

    gokulchandru
    8 views6 pages
    f

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    f

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    8 views6 pages

    Iscas 89 Info

    Uploaded by

    gokulchandru
    f

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 6
    Combinational Profiles of Sequential Benchmark Circuits Franc Brglez*, David Bryan, Krzysztof Koémiriski Microelectronics Center of North Carolina P.O.Box 12889, 3021 Comuallis Rd, Research Triangle Park, NC 27709 Abstract ‘This paper presents a set of 31 digital sequential circuits deseribed at the gate level. These circuits extend the size and complexity ofthe ISCAS'8S set of Combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed SequentalScan-based test generation vis partial sean techniques. Although all the benchmark circuits are Sequential, synchronous, and use only D-type Nip flops, additional interior faults and asynchronous behavior can be introduced by substiuting some oF all of the flip-flops with their appropriate functional ‘models. The standard functional model of a D flip= flop provides a reference point independent of the faults particular to the flip-flop implementation. In this paper, a testability profile of the benchmarks in the fulrscan mode configuration is discussed. Introduction ‘The advances in automatic test pattem genera- tion (ATPG) algorithms for scan-based systems [1,2] prompted an exchange of benchmark circuits (3) that ‘were distributed to special session participants during ISCAS (4). These benchmarks are characterized in more detail in (5.6). Since their introduction, the benchmarks have been widely distributed and have been used not only forthe purpose of evaluating the performance of ATPG algorithms but also in the areas of simulation, fault simulation, testability alysis, Tormal. verification, logic. synthesis, technology mapping and layout synthesis. The ISCAS'SS benchmarks contain faults for which no tests can be found and proving them redundant with reasonable computational effor remains a challenge feven today, The task of proving all untestable faults in these benchmarks to be redundant has been accomplished forthe frst time only recently (7) For ISCAS'89, we have prepared a new set of benchmarks that can be used for evaluating not only ‘Algo wah Bel Norther Research, Reseach Triangle Path, Seaton ISCAS “89 27) 835.4080 full scan-based algorithms for test pattem genera tion, but also to identify opportunities and limitations for sequential test pattern generation algorithms, with of without the assistance of partial scan. Most Significantly, dhese benchmarks extend the range of current ISCAS'85 benchmarks both in their size as Wwell as complexity. While all benchmark nelists are by defaule’ expanded for synchronous. circuit behavior, asynchronous behavior and additional faults can be introduced by appropriate modeling of D flip-flop primitives as discussed later in the paper. Following our cal for contributions in Septem: ber 1988, the benchmarks were assembled from Various nedist formats received from industrial and university sources from the USA and abroad. We also synthesized several ofthe benchmarks automati cally, 35 apart ofthe on-going research at MCNC, ‘The first part of the paper presents the benchmarks, their essential circuit parameters, and any structural characteristics that were passed On 10 us. A testability profile is determined forthe full sean mode configurations ofall circuits in order 19 establish the basis for comparisons of scan-, partial Scan, and sequential-based methods in terms of fault ‘overage and test patem generation cost. The second part of the paper discusses the netlist details, the urrent distribution format, and deseribes the method sed at MCNC to produce several different levels of IC representations, including the ones distributed ‘with the rest of the benchmark set, from a single high-level description, Our target forthe future is 10 have a consistent set of different-level representations of identical circuits that will help to coordinate the test pattem generation efforts on the Switch-level, gate-level, and higher levels of abstraction, and to make possible fair comparisons between test patem generation algorithms operating on different levels Benchmark characteristics and profiles We present a total of 31 cireuit benchmarks; their essential statistics are shown in Table 1. We adopt the naming convention similar to the ISCAS 1929 (c#2692-2/89/0000-1929 $1.00 © 1989 IEEE. ‘ruruwer imormanon van oe oowined trom we, ¥¥. ReNnetN JENKINS, set: s#. The letter 5 signifies that the circuit is synchronous sequential, the number that follows represents the number of interconnect lines among the cireuit primitives. Note that the double of this ‘number also represents the upper bound on the size fof the single stick-at fault ist The actual size ofthe fault list reported in Table | has been obtained by a simple fauit collapsing method outlined in the next + $386, $510, 5983, and 51498 are controllers Synthesized rom ahigh level desenption, $1238 isa combinational circuit with randomly ineertd flip-flops, £208, 2420, and” s838 are digital fractional ‘multipliers (8), synthesized hierarchically from 2 igh level description, 4258, 5208, 3713, 864, and s832 are based on PLD devices, + $346, 4382, s526n, 9641, 3820, 51196, s1488 iat at Rat ek re = have been re-synthesized from $348, 400, $526. acuity [Primary] D-tpe J ANDIOR | Cotapre ST13, $832, 61238, $1494, ater removing ali Nave_|ingus” |Ovpus | figtops| NOT Gud Fala 3 fe a suse [tans [Ouse NOT Cred fa redundancies in Flls Fa a CT AA full-sean mode testability profile of these 296 [3 —— Jefe fro — a benchmarks is given in Tables 2,3, and 4. a axon | —owatien | PU vine [Uawnot 336 [ef fis fies 0 cut |rmem' |e [Pea | ne] owe [oe 3823 Je Jar hiss foo Nave [Pout | nem Coveney 5867 [7 —s Tiss Tt ee 300—[3 Js Ties Toe aro hoofs ar e001) [fis fos fos 208 iowa — [7 — foo fn ss_[3 Jo at fist fora 298 fioo [56 p00 se FC soo —[2s—T100—fo-s ris 260 [3 fear five —f553 39 oops oo. 3 Jor fais 2526 [3 [6 Jar fos —Ts5 S32 f106 —[36— [100 Joe fn seat [95 fae fis 9 Tar 386100 —]7s [1001-4 ist aris isos [sa 300 oa — [on se [1s Sor smo —fie fo —]5- en Tas seat foro} — foo [19 ffs 832s fis [fer for ses_[oras [or — [ors [as — [33s es [2 [roo Tas ssi0_ [100 for fio [1 ea 9531s [25a [398 f95 8260 foo [70100 — [6 i561 ugg fie fie fae fs29 fae FS EO sia fig fie fie [sos [ss sos poo [s9— fo Pos — fs sigs fi7 [soe Yost ss ison | [oe [ss [ti ine siaae_ fe [19 Jo fossa 82000 asf 00 Toe a steoe [a [191s Joar_—f06 5630p. fos. 3 afr FS ES CE Sta fanss- [e100 fae aoa 234 [i> [aoa —|s597 nor Sse fs So sisaar st fiat [oso —r951 [on 1196 [99.82 [vee Too — [7 [23a sisssof ue fer [97 Jarra 737 sine [oa 7s fis) [oa 99 feof — [son 233932] 35 [20 roa frees — stad aos [78 —[op.08 [str [5059 38817 [25 [1066369 — [ra Si [roo [te [00 fs ls sake [2 [2a [as ions [0 sass sa [sT [oso [ss es Table |. Benchmark ciruit characterises ss ofan fos fos a si |woas_fars [93.47 [oe No schematic diagrams re provided for hese [Sons tant— [anaes benchmark seus. Also, the funcional dessipuons Tiaras [oer [as [oer are not available for most of the circuits The Fsesaeebe fSiTFhases fons free Hovres following is a summary of what we presently know FSS22{B8L_ ts —[ep.st_ fase ooish asso aboot the circuits: ssnstals.65— [963 —osas [e070 on 5349 is a 4-bit mulkiplien, 5298, 400, s444, and s526 are traffic light controllers, 59234, 513207, 15850, 538417, s38584 are real-chip based and rely on paral sean, 1930 Table 2. Testability profile in fll scan mode Our test generation system is based on the components described in [10.11,12] and runs on a VAX-8650. The wo main points highlighted in ‘Tables 2, 3, and 4 are: random pattem testability of the circuits, and the length of test sequences required to tes for the shown fault coverage in the full scan ‘mode. This length is a function of the number of Useful test pattems, n, and number of Mip-flops in the scan chain, d: n(d#1)+d. The random pattern ‘grading algoridum was run for 100,000 teal paterss, Unless 2 100% faule coverage was attained earlier, this occurred for citcuits listed in Table 3, For some circuits we could prove redundaney of all faulis aborted with 50 backiracks by extending the backtrack limit in our DTPG: these circuits are marked in table 4 with °*', The total additional ‘computation eos fr these circuits was 90 seconds of CPU time, We also reduced the number of aborted faults in $1423 10 5, and in s$378 to I; these circuits are marked with “T". The CPU time used for these ‘ireaits was 644 seconds Tee Sara et "We made no ate 9 optimize th ove sos = oe ofthe tet pate genera proces: he Cot could ko Be Sanebyelued on Soe ran parm ae Tsistntchecis if we che vo engage ie Sn 0 ‘Ereminisi et pate genes ear Ste Sua Levels of Benchmark Representation Sat — pan Sem In thi section we describe the curren Spe sistouson format and Masta our approach fo fra_[ate erating different levels of Cenchmark or Gresenatn fom tingle high-level description, ar ‘Weave use te spproach or mi 0 develop some Taz ea Df te tabiytencnars but soo conrbute Tle 31 Creuse 10% random emai, wef pout Benchmarks oe freoming fay Rant al ‘The benchmark circuits distributed to ISCAS'89 ae ses ca Ser as ee sep x icet Ane example of cet 327s oo [she benchma shown in Fg 1 Esp SORE 77 apate Sot fir Ti eRate fe £3°S°Bpe nip tops te 12 iach sia fe = 13 tel Aos +1 nans «2 ons +4 NOR) rae fi NONE pute! B z runs} af iNrurie} Sepa Nrurtes) Sartor — oureente:7) 315850 [308 st G5 = DFFIGIO, Sas —[ 82 Briel} Seas —tie Sr Bereta Seehes —tt Gis » sonco S17 2 Nonety Table 4, Cire with edundant andor aborted faults (Gee text forthe meaning of * and *). G8 © ANDIGI4.06) Gis ontciz.cs) For random pater resistant fats, our | S48 2 GIES deerme pte ener OTE) siwat | ae nyo ran wha bocktack init of 30. The fal fut | Sage mynareer Coverage given n Table 2 not aivays HOR ine | GLP > ROMELEG) Sota aut fous for vbich DIVG found no ess are | GL2 = NONGLCT hen Table «Even wih the baokrack hmieot [G19 = NONEZEI2 50, we found that most of the faults not covered in random pattern grading were redundant. However, all of the synthesized andjor re-synthesized circuits ‘were 100% testable inthe full sean mode 27) 835.4080 Fig. 1, Netlist of the 527 benchmark circuit We chose a netlist format that is concise, self documenting and easy to parse. The only sequential 193 ‘ruruwer imormanon van oe oowined trom we, ¥¥. ReNnetN JENKINS,

    You might also like