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AVRinstruction Set
AVRinstruction Set
Status Register
C:
Carry Flag
Z:
Zero Flag
N:
Negative Flag
V:
S:
H:
T:
I:
8-bit
Instruction Set
Rr:
R:
K:
Constant data
k:
Constant address
b:
s:
X,Y,Z:
A:
q:
Rev. 0856EAVR11/05
I/O Registers
RAMPX, RAMPY, RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with
more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.
RAMPD
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K
bytes data space.
EIND
Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more
than 64K words (128K bytes) program space.
Stack
STACK: Stack for return address and pushed registers
SP:
Flags
:
0:
1:
-:
Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
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0856EAVR11/05
I/O Direct
Figure 3. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Note:
Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the
opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing,
not I/O addressing.
Data Direct
Figure 4. Direct Data Addressing
Data Space
20 19
31
OP
16
0x0000
Rr/Rd
Data Address
15
RAMEND
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.
0
Y OR Z - REGISTER
15
10
OP
6 5
Rr/Rd
0
q
RAMEND
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction
word. Rd/Rr specify the destination or source register.
Data Indirect
Figure 6. Data Indirect Addressing
Data Space
0x0000
15
0
X, Y OR Z - REGISTER
RAMEND
Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing is
called Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the data
space form 0 to 31 is the Register File.
5
0856EAVR11/05
0
X, Y OR Z - REGISTER
-1
RAMEND
The X,- Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-,
Y-, or the Z-register.
Data Indirect with Post-increment
Figure 8. Data Indirect Addressing with Post-increment
Data Space
0x0000
15
0
X, Y OR Z - REGISTER
RAMEND
The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing.
LSB
FLASHEND
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. For LPM, the LSB selects
low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. If ELPM is used, the
RAMPZ Register is used to extend the Z-register.
Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction
Figure 10. Program Memory Addressing with Post-increment
0x0000
LSB
1
FLASHEND
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSB selects low byte
if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.
7
0856EAVR11/05
16
OP
0x0000
6 MSB
16 LSB
15
21
0
PC
FLASHEND
15
0
PC
FLASHEND
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Zregister).
FLASHEND
Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.
9
0856EAVR11/05
Boolean
Rd > Rr
Z(N V) = 0
Rd Rr
Complementary
Boolean
BRLT(1)
Rd Rr
Z+(N V) = 1
(N V) = 0
BRGE
Rd < Rr
Rd = Rr
Z=1
BREQ
Rd Rr
Rd Rr
Z+(N V) = 1
Rd < Rr
(N V) = 1
Rd > Rr
C+Z=0
Mnemonic
Mnemonic
Comment
BRGE*
Signed
(N V) = 1
BRLT
Signed
Z=0
BRNE
Signed
Rd > Rr
Z(N V) = 0
BRLT*
Signed
BRLT
Rd Rr
(N V) = 0
BRGE
Signed
BRLO(1)
Rd Rr
C+Z=1
BRSH*
Unsigned
BRGE
(1)
Rd Rr
C=0
BRSH/BRCC
Rd < Rr
C=1
BRLO/BRCS
Unsigned
Rd = Rr
Z=1
BREQ
Rd Rr
Z=0
BRNE
Unsigned
Rd Rr
C+Z=1
BRSH(1)
Rd > Rr
C+Z=0
BRLO*
Unsigned
Rd < Rr
C=1
BRLO/BRCS
Rd Rr
C=0
BRSH/BRCC
Unsigned
Carry
C=1
BRCS
No carry
C=0
BRCC
Simple
Negative
N=1
BRMI
Positive
N=0
BRPL
Simple
Overflow
V=1
BRVS
No overflow
V=0
BRVC
Simple
Zero
Z=1
BREQ
Not zero
Z=0
BRNE
Simple
Note:
10
1. Interchange Rd and Rr in the operation before the test, i.e., CP Rd,Rr CP Rr,Rd
Operands
Description
Operation
Flags
#Clock
Note
Rd, Rr
Rd Rd + Rr
Z,C,N,V,S,H
ADC
Rd, Rr
Rd Rd + Rr + C
Z,C,N,V,S,H
ADIW
Rd, K
Rd+1:Rd Rd+1:Rd + K
Z,C,N,V,S
2 (1)
SUB
Rd, Rr
Rd Rd - Rr
Z,C,N,V,S,H
SUBI
Rd, K
Subtract Immediate
Rd Rd - K
Z,C,N,V,S,H
SBC
Rd, Rr
Rd Rd - Rr - C
Z,C,N,V,S,H
SBCI
Rd, K
Rd Rd - K - C
Z,C,N,V,S,H
SBIW
Rd, K
Rd+1:Rd Rd+1:Rd - K
Z,C,N,V,S
2 (1)
AND
Rd, Rr
Logical AND
Rd Rd Rr
Z,N,V,S
ANDI
Rd, K
Rd Rd K
Z,N,V,S
OR
Rd, Rr
Logical OR
Rd Rd v Rr
Z,N,V,S
ORI
Rd, K
Rd Rd v K
Z,N,V,S
EOR
Rd, Rr
Exclusive OR
Rd Rd Rr
Z,N,V,S
COM
Rd
Ones Complement
Rd $FF - Rd
Z,C,N,V,S
NEG
Rd
Twos Complement
Rd $00 - Rd
Z,C,N,V,S,H
SBR
Rd,K
Rd Rd v K
Z,N,V,S
CBR
Rd,K
Rd Rd ($FFh - K)
Z,N,V,S
INC
Rd
Increment
Rd Rd + 1
Z,N,V,S
DEC
Rd
Decrement
Rd Rd - 1
Z,N,V,S
TST
Rd
Rd Rd Rd
Z,N,V,S
CLR
Rd
Clear Register
Rd Rd Rd
Z,N,V,S
SER
Rd
Set Register
Rd $FF
None
MUL
Rd,Rr
Multiply Unsigned
R1:R0 Rd Rr (UU)
Z,C
2 (1)
MULS
Rd,Rr
Multiply Signed
R1:R0 Rd Rr (SS)
Z,C
2 (1)
MULSU
Rd,Rr
R1:R0 Rd Rr (SU)
Z,C
2 (1)
FMUL
Rd,Rr
Z,C
2 (1)
FMULS
Rd,Rr
Z,C
2 (1)
FMULSU
Rd,Rr
Z,C
2 (1)
Branch Instructions
RJMP
IJMP
Relative Jump
PC PC + k + 1
None
PC(15:0) Z, PC(21:16) 0
None
2 (1)
11
0856EAVR11/05
Operands
EIJMP
Description
Operation
Flags
#Clock
Note
None
2 (1)
JMP
Jump
PC k
None
3 (1)
RCALL
PC PC + k + 1
None
3 / 4 (4)
ICALL
PC(15:0) Z, PC(21:16) 0
None
3 / 4 (1)(4)
EICALL
None
4 (1)(4)
Call Subroutine
PC k
None
4 / 5 (1)(4)
RET
Subroutine Return
PC STACK
None
4 / 5 (4)
RETI
Interrupt Return
PC STACK
4 / 5 (4)
CALL
CPSE
Rd,Rr
if (Rd = Rr) PC PC + 2 or 3
None
1/2/3
CP
Rd,Rr
Compare
Rd - Rr
Z,C,N,V,S,H
CPC
Rd,Rr
Rd - Rr - C
Z,C,N,V,S,H
CPI
Rd,K
Rd - K
Z,C,N,V,S,H
SBRC
Rr, b
if (Rr(b)=0) PC PC + 2 or 3
None
1/2/3
SBRS
Rr, b
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
A, b
if(I/O(A,b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
A, b
If(I/O(A,b)=1) PC PC + 2 or 3
None
1/2/3
BRBS
s, k
None
1/2
BRBC
s, k
None
1/2
BREQ
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
BRNE
if (Z = 0) then PC PC + k + 1
None
1/2
BRCS
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
if (C = 0) then PC PC + k + 1
None
1/2
BRSH
if (C = 0) then PC PC + k + 1
None
1/2
BRLO
Branch if Lower
if (C = 1) then PC PC + k + 1
None
1/2
BRMI
Branch if Minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
Branch if Plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
if (T = 0) then PC PC + k + 1
None
1/2
BRVS
if (V = 1) then PC PC + k + 1
None
1/2
BRVC
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
if ( I = 1) then PC PC + k + 1
None
1/2
12
Operands
Description
Operation
Flags
#Clock
Note
BRID
if ( I = 0) then PC PC + k + 1
None
1/2
Rd, Rr
Copy Register
Rd Rr
None
MOVW
Rd, Rr
Rd+1:Rd Rr+1:Rr
None
1 (1)
LDI
Rd, K
Load Immediate
Rd K
None
LDS
Rd, k
Rd (k)
None
2 (1)(4)
LD
Rd, X
Load Indirect
Rd (X)
None
2 (2)(4)
LD
Rd, X+
Rd (X), X X + 1
None
2 (2)(4)
LD
Rd, -X
X X - 1, Rd (X)
None
2 (2)(4)
LD
Rd, Y
Load Indirect
Rd (Y)
None
2 (2)(4)
LD
Rd, Y+
Rd (Y), Y Y + 1
None
2 (2)(4)
LD
Rd, -Y
Y Y - 1, Rd (Y)
None
2 (2)(4)
LDD
Rd,Y+q
Rd (Y + q)
None
2 (1)(4)
LD
Rd, Z
Load Indirect
Rd (Z)
None
2 (2)(4)
LD
Rd, Z+
Rd (Z), Z Z+1
None
2 (2)(4)
LD
Rd, -Z
Z Z - 1, Rd (Z)
None
2 (2)(4)
LDD
Rd, Z+q
Rd (Z + q)
None
2 (1)(4)
STS
k, Rr
(k) Rd
None
2 (1)(4)
ST
X, Rr
Store Indirect
(X) Rr
None
2 (2)(4)
ST
X+, Rr
(X) Rr, X X + 1
None
2 (2)(4)
ST
-X, Rr
X X - 1, (X) Rr
None
2 (2)(4)
ST
Y, Rr
Store Indirect
(Y) Rr
None
2 (2)(4)
ST
Y+, Rr
(Y) Rr, Y Y + 1
None
2 (2)(4)
ST
-Y, Rr
Y Y - 1, (Y) Rr
None
2 (2)(4)
STD
Y+q,Rr
(Y + q) Rr
None
2 (1)(4)
ST
Z, Rr
Store Indirect
(Z) Rr
None
2 (2)(4)
ST
Z+, Rr
(Z) Rr, Z Z + 1
None
2 (2)(4)
ST
-Z, Rr
Z Z - 1, (Z) Rr
None
2 (2)(4)
STD
Z+q,Rr
(Z + q) Rr
None
2 (1)(4)
R0 (Z)
None
3 (3)
LPM
LPM
Rd, Z
Rd (Z)
None
3 (3)
LPM
Rd, Z+
Rd (Z), Z Z + 1
None
3 (3)
R0 (RAMPZ:Z)
None
3 (1)
Rd (RAMPZ:Z)
None
3 (1)
ELPM
ELPM
Rd, Z
13
0856EAVR11/05
Operands
Description
Operation
Flags
#Clock
Note
ELPM
Rd, Z+
Rd (RAMPZ:Z), Z Z + 1
None
3 (1)
(Z) R1:R0
None
- (1)
SPM
IN
Rd, A
Rd I/O(A)
None
OUT
A, Rr
I/O(A) Rr
None
PUSH
Rr
STACK Rr
None
2 (1)
POP
Rd
Rd STACK
None
2 (1)
Rd
Rd(n+1)Rd(n),Rd(0)0,CRd(7)
Z,C,N,V,H
LSR
Rd
Rd(n)Rd(n+1),Rd(7)0,CRd(0)
Z,C,N,V
ROL
Rd
Rd(0)C,Rd(n+1)Rd(n),CRd(7)
Z,C,N,V,H
ROR
Rd
Rd(7)C,Rd(n)Rd(n+1),CRd(0)
Z,C,N,V
ASR
Rd
Z,C,N,V
SWAP
Rd
Swap Nibbles
Rd(3..0) Rd(7..4)
None
BSET
Flag Set
SREG(s) 1
SREG(s)
BCLR
Flag Clear
SREG(s) 0
SREG(s)
SBI
A, b
I/O(A, b) 1
None
CBI
A, b
I/O(A, b) 0
None
BST
Rr, b
T Rr(b)
BLD
Rd, b
Rd(b) T
None
SEC
Set Carry
C1
CLC
Clear Carry
C0
SEN
N1
CLN
N0
SEZ
Z1
CLZ
Z0
SEI
I1
CLI
I0
SES
S1
CLS
S0
SEV
V1
CLV
V0
SET
Set T in SREG
T1
CLT
Clear T in SREG
T0
SEH
H1
CLH
H0
14
Operands
Description
Operation
Flags
#Clock
Note
None
1 (1)
None
Break
NOP
No Operation
SLEEP
Sleep
None
WDR
Watchdog Reset
None
Notes:
1. This instruction is not available in all devices. Refer to the device specific instruction set summary.
2. Not all variants of this instruction are available in all devices. Refer to the device specific instruction set summary.
3. Not all variants of the LPM instruction are available in all devices. Refer to the device specific instruction set summary. The
LPM instruction is not implemented at all in the AT90S1200 device.
4. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external
RAM interface. For LD, ST, LDS, STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL, ICALL,
EICALL, RCALL, RET, RETI in devices with 16-bit PC, add three cycles plus two cycles for each wait state. For CALL,
ICALL, EICALL, RCALL, RET, RETI in devices with 22-bit PC, add five cycles plus three cycles for each wait state.
15
0856EAVR11/05
Rd Rd + Rr + C
(i)
(i)
Syntax:
Operands:
Program Counter:
ADC Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0001
11rd
dddd
rrrr
H:
Rd3Rr3+Rr3R3+R3Rd3
Set if there was a carry from bit 3; cleared otherwise
S:
V:
Rd7Rr7R7+Rd7Rr7R7
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd7Rr7+Rr7R7+R7Rd7
Set if there was carry from the MSB of the result; cleared otherwise.
r2,r0
adc
r3,r1
Words: 1 (2 bytes)
Cycles: 1
16
Rd Rd + Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
ADD Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0000
11rd
dddd
rrrr
H:
Rd3Rr3+Rr3R3+R3Rd3
Set if there was a carry from bit 3; cleared otherwise
S:
V:
Rd7Rr7R7+Rd7Rr7R7
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
r1,r2
; Add r2 to r1 (r1=r1+r2)
add
r28,r28
Words: 1 (2 bytes)
Cycles: 1
17
0856EAVR11/05
Rd+1:Rd Rd+1:Rd + K
(i)
(i)
Syntax:
Operands:
Program Counter:
ADIW Rd+1:Rd,K
d {24,26,28,30}, 0 K 63
PC PC + 1
16-bit Opcode:
1001
0110
KKdd
KKKK
S:
V:
Rdh7 R15
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R15
Set if MSB of the result is set; cleared otherwise.
Z:
C:
R15 Rdh7
Set if there was carry from the MSB of the result; cleared otherwise.
Words: 1 (2 bytes)
Cycles: 2
18
Rd Rd Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
AND Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0010
00rd
dddd
rrrr
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r2,r3
ldi
r16,1
and
r2,r16
; Isolate bit 0 in r2
Words: 1 (2 bytes)
Cycles: 1
19
0856EAVR11/05
Rd Rd K
(i)
(i)
Syntax:
Operands:
Program Counter:
ANDI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0111
KKKK
dddd
KKKK
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
andi r18,$10
andi r19,$AA
Words: 1 (2 bytes)
Cycles: 1
20
(i)
b7-------------------b0
(i)
Syntax:
Operands:
Program Counter:
ASR Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0101
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd0
Set if, before the shift, the LSB of Rd was set; cleared otherwise.
r16,$10
asr
r16
; r16=r16 / 2
ldi
r17,$FC
; Load -4 in r17
asr
r17
; r17=r17/2
Words: 1 (2 bytes)
Cycles: 1
21
0856EAVR11/05
SREG(s) 0
(i)
(i)
Syntax:
Operands:
Program Counter:
BCLR s
0s7
PC PC + 1
16-bit Opcode:
1001
0100
1sss
1000
I:
0 if s = 7; Unchanged otherwise.
T:
0 if s = 6; Unchanged otherwise.
H:
0 if s = 5; Unchanged otherwise.
S:
0 if s = 4; Unchanged otherwise.
V:
0 if s = 3; Unchanged otherwise.
N:
0 if s = 2; Unchanged otherwise.
Z:
0 if s = 1; Unchanged otherwise.
C:
0 if s = 0; Unchanged otherwise.
Example:
bclr
bclr
; Disable interrupts
Words: 1 (2 bytes)
Cycles: 1
22
Rd(b) T
(i)
(i)
Syntax:
Operands:
Program Counter:
BLD Rd,b
0 d 31, 0 b 7
PC PC + 1
16 bit Opcode:
1111
100d
dddd
0bbb
Example:
; Copy bit
bst
r1,2
bld
r0,4
Words: 1 (2 bytes)
Cycles: 1
23
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
BRBC s,k
0 s 7, -64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
ksss
Example:
cpi
r20,5
brbc 1,noteq
...
noteq:nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
24
(i)
(i)
Syntax:
Operands:
Program Counter:
BRBS s,k
0 s 7, -64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
ksss
Example:
bst
r0,3
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
25
0856EAVR11/05
If C = 0 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRCC k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k000
Example:
add
r22,r23
brcc nocarry
...
nocarry: nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
26
If C = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRCS k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k000
Example:
cpi
r26,$56
brcs carry
...
carry: nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
27
0856EAVR11/05
BREAK Break
Description:
The BREAK instruction is used by the On-chip Debug system, and is normally not used in the application software. When
the BREAK instruction is executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip Debugger access to
internal resources.
If any Lock bits are set, or either the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK instruction as a NOP and will not enter the Stopped mode.
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
(i)
Syntax:
Operands:
Program Counter:
BREAK
None
PC PC + 1
16-bit Opcode:
1001
0101
1001
1000
Words: 1 (2 bytes)
Cycles: 1
28
If Rd = Rr (Z = 1) then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BREQ k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k001
Example:
cp
r1,r0
breq equal
...
equal: nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
29
0856EAVR11/05
If Rd Rr (N V = 0) then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRGE k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k100
Example:
cp
r11,r12
brge greateq
...
greateq: nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
30
If H = 0 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRHC k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k101
Example:
brhc hclear
...
hclear:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
31
0856EAVR11/05
If H = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRHS k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k101
Example:
brhs
hset
...
hset:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
32
If I = 0 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRID k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k111
Example:
brid intdis
...
intdis:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
33
0856EAVR11/05
If I = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRIE k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k111
Example:
brie
inten
...
inten:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
34
(i)
(i)
Syntax:
Operands:
Program Counter:
BRLO k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k000
Example:
loop:
eor
r19,r19
; Clear r19
inc
r19
; Increase r19
...
cpi
r19,$10
brlo loop
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
35
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
BRLT k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k100
Example:
cp
r16,r1
brlt less
; Compare r16 to r1
; Branch if r16 < r1 (signed)
...
less:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
36
If N = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRMI k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k010
Example:
subi
r18,4
brmi
negative
...
negative:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
37
0856EAVR11/05
If Rd Rr (Z = 0) then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRNE k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k001
Example:
loop:
eor
r27,r27
; Clear r27
inc
r27
; Increase r27
cpi
r27,5
; Compare r27 to 5
brne
loop
; Branch if r27<>5
...
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
38
If N = 0 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRPL k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k010
Example:
subi r26,$50
brpl positive
...
positive:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
39
0856EAVR11/05
If Rd Rr (C = 0) then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRSH k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k000
Example:
subi r19,4
brsh highsm
...
highsm:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
40
If T = 0 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRTC k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k110
Example:
bst
r3,5
brtc
tclear
...
tclear:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
41
0856EAVR11/05
If T = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRTS k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k110
Example:
bst
r3,5
brts tset
...
tset:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
42
(i)
If V = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRVC k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
01kk
kkkk
k011
Example:
add
r3,r4
brvc noover
; Add r4 to r3
; Branch if no overflow
...
noover:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
43
0856EAVR11/05
If V = 1 then PC PC + k + 1, else PC PC + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BRVS k
-64 k +63
PC PC + k + 1
PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k011
Example:
add
r3,r4
; Add r4 to r3
brvs
overfl
; Branch if overflow
...
overfl:
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false
2 if condition is true
44
SREG(s) 1
(i)
(i)
Syntax:
Operands:
Program Counter:
BSET s
0s7
PC PC + 1
16-bit Opcode:
1001
0100
0sss
1000
I:
1 if s = 7; Unchanged otherwise.
T:
1 if s = 6; Unchanged otherwise.
H:
1 if s = 5; Unchanged otherwise.
S:
1 if s = 4; Unchanged otherwise.
V:
1 if s = 3; Unchanged otherwise.
N:
1 if s = 2; Unchanged otherwise.
Z:
1 if s = 1; Unchanged otherwise.
C:
1 if s = 0; Unchanged otherwise.
Example:
bset
; Set T Flag
bset
; Enable interrupt
Words: 1 (2 bytes)
Cycles: 1
45
0856EAVR11/05
T Rd(b)
(i)
(i)
Syntax:
Operands:
Program Counter:
BST Rd,b
0 d 31, 0 b 7
PC PC + 1
16-bit Opcode:
1111
101d
dddd
0bbb
T:
Example:
; Copy bit
bst
r1,2
bld
r0,4
Words: 1 (2 bytes)
Cycles: 1
46
(i)
(ii)
PC k
PC k
Syntax:
Operands:
Program Counter
Stack:
(i)
CALL k
0 k < 64K
PC k
STACK PC+2
SP SP-2, (2 bytes, 16 bits)
(ii)
CALL k
0 k < 4M
PC k
STACK PC+2
SP SP-3 (3 bytes, 22 bits)
32-bit Opcode:
1001
010k
kkkk
111k
kkkk
kkkk
kkkk
kkkk
Example:
mov
r16,r0
; Copy r0 to r16
call
check
; Call subroutine
nop
...
check: cpi
breq
r16,$42
error
; Branch if equal
ret
...
error: rjmp
error
; Infinite loop
Words: 2 (4 bytes)
Cycles: 4, devices with 16 bit PC
5, devices with 22 bit PC
47
0856EAVR11/05
I/O(A,b) 0
(i)
(i)
Syntax:
Operands:
Program Counter:
CBI A,b
0 A 31, 0 b 7
PC PC + 1
16-bit Opcode:
1001
1000
AAAA
Abbb
Example:
cbi
$12,7
Words: 1 (2 bytes)
Cycles: 2
48
Rd Rd ($FF - K)
(i)
(i)
Syntax:
Operands:
Program Counter:
CBR Rd,K
16 d 31, 0 K 255
PC PC + 1
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r16,$F0
cbr
r18,1
Words: 1 (2 bytes)
Cycles: 1
49
0856EAVR11/05
C0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLC
None
PC PC + 1
16-bit Opcode:
1001
0100
1000
1000
C:
0
Carry Flag cleared
Example:
add
r0,r0
clc
; Add r0 to itself
; Clear Carry Flag
Words: 1 (2 bytes)
Cycles: 1
50
H0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLH
None
PC PC + 1
16-bit Opcode:
1001
0100
1101
1000
H:
0
Half Carry Flag cleared
Example:
clh
Words: 1 (2 bytes)
Cycles: 1
51
0856EAVR11/05
I0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLI
None
PC PC + 1
16-bit Opcode:
1001
0100
1111
1000
I:
0
Global Interrupt Flag cleared
Example:
in
cli
sbi
sbi
EECR, EEWE
out
Words: 1 (2 bytes)
Cycles: 1
52
N0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLN
None
PC PC + 1
16-bit Opcode:
1001
0100
1010
1000
N:
0
Negative Flag cleared
Example:
add
cln
r2,r3
; Add r3 to r2
; Clear Negative Flag
Words: 1 (2 bytes)
Cycles: 1
53
0856EAVR11/05
Rd Rd Rd
(i)
(i)
Syntax:
Operands:
Program Counter:
CLR Rd
0 d 31
PC PC + 1
01dd
dddd
dddd
S:
0
Cleared
V:
0
Cleared
N:
0
Cleared
Z:
1
Set
clr
r18
; clear r18
inc
r18
; increase r18
r18,$50
...
cpi
brne loop
Words: 1 (2 bytes)
Cycles: 1
54
S0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLS
None
PC PC + 1
16-bit Opcode:
1001
0100
1100
1000
S:
0
Signed Flag cleared
Example:
add
cls
r2,r3
; Add r3 to r2
; Clear Signed Flag
Words: 1 (2 bytes)
Cycles: 1
55
0856EAVR11/05
T0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLT
None
PC PC + 1
16-bit Opcode:
1001
0100
1110
1000
T:
0
T Flag cleared
Example:
clt
; Clear T Flag
Words: 1 (2 bytes)
Cycles: 1
56
V0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLV
None
PC PC + 1
16-bit Opcode:
1001
0100
1011
1000
V:
0
Overflow Flag cleared
Example:
add
clv
r2,r3
; Add r3 to r2
; Clear Overflow Flag
Words: 1 (2 bytes)
Cycles: 1
57
0856EAVR11/05
Z0
(i)
(i)
Syntax:
Operands:
Program Counter:
CLZ
None
PC PC + 1
16-bit Opcode:
1001
0100
1001
1000
Z:
0
Zero Flag cleared
Example:
add
clz
r2,r3
; Add r3 to r2
; Clear zero
Words: 1 (2 bytes)
Cycles: 1
58
Rd $FF - Rd
(i)
(i)
Syntax:
Operands:
Program Counter:
COM Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0000
S:
NV
For signed tests.
V:
0
Cleared.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; Cleared otherwise.
C:
1
Set.
r4
breq
zero
; Branch if zero
...
zero:
nop
Words: 1 (2 bytes)
Cycles: 1
59
0856EAVR11/05
CP Compare
Description:
This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All conditional
branches can be used after this instruction.
Operation:
(i)
Rd - Rr
(i)
Syntax:
Operands:
Program Counter:
CP Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0001
01rd
dddd
rrrr
H:
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
r4,r19
brne noteq
...
noteq: nop
Words: 1 (2 bytes)
Cycles: 1
60
(i)
Rd - Rr - C
(i)
Syntax:
Operands:
Program Counter:
CPC Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0000
01rd
dddd
rrrr
H:
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0 Z
Previous value remains unchanged when the result is zero; cleared otherwise.
C:
r2,r0
cpc
r3,r1
brne
noteq
...
noteq: nop
61
0856EAVR11/05
Words: 1 (2 bytes)
Cycles: 1
62
(i)
Rd - K
(i)
Syntax:
Operands:
Program Counter:
CPI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0011
KKKK
dddd
KKKK
H:
S:
V:
Rd7 K7 R7 +Rd7 K7 R7
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
r19,3
brne
error
; Branch if r19<>3
...
error:
nop
Words: 1 (2 bytes)
Cycles: 1
63
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
CPSE Rd,Rr
0 d 31, 0 r 31
16-bit Opcode:
0001
00rd
dddd
rrrr
Example:
inc
r4
; Increase r4
cpse
r4,r0
; Compare r4 to r0
neg
r4
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
64
Rd Rd - 1
(i)
(i)
Syntax:
Operands:
Program Counter:
DEC Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
1010
S:
NV
For signed tests.
V:
R7 R6 R5 R4 R3 R2 R1 R0
Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs
if and only if Rd was $80 before the operation.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; Cleared otherwise.
ldi
r17,$10
add
r1,r2
; Add r2 to r1
dec
r17
; Decrement r17
brne loop
; Branch if r17<>0
nop
Words: 1 (2 bytes)
Cycles: 1
65
0856EAVR11/05
(i)
PC(15:0) Z(15:0)
PC(21:16) EIND
Syntax:
Operands:
Program Counter:
Stack:
(i)
EICALL
None
See Operation
STACK PC + 1
SP SP - 3 (3 bytes, 22 bits)
16-bit Opcode:
1001
0101
0001
1001
Example:
ldi
r16,$05
out
EIND,r16
ldi
r30,$00
ldi
r31,$10
eicall
; Call to $051000
Words: 1 (2 bytes)
Cycles: 4 (only implemented in devices with 22 bit PC)
66
(i)
PC(15:0) Z(15:0)
PC(21:16) EIND
(i)
EIJMP
Syntax:
Operands:
None
Program Counter:
Stack:
See Operation
Not Affected
16-bit Opcode:
1001
0100
0001
1001
Example:
ldi
r16,$05
out
EIND,r16
ldi
r30,$00
ldi
r31,$10
eijmp
; Jump to $051000
Words: 1 (2 bytes)
Cycles: 2
67
0856EAVR11/05
(i)
(ii)
(iii)
(i)
(ii)
(iii)
Operation:
Comment:
R0 (RAMPZ:Z)
Rd (RAMPZ:Z)
Rd (RAMPZ:Z)
(RAMPZ:Z) (RAMPZ:Z) + 1
Syntax:
Operands:
Program Counter:
ELPM
ELPM Rd, Z
ELPM Rd, Z+
None, R0 implied
0 d 31
0 d 31
PC PC + 1
PC PC + 1
PC PC + 1
16 bit Opcode:
(i)
1001
0101
1101
1000
(ii)
1001
000d
dddd
0110
(iii)
1001
000d
dddd
0111
Example:
ldi
out
RAMPZ, ZL
ldi
ZH, byte2(Table_1<<1)
ldi
ZL, byte1(Table_1<<1)
elpm r16, Z+
...
Table_1:
.dw 0x3738
68
Words: 1 (2 bytes)
Cycles: 3
69
0856EAVR11/05
EOR Exclusive OR
Description:
Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination register Rd.
Operation:
Rd Rd Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
EOR Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0010
01rd
dddd
rrrr
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r4,r4
; Clear r4
eor
r0,r22
Words: 1 (2 bytes)
Cycles: 1
70
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A
multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left
shift is required for the high byte of the product to be in the same format as the inputs. The FMUL instruction incorporates
the shift operation in the same number of cycles as MUL.
The (1.7) format is most commonly used with signed numbers, while FMUL performs an unsigned multiplication. This
instruction is therefore most useful for calculating one of the partial products when performing a signed multiplication with
16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the FMUL operation may suffer
from a 2s complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example.
The multiplicand Rd and the multiplier Rr are two registers containing unsigned fractional numbers where the implicit radix
point lies between bit 6 and bit 7. The 16-bit unsigned fractional product with the implicit radix point between bit 14 and bit
15 is placed in R1 (high byte) and R0 (low byte).
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
(i)
FMUL Rd,Rr
16 d 23, 16 r 23
PC PC + 1
16-bit Opcode:
0000
0011
0ddd
1rrr
C:
R16
Set if bit 15 of the result before left shift is set; cleared otherwise.
Z:
71
0856EAVR11/05
Example:
;******************************************************************************
;* DESCRIPTION
;*Signed fractional multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;*r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;******************************************************************************
fmuls16x16_32:
clrr2
fmulsr23, r21;((signed)ah * (signed)bh) << 1
movwr19:r18, r1:r0
fmulr22, r20;(al * bl) << 1
adcr18, r2
movwr17:r16, r1:r0
fmulsur23, r20;((signed)ah * bl) << 1
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
fmulsur21, r22;((signed)bh * al) << 1
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
Words: 1 (2 bytes)
Cycles: 2
72
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A
multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left
shift is required for the high byte of the product to be in the same format as the inputs. The FMULS instruction incorporates
the shift operation in the same number of cycles as MULS.
The multiplicand Rd and the multiplier Rr are two registers containing signed fractional numbers where the implicit radix
point lies between bit 6 and bit 7. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15
is placed in R1 (high byte) and R0 (low byte).
Note that when multiplying 0x80 (-1) with 0x80 (-1), the result of the shift operation is 0x8000 (-1). The shift operation thus
gives a twos complement overflow. This must be checked and handled by software.
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
(i)
FMULS Rd,Rr
16 d 23, 16 r 23
PC PC + 1
16-bit Opcode:
0000
0011
1ddd
0rrr
C:
R16
Set if bit 15 of the result before left shift is set; cleared otherwise.
Z:
; Multiply signed r23 and r22 in (1.7) format, result in (1.15) format
movw r23:r22,r1:r0
73
0856EAVR11/05
Words: 1 (2 bytes)
Cycles: 2
74
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A
multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left
shift is required for the high byte of the product to be in the same format as the inputs. The FMULSU instruction incorporates the shift operation in the same number of cycles as MULSU.
The (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication with one unsigned
and one signed input. This instruction is therefore most useful for calculating two of the partial products when performing a
signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the
FMULSU operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of
the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example.
The multiplicand Rd and the multiplier Rr are two registers containing fractional numbers where the implicit radix point lies
between bit 6 and bit 7. The multiplicand Rd is a signed fractional number, and the multiplier Rr is an unsigned fractional
number. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high
byte) and R0 (low byte).
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
(i)
FMULSU Rd,Rr
16 d 23, 16 r 23
PC PC + 1
16-bit Opcode:
0000
0011
1ddd
1rrr
C:
R16
Set if bit 15 of the result before left shift is set; cleared otherwise.
Z:
75
0856EAVR11/05
Example:
;******************************************************************************
;* DESCRIPTION
;*Signed fractional multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;*r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;******************************************************************************
fmuls16x16_32:
clrr2
fmulsr23, r21;((signed)ah * (signed)bh) << 1
movwr19:r18, r1:r0
fmulr22, r20;(al * bl) << 1
adcr18, r2
movwr17:r16, r1:r0
fmulsur23, r20;((signed)ah * bl) << 1
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
fmulsur21, r22;((signed)bh * al) << 1
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
Words: 1 (2 bytes)
Cycles: 2
76
PC(15:0) Z(15:0) Devices with 16 bits PC, 128K bytes Program memory maximum.
PC(15:0) Z(15:0) Devices with 22 bits PC, 8M bytes Program memory maximum.
PC(21:16) 0
(i)
(ii)
Syntax:
Operands:
Program Counter:
Stack:
(i)
ICALL
None
See Operation
STACK PC + 1
SP SP - 2 (2 bytes, 16 bits)
(ii)
ICALL
None
See Operation
STACK PC + 1
SP SP - 3 (3 bytes, 22 bits)
16-bit Opcode:
1001
0101
0000
1001
Example:
mov
icall
r30,r0
Words: 1 (2 bytes)
Cycles: 3 devices with 16 bit PC
4 devices with 22 bit PC
77
0856EAVR11/05
PC Z(15:0)
Devices with 16 bits PC, 128K bytes Program memory maximum.
PC(15:0) Z(15:0) Devices with 22 bits PC, 8M bytes Program memory maximum.
PC(21:16) 0
(i)
(ii)
Syntax:
(i),(ii)
Operands:
IJMP
None
Program Counter:
Stack:
See Operation
Not Affected
16-bit Opcode:
1001
0100
0000
1001
Example:
mov
ijmp
r30,r0
Words: 1 (2 bytes)
Cycles: 2
78
Rd I/O(A)
(i)
(i)
Syntax:
Operands:
Program Counter:
IN Rd,A
0 d 31, 0 A 63
PC PC + 1
16-bit Opcode:
1011
0AAd
dddd
AAAA
Example:
in
r25,$16
; Read Port B
cpi
r25,4
breq
exit
; Branch if r25=4
...
exit:
nop
Words: 1 (2 bytes)
Cycles: 1
79
0856EAVR11/05
INC Increment
Description:
Adds one -1- to the contents of register Rd and places the result in the destination register Rd.
The C Flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in multiple-precision computations.
When operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently. When
operating on twos complement values, all signed branches are available.
Operation:
Rd Rd + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
INC Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0011
S:
NV
For signed tests.
V:
R7 R6 R5 R4 R3 R2 R1 R0
Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs
if and only if Rd was $7F before the operation.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4R3 R2 R1 R0
Set if the result is $00; Cleared otherwise.
clr
r22
; clear r22
inc
r22
; increment r22
cpi
r22,$4F
brne
loop
...
nop
80
81
0856EAVR11/05
JMP Jump
Description:
Jump to an address within the entire 4M (words) Program memory. See also RJMP.
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
PC k
Syntax:
Operands:
Program Counter:
Stack:
(i)
JMP k
0 k < 4M
PC k
Unchanged
32-bit Opcode:
1001
010k
kkkk
110k
kkkk
kkkk
kkkk
kkkk
Example:
mov
r1,r0
; Copy r0 to r1
jmp
farplc
; Unconditional jump
...
farplc: nop
Words: 2 (4 bytes)
Cycles: 3
82
(i)
(ii)
(iii)
(i)
(ii)
(iii)
Operation:
Comment:
Rd (X)
Rd (X)
XX-1
XX+1
Rd (X)
X: Unchanged
X: Post incremented
X: Pre decremented
Syntax:
Operands:
Program Counter:
LD Rd, X
LD Rd, X+
LD Rd, -X
0 d 31
0 d 31
0 d 31
PC PC + 1
PC PC + 1
PC PC + 1
16-bit Opcode:
(i)
1001
000d
dddd
1100
(ii)
1001
000d
dddd
1101
(iii)
1001
000d
dddd
1110
Example:
clr
r27
ldi
r26,$60
83
0856EAVR11/05
ld
r0,X+
ld
r1,X
ldi
r26,$63
ld
r2,X
ld
r3,X
Words: 1 (2 bytes)
Cycles: 2
84
(i)
(ii)
(iii)
(iiii)
(i)
(ii)
(iii)
(iiii)
Operation:
Comment:
Rd (Y)
Rd (Y)
YY-1
Rd (Y+q)
YY+1
Rd (Y)
Y: Unchanged
Y: Post incremented
Y: Pre decremented
Y: Unchanged, q: Displacement
Syntax:
Operands:
Program Counter:
LD Rd, Y
LD Rd, Y+
LD Rd, -Y
LDD Rd, Y+q
0 d 31
0 d 31
0 d 31
0 d 31, 0 q 63
PC PC + 1
PC PC + 1
PC PC + 1
PC PC + 1
85
0856EAVR11/05
16-bit Opcode:
(i)
1000
000d
dddd
1000
(ii)
1001
000d
dddd
1001
(iii)
1001
000d
dddd
1010
(iiii)
10q0
qq0d
dddd
1qqq
Example:
clr
r29
ldi
r28,$60
ld
r0,Y+
ld
r1,Y
ldi
r28,$63
ld
r2,Y
ld
r3,-Y
ldd
r4,Y+2
Words: 1 (2 bytes)
Cycles: 2
86
(i)
(ii)
(iii)
(iiii)
(i)
(ii)
(iii)
(iiii)
Operation:
Comment:
Rd (Z)
Rd (Z)
Z Z -1
Rd (Z+q)
ZZ+1
Rd (Z)
Z: Unchanged
Z: Post increment
Z: Pre decrement
Z: Unchanged, q: Displacement
Syntax:
Operands:
Program Counter:
LD Rd, Z
LD Rd, Z+
LD Rd, -Z
LDD Rd, Z+q
0 d 31
0 d 31
0 d 31
0 d 31, 0 q 63
PC PC + 1
PC PC + 1
PC PC + 1
PC PC + 1
87
0856EAVR11/05
16-bit Opcode:
(i)
1000
000d
dddd
0000
(ii)
1001
000d
dddd
0001
(iii)
1001
000d
dddd
0010
(iiii)
10q0
qq0d
dddd
0qqq
Example:
clr
r31
ldi
r30,$60
ld
r0,Z+
ld
r1,Z
ldi
r30,$63
ld
r2,Z
ld
r3,-Z
ldd
r4,Z+2
Words: 1 (2 bytes)
Cycles: 2
88
Rd K
(i)
(i)
Syntax:
Operands:
Program Counter:
LDI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
1110
KKKK
dddd
KKKK
Example:
clr
r31
ldi
r30,$F0
lpm
Words: 1 (2 bytes)
Cycles: 1
89
0856EAVR11/05
Rd (k)
(i)
(i)
Syntax:
Operands:
Program Counter:
LDS Rd,k
0 d 31, 0 k 65535
PC PC + 2
32-bit Opcode:
1001
000d
dddd
0000
kkkk
kkkk
kkkk
kkkk
Example:
lds
r2,$FF00
add
r2,r1
; add r1 to r2
sts
$FF00,r2
; Write back
Words: 2 (4 bytes)
Cycles: 2
90
(i)
(ii)
(iii)
(i)
(ii)
(iii)
Operation:
Comment:
R0 (Z)
Rd (Z)
Rd (Z)
ZZ+1
Syntax:
Operands:
Program Counter:
LPM
LPM Rd, Z
LPM Rd, Z+
None, R0 implied
0 d 31
0 d 31
PC PC + 1
PC PC + 1
PC PC + 1
16-bit Opcode:
(i)
1001
0101
1100
1000
(ii)
1001
000d
dddd
0100
(iii)
1001
000d
dddd
0101
Example:
ldi
ldi
ZL, low(Table_1<<1)
lpm
r16, Z
...
Table_1:
.dw 0x5876
...
91
0856EAVR11/05
Words: 1 (2 bytes)
Cycles: 3
92
(i)
(i)
b7 - - - - - - - - - - - - - - - - - - b0
Syntax:
Operands:
Program Counter:
LSL Rd
0 d 31
PC PC + 1
11dd
dddd
dddd
H:
Rd3
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd7
Set if, before the shift, the MSB of Rd was set; cleared otherwise.
r0,r4
; Add r4 to r0
lsl
r0
; Multiply r0 by 2
Words: 1 (2 bytes)
Cycles: 1
93
0856EAVR11/05
(i)
b7 - - - - - - - - - - - - - - - - - - b0
Syntax:
Operands:
Program Counter:
LSR Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0110
S:
V:
N:
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd0
Set if, before the shift, the LSB of Rd was set; cleared otherwise.
r0,r4
; Add r4 to r0
lsr
r0
; Divide r0 by 2
Words: 1 (2 bytes)
Cycles: 1
94
Rd Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
MOV Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0010
11rd
dddd
rrrr
Example:
mov
r16,r0
; Copy r0 to r16
call
check
; Call subroutine
r16,$11
...
check:
cpi
...
ret
Words: 1 (2 bytes)
Cycles: 1
95
0856EAVR11/05
Rd+1:Rd Rr+1:Rr
(i)
Syntax:
Operands:
Program Counter:
(i)
PC PC + 1
16-bit Opcode:
0000
0001
dddd
rrrr
Example:
movw
call
check
; Call subroutine
r16,$11
r17,$32
...
check:
cpi
...
cpi
...
ret
Words: 1 (2 bytes)
Cycles: 1
96
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
The multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned product is
placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0 or R1 the result
will overwrite those after multiplication.
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
MUL Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
1001
11rd
dddd
rrrr
C:
R15
Set if bit 15 of the result is set; cleared otherwise.
Z:
r5,r4
movw r4,r0
Words: 1 (2 bytes)
Cycles: 2
97
0856EAVR11/05
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
The multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is placed
in R1 (high byte) and R0 (low byte).
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
MULS Rd,Rr
16 d 31, 16 r 31
PC PC + 1
16-bit Opcode:
0000
0010
dddd
rrrr
C:
R15
Set if bit 15 of the result is set; cleared otherwise.
Z:
movw r20,r0
Words: 1 (2 bytes)
Cycles: 2
98
Rr
Multiplicand
Multiplier
R1
R0
Product High
Product Low
16
The multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the multiplier Rr is
unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
(i)
R1:R0 Rd Rr
Syntax:
Operands:
Program Counter:
MULSU Rd,Rr
16 d 23, 16 r 23
PC PC + 1
16-bit Opcode:
0000
0011
0ddd
0rrr
C:
R15
Set if bit 15 of the result is set; cleared otherwise.
Z:
99
0856EAVR11/05
movwr19:r18, r1:r0
mulr22, r20; al * bl
movwr17:r16, r1:r0
mulsur23, r20; (signed)ah * bl
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
mulsur21, r22; (signed)bh * al
sbcr19, r2
addr17, r0
adcr18, r1
adcr19, r2
ret
Words: 1 (2 bytes)
Cycles: 2
100
Rd $00 - Rd
(i)
(i)
Syntax:
Operands:
Program Counter:
NEG Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0001
H:
R3 + Rd3
Set if there was a borrow from bit 3; cleared otherwise
S:
NV
For signed tests.
V:
R7 R6 R5 R4 R3 R2 R1 R0
Set if there is a twos complement overflow from the implied subtraction from zero; cleared otherwise. A twos complement overflow will occur if and only if the contents of the Register after operation (Result) is $80.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; Cleared otherwise.
C:
R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C Flag will be set in all cases
except when the contents of Register after operation is $00.
positive:
r11,r0
brpl positive
neg
nop
r11
Words: 1 (2 bytes)
Cycles: 1
101
0856EAVR11/05
NOP No Operation
Description:
This instruction performs a single cycle No Operation.
Operation:
(i)
No
(i)
Syntax:
Operands:
Program Counter:
NOP
None
PC PC + 1
16-bit Opcode:
0000
0000
0000
0000
Example:
clr
r16
; Clear r16
ser
r17
; Set r17
out
$18,r16
nop
out
Words: 1 (2 bytes)
Cycles: 1
102
Rd Rd v Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
OR Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0010
10rd
dddd
rrrr
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r15,r16
bst
r15,6
brts
ok
...
ok:
nop
Words: 1 (2 bytes)
Cycles: 1
103
0856EAVR11/05
Rd Rd v K
(i)
(i)
Syntax:
Operands:
Program Counter:
ORI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0110
KKKK
dddd
KKKK
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r16,$F0
ori
r17,1
Words: 1 (2 bytes)
Cycles: 1
104
I/O(A) Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
OUT A,Rr
0 r 31, 0 A 63
PC PC + 1
16-bit Opcode:
1011
1AAr
rrrr
AAAA
Example:
clr
r16
ser
r17
; Set r17
out
$18,r16
nop
out
; Clear r16
Words: 1 (2 bytes)
Cycles: 1
105
0856EAVR11/05
Rd STACK
(i)
(i)
Syntax:
Operands:
Program Counter:
Stack:
POP Rd
0 d 31
PC PC + 1
SP SP + 1
16-bit Opcode:
1001
000d
dddd
1111
Example:
call
routine
; Call subroutine
...
routine:
push
r14
push
r13
pop
r13
; Restore r13
pop
r14
; Restore r14
...
ret
Words: 1 (2 bytes)
Cycles: 2
106
STACK Rr
(i)
Syntax:
(i)
PUSH Rr
Operands:
Program Counter:
Stack:
0 r 31
PC PC + 1
SP SP - 1
16-bit Opcode:
1001
001d
dddd
1111
Example:
call
...
routine:
push
r14
push
r13
pop
r13
; Restore r13
pop
r14
...
ret
; Restore r14
; Return from subroutine
Words: 1 (2 bytes)
Cycles: 2
107
0856EAVR11/05
PC PC + k + 1
PC PC + k + 1
Syntax:
Operands:
Program Counter:
Stack:
(i)
RCALL k
-2K k < 2K
PC PC + k + 1
STACK PC + 1
SP SP - 2 (2 bytes, 16 bits)
(ii)
RCALL k
-2K k < 2K
PC PC + k + 1
STACK PC + 1
SP SP - 3 (3 bytes, 22 bits)
(i)
(ii)
16-bit Opcode:
1101
kkkk
kkkk
kkkk
Example:
rcall
routine
; Call subroutine
r14
r14
; Restore r14
...
routine:
push
...
pop
ret
Words: 1 (2 bytes)
Cycles: 3 devices with 16-bit PC
4 devices with 22-bit PC
108
PC(15:0) STACK Devices with 16 bits PC, 128K bytes Program memory maximum.
PC(21:0) STACKDevices with 22 bits PC, 8M bytes Program memory maximum.
(i)
(ii)
Syntax:
Operands:
Program Counter:
Stack:
(i)
RET
None
See Operation
(ii)
RET
None
See Operation
16-bit Opcode:
1001
0101
0000
1000
call
routine
; Call subroutine
r14
r14
; Restore r14
Example:
...
routine:
push
...
pop
ret
Words: 1 (2 bytes)
Cycles: 4 devices with 16-bit PC
5 devices with 22-bit PC
109
0856EAVR11/05
(i)
(ii)
PC(15:0) STACK Devices with 16 bits PC, 128K bytes Program memory maximum.
PC(21:0) STACKDevices with 22 bits PC, 8M bytes Program memory maximum.
Syntax:
Operands:
Program Counter:
Stack
(i)
RETI
None
See Operation
SP SP + 2 (2 bytes, 16 bits)
(ii)
RETI
None
See Operation
SP SP + 3 (3 bytes, 22 bits)
16-bit Opcode:
1001
0101
0001
1000
I:
1
The I Flag is set.
Example:
...
extint:
push
r0
...
pop
r0
reti
; Restore r0
; Return and enable interrupts
Words: 1 (2 bytes)
Cycles: 4 devices with 16-bit PC
5 devices with 22-bit PC
110
PC PC + k + 1
(i)
(i)
Syntax:
Operands:
Program Counter:
Stack
RJMP k
-2K k < 2K
PC PC + k + 1
Unchanged
16-bit Opcode:
1100
kkkk
kkkk
kkkk
Example:
error:
ok:
cpi
r16,$42
brne
error
rjmp
ok
; Unconditional branch
add
r16,r17
inc
r16
; Increment r16
nop
Words: 1 (2 bytes)
Cycles: 2
111
0856EAVR11/05
(i)
b7 - - - - - - - - - - - - - - - - - - b0
Syntax:
Operands:
Program Counter:
ROL Rd
0 d 31
PC PC + 1
11dd
dddd
dddd
H:
Rd3
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd7
Set if, before the shift, the MSB of Rd was set; cleared otherwise.
r18
rol
r19
brcs oneenc
...
oneenc:
nop
Words: 1 (2 bytes)
Cycles: 1
112
(i)
b7 - - - - - - - - - - - - - - - - - - b0
Syntax:
Operands:
Program Counter:
ROR Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0111
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
Rd0
Set if, before the shift, the LSB of Rd was set; cleared otherwise.
r19
ror
r18
brcc zeroenc1
asr
r17
ror
r16
brcc zeroenc2
...
zeroenc1:
nop
...
113
0856EAVR11/05
zeroenc1:
nop
Words: 1 (2 bytes)
Cycles: 1
114
Rd Rd - Rr - C
(i)
(i)
Syntax:
Operands:
Program Counter:
SBC Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0000
10rd
dddd
rrrr
H:
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0 Z
Previous value remains unchanged when the result is zero; cleared otherwise.
C:
r2,r0
sbc
r3,r1
Words: 1 (2 bytes)
Cycles: 1
115
0856EAVR11/05
Rd Rd - K - C
(i)
(i)
Syntax:
Operands:
Program Counter:
SBCI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0100
KKKK
dddd
KKKK
H:
Rd3 K3 + K3 R3 + R3 Rd3
Set if there was a borrow from bit 3; cleared otherwise
S:
V:
Rd7 K7 R7 +Rd7 K7 R7
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0 Z
Previous value remains unchanged when the result is zero; cleared otherwise.
C:
sbci r17,$4F
Words: 1 (2 bytes)
Cycles: 1
116
I/O(A,b) 1
(i)
(i)
Syntax:
Operands:
Program Counter:
SBI A,b
0 A 31, 0 b 7
PC PC + 1
16-bit Opcode:
1001
1010
AAAA
Abbb
Example:
out
$1E,r0
sbi
$1C,0
in
r1,$1D
Words: 1 (2 bytes)
Cycles: 2
117
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
SBIC A,b
0 A 31, 0 b 7
16-bit Opcode:
1001
1001
AAAA
Abbb
Example:
e2wait:
sbic $1C,1
rjmp e2wait
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
118
(i)
(i)
Syntax:
Operands:
Program Counter:
SBIS A,b
0 A 31, 0 b 7
16-bit Opcode:
1001
1011
AAAA
Abbb
Example:
waitset: sbis $10,0
rjmp waitset
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
119
0856EAVR11/05
Rd+1:Rd Rd+1:Rd - K
(i)
(i)
Syntax:
Operands:
Program Counter:
SBIW Rd+1:Rd,K
d {24,26,28,30}, 0 K 63
PC PC + 1
16-bit Opcode:
1001
0111
KKdd
KKKK
S:
V:
Rdh7 R15
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R15
Set if MSB of the result is set; cleared otherwise.
Z:
C:
R15 Rdh7
Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
r25:r24,1
sbiw
YH:YL,63
Words: 1 (2 bytes)
Cycles: 2
120
Rd Rd v K
(i)
(i)
Syntax:
Operands:
Program Counter:
SBR Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0110
KKKK
dddd
KKKK
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r16,3
sbr
r17,$F0
Words: 1 (2 bytes)
Cycles: 1
121
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
SBRC Rr,b
0 r 31, 0 b 7
16-bit Opcode:
1111
110r
rrrr
0bbb
Example:
sub
r0,r1
sbrc r0,7
sub
nop
r0,r1
; Subtract r1 from r0
; Skip if bit 7 in r0 cleared
; Only executed if bit 7 in r0 not cleared
; Continue (do nothing)
Words: 1 (2 bytes)
Cycles: 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
122
(i)
(i)
Syntax:
Operands:
Program Counter:
SBRS Rr,b
0 r 31, 0 b 7
16-bit Opcode:
1111
111r
rrrr
0bbb
Example:
sub
r0,r1
; Subtract r1 from r0
sbrs
r0,7
neg
r0
nop
Words: 1 (2 bytes)
Cycles: 1 if condition is false (no skip)
2 if condition is true (skip is executed) and the instruction skipped is 1 word
3 if condition is true (skip is executed) and the instruction skipped is 2 words
123
0856EAVR11/05
C1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEC
None
PC PC + 1
16-bit Opcode:
1001
0100
0000
1000
C:
1
Carry Flag set
Example:
sec
adc
; r0=r0+r1+1
Words: 1 (2 bytes)
Cycles: 1
124
H1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEH
None
PC PC + 1
16-bit Opcode:
1001
0100
0101
1000
H:
1
Half Carry Flag set
Example:
seh
Words: 1 (2 bytes)
Cycles: 1
125
0856EAVR11/05
I1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEI
None
PC PC + 1
16-bit Opcode:
1001
0100
0111
1000
I:
1
Global Interrupt Flag set
Example:
sei
sleep
Words: 1 (2 bytes)
Cycles: 1
126
N1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEN
None
PC PC + 1
16-bit Opcode:
1001
0100
0010
1000
N:
1
Negative Flag set
Example:
add
sen
r2,r19
; Add r19 to r2
; Set Negative Flag
Words: 1 (2 bytes)
Cycles: 1
127
0856EAVR11/05
Rd $FF
(i)
(i)
Syntax:
Operands:
Program Counter:
SER Rd
16 d 31
PC PC + 1
16-bit Opcode:
1110
1111
dddd
1111
Example:
clr
r16
ser
r17
; Set r17
out
$18,r16
nop
out
; Clear r16
Words: 1 (2 bytes)
Cycles: 1
128
S1
(i)
(i)
Syntax:
Operands:
Program Counter:
SES
None
PC PC + 1
16-bit Opcode:
1001
0100
0100
1000
S:
1
Signed Flag set
Example:
add
ses
r2,r19
; Add r19 to r2
; Set Negative Flag
Words: 1 (2 bytes)
Cycles: 1
129
0856EAVR11/05
T1
(i)
(i)
Syntax:
Operands:
Program Counter:
SET
None
PC PC + 1
16-bit Opcode:
1001
0100
0110
1000
T:
1
T Flag set
Example:
set
; Set T Flag
Words: 1 (2 bytes)
Cycles: 1
130
V1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEV
None
PC PC + 1
16-bit Opcode:
1001
0100
0011
1000
V:
1
Overflow Flag set
Example:
add
sev
r2,r19
; Add r19 to r2
; Set Overflow Flag
Words: 1 (2 bytes)
Cycles: 1
131
0856EAVR11/05
Z1
(i)
(i)
Syntax:
Operands:
Program Counter:
SEZ
None
PC PC + 1
16-bit Opcode:
1001
0100
0001
1000
Z:
1
Zero Flag set
Example:
add
sez
r2,r19
; Add r19 to r2
; Set Zero Flag
Words: 1 (2 bytes)
Cycles: 1
132
Operands:
Program Counter:
SLEEP
None
PC PC + 1
16-bit Opcode:
1001
0101
1000
1000
Example:
mov
r0,r11
; Copy r11 to r0
ldi
r16,(1<<SE)
out
MCUCR, r16
sleep
Words: 1 (2 bytes)
Cycles: 1
133
0856EAVR11/05
1. R1 determines the instruction high byte, and R0 determines the instruction low byte.
Operation:
Comment:
(i)
(ii)
(iii)
(iv)
(v)
(RAMPZ:Z) $ffff
(RAMPZ:Z) R1:R0
(RAMPZ:Z) R1:R0
(RAMPZ:Z) TEMP
BLBITS R1:R0
Syntax:
Operands:
Program Counter:
SPM
None
PC PC + 1
(i)-(v)
16-bit Opcode:
1001
0101
1110
1000
Example:
;This example shows SPM write of one page for devices with page write
;- the routine writes one page of data from RAM to Flash
;
134
135
0856EAVR11/05
ret
Words: 1 (2 bytes)
Cycles: depends on the operation
136
(i)
(ii)
(iii)
(i)
(ii)
(iii)
Operation:
Comment:
(X) Rr
(X) Rr
XX-1
X X+1
(X) Rr
X: Unchanged
X: Post incremented
X: Pre decremented
Syntax:
Operands:
Program Counter:
ST X, Rr
ST X+, Rr
ST -X, Rr
0 r 31
0 r 31
0 r 31
PC PC + 1
PC PC + 1
PC PC + 1
16-bit Opcode :
(i)
1001
001r
rrrr
1100
(ii)
1001
001r
rrrr
1101
(iii)
1001
001r
rrrr
1110
137
0856EAVR11/05
Example:
clr
r27
ldi
r26,$60
st
X+,r0
st
X,r1
ldi
r26,$63
st
X,r2
st
-X,r3
Words: 1 (2 bytes)
Cycles: 2
138
(i)
(ii)
(iii)
(iiii)
(i)
(ii)
(iii)
(iiii)
Operation:
Comment:
(Y) Rr
(Y) Rr
YY-1
(Y+q) Rr
Y Y+1
(Y) Rr
Y: Unchanged
Y: Post incremented
Y: Pre decremented
Y: Unchanged, q: Displacement
Syntax:
Operands:
Program Counter:
ST Y, Rr
ST Y+, Rr
ST -Y, Rr
STD Y+q, Rr
0 r 31
0 r 31
0 r 31
0 r 31, 0 q 63
PC PC + 1
PC PC + 1
PC PC + 1
PC PC + 1
16-bit Opcode:
(i)
1000
001r
rrrr
1000
(ii)
1001
001r
rrrr
1001
(iii)
1001
001r
rrrr
1010
(iiii)
10q0
qq1r
rrrr
1qqq
139
0856EAVR11/05
Example:
clr
r29
ldi
r28,$60
st
Y+,r0
st
Y,r1
ldi
r28,$63
st
Y,r2
st
-Y,r3
std
Y+2,r4
Words: 1 (2 bytes)
Cycles: 2
140
Comment:
(i)
(ii)
(iii)
(iiii)
(Z) Rr
(Z) Rr
ZZ-1
(Z+q) Rr
Z Z+1
(Z) Rr
Z: Unchanged
Z: Post incremented
Z: Pre decremented
Z: Unchanged, q: Displacement
Syntax:
Operands:
Program Counter:
(i)
(ii)
(iii)
(iiii)
ST Z, Rr
ST Z+, Rr
ST -Z, Rr
STD Z+q, Rr
0 r 31
0 r 31
0 r 31
0 r 31, 0 q 63
PC PC + 1
PC PC + 1
PC PC + 1
PC PC + 1
141
0856EAVR11/05
16-bit Opcode :
(i)
1000
001r
rrrr
0000
(ii)
1001
001r
rrrr
0001
(iii)
1001
001r
rrrr
0010
(iiii)
10q0
qq1r
rrrr
0qqq
Example:
clr
r31
ldi
r30,$60
st
Z+,r0
st
Z,r1
ldi
r30,$63
st
Z,r2
st
-Z,r3
std
Z+2,r4
Words: 1 (2 bytes)
Cycles: 2
142
(k) Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
STS k,Rr
0 r 31, 0 k 65535
PC PC + 2
32-bit Opcode:
1001
001d
dddd
0000
kkkk
kkkk
kkkk
kkkk
Example:
lds
r2,$FF00
add
r2,r1
; add r1 to r2
sts
$FF00,r2
; Write back
Words: 2 (4 bytes)
Cycles: 2
143
0856EAVR11/05
Rd Rd - Rr
(i)
(i)
Syntax:
Operands:
Program Counter:
SUB Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0001
10rd
dddd
rrrr
H:
S:
V:
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
r13,r12
brne
noteq
; Branch if r12<>r13
...
noteq:
nop
Words: 1 (2 bytes)
Cycles: 1
144
Rd Rd - K
(i)
(i)
Syntax:
Operands:
Program Counter:
SUBI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0101
KKKK
dddd
KKKK
H:
S:
V:
Rd7 K7 R7 +Rd7 K7 R7
Set if twos complement overflow resulted from the operation; cleared otherwise.
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
C:
r22,$11
brne
noteq
; Branch if r22<>$11
...
noteq:
nop
Words: 1 (2 bytes)
Cycles: 1
145
0856EAVR11/05
(i)
(i)
Syntax:
Operands:
Program Counter:
SWAP Rd
0 d 31
PC PC + 1
16-bit Opcode:
1001
010d
dddd
0010
r1
; Increment r1
swap
r1
inc
r1
swap
r1
; Swap back
Words: 1 (2 bytes)
Cycles: 1
146
Rd Rd Rd
(i)
(i)
Syntax:
Operands:
Program Counter:
TST Rd
0 d 31
PC PC + 1
00dd
dddd
dddd
S:
V:
0
Cleared
N:
R7
Set if MSB of the result is set; cleared otherwise.
Z:
R7 R6 R5 R4 R3 R2 R1 R0
Set if the result is $00; cleared otherwise.
r0
breq zero
; Test r0
; Branch if r0=0
...
zero:
nop
Words: 1 (2 bytes)
Cycles: 1
147
0856EAVR11/05
(i)
WD timer restart.
(i)
Syntax:
Operands:
Program Counter:
WDR
None
PC PC + 1
16-bit Opcode:
1001
0101
1010
1000
Example:
wdr
Words: 1 (2 bytes)
Cycles: 1
148
149
0856EAVR11/05
Atmel Corporation
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