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74ls74 PDF
74ls74 PDF
DATA SHEET
74AHC74; 74AHCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 1999 Aug 05
File under Integrated Circuits, IC06
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
PARAMETER
CONDITIONS
tPHL/tPLH
propagation delay
CL = 15 pF;
VCC = 5 V
nCP to nQ, nQ
UNIT
AHC AHCT
3.7
3.3
ns
3.7
3.7
ns
130
100
MHz
fmax
CI
input capacitance
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
16
pF
12
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (SD) and
reset (RD) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
See note 1
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQ
nQ
Table 2
See note 1
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQn+1
nQn+1
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
ORDERING INFORMATION
PACKAGE
OUTSIDE
NORTH
AMERICA
NORTH AMERICA
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
40 to +85 C
14
SO
plastic
SOT108-1
74AHC74D
74AHC74D
74AHC74PW
74AHC74PW DH
14
TSSOP
plastic
SOT402-1
74AHCT74D
74AHCT74D
14
SO
plastic
SOT108-1
74AHCT74PW
74AHCT74PW DH
14
TSSOP
plastic
SOT402-1
PINNING
PIN
SYMBOL
DESCRIPTION
1 and 13
2 and 12
1D and 2D
data inputs
3 and 11
4 and 10
5 and 9
1Q and 2Q
6 and 8
1Q and 2Q
GND
ground (0 V)
14
VCC
DC supply voltage
handbook, halfpage
1RD
1D
13 2RD
1CP
12 2D
1SD
1Q
10 2SD
1Q
GND
8 2Q
74
4 10
handbook, halfpage
14 VCC
1SD 2SD
2
12
3
11
11 2CP
2Q
SD
1Q
1D
Q
D
2D
2Q
1CP
CP
2CP
FF
1Q
Q
2Q
RD
6
8
1RD 2RD
1 13
MNA417
1999 Sep 23
5
9
MNA418
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
handbook, halfpage
2
handbook, halfpage
4
3
2
1
11
12
13
1D
1CP
SD
Q
FF
Q
1D
1Q
RD
R
10
1Q
CP
C1
1
10
1SD
1RD
2SD
C1
1D
12
11
2D
2CP
SD
Q
CP
FF
MNA419
2Q
2Q
RD
13
2RD
MNA420
Q
C
C
C
Q
C
RD
SD
CP
MNA421
C
C
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
PARAMETER
74AHCT
CONDITIONS
UNIT
MIN.
TYP. MAX.
4.5
5.0
5.5
VCC
DC supply voltage
2.0
5.0
5.5
VI
input voltage
5.5
5.5
VO
output voltage
VCC
VCC
Tamb
40
+25
+85
40
+25
+85
40
+25
+125 40
+25
+125 C
see DC and AC
characteristics per
device
100
VCC = 5 V 0.5 V
20
20
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
VCC
DC supply voltage
0.5
+7.0
VI
input voltage
0.5
+7.0
IIK
20
mA
IOK
20
mA
IO
25
mA
ICC
75
mA
Tstg
storage temperature
PD
65
+150 C
500
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 23
mW
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
Tamb (C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
VIL
VOH
VOL
40 to +85
25
PARAMETER
HIGH-level input
voltage
LOW-level input
voltage
VCC (V)
40 to +125 UNIT
MIN.
TYP.
2.0
1.5
1.5
1.5
3.0
2.1
2.1
2.1
5.5
3.85
3.85
3.85
2.0
0.5
0.5
0.5
3.0
0.9
0.9
0.9
5.5
1.65
1.65
1.65
2.0
1.9
2.0
1.9
1.9
3.0
2.9
3.0
2.9
2.9
4.5
4.4
4.5
4.4
4.4
HIGH-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
HIGH-level output
voltage
VI = VIH or VIL;
IO = 4.0 mA
3.0
2.58
2.48
2.40
VI = VIH or VIL;
IO = 8.0 mA
4.5
3.94
3.8
3.70
LOW-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
2.0
0.1
0.1
0.1
3.0
0.1
0.1
0.1
4.5
0.1
0.1
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 4 mA
3.0
0.36
0.44
0.55
VI = VIH or VIL;
IO = 8 mA
4.5
0.36
0.44
0.55
1.0
2.0
2.5
10.0 A
II
input leakage
current
VI = VCC or GND
5.5
0.1
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
0.25
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
2.0
20
40
CI
input capacitance
10
10
10
pF
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
74AHCT family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
Tamb (C)
PARAMETER
40 to +85
25
OTHER
VCC (V)
40 to +125 UNIT
VIH
HIGH-level input
voltage
2.0
2.0
VIL
LOW-level input
voltage
4.5 to 5.5
0.8
0.8
0.8
VOH
HIGH-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
4.5
4.4
4.5
4.4
4.4
HIGH-level output
voltage
VI = VIH or VIL;
IO = 8.0 mA
4.5
3.94
3.8
3.70
LOW-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
4.5
0.1
0.1
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 8 mA
4.5
0.36
0.44
0.55
II
input leakage
current
VI = VIH or VIL
5.5
0.1
1.0
2.0
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
0.25
2.5
10.0 A
ICC
quiescent supply
current
2.0
20
40
ICC
additional
quiescent supply
current per input
pin
VI = VCC 2.1 V
other inputs at
VCC or GND;
IO = 0
4.5 to 5.5
1.35
1.5
1.5
mA
CI
input capacitance
10
10
10
pF
VOL
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
AC CHARACTERISTICS
Type 74AHC74
GND = 0 V; tr = tf 3.0 ns.
Tamb (C)
TEST CONDITIONS
SYMBOL
40 to +85
25
PARAMETER
WAVEFORMS
CL
MIN.
TYP.
40 to +125
UNIT
15 pF
5.2
11.9
1.0
14.0
1.0
15.0
ns
5.4
12.3
1.0
14.5
1.0
15.5
ns
fmax
maximum clock
pulse frequency
80
125
45
45
ns
tPHL/tPLH
propagation delay
nCP to nQ, nQ
tPHL/tPLH
tW
propagation delay
nCP to nQ, nQ
50 pF
7.4
15.4
1.0
17.5
1.0
19.5
ns
7.7
15.8
1.0
18.0
1.0
20.0
ns
6.0
7.0
7.0
ns
6.0
7.0
7.0
ns
5.0
5.0
5.0
ns
6.0
7.0
7.0
ns
trem
tsu
set-up time
nD to nCP
th
hold time
nD to nCP
0.5
0.5
0.5
ns
fmax
maximum clock
pulse frequency
50
75
70
70
ns
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
TEST CONDITIONS
SYMBOL
Tamb (C)
PARAMETER
40 to +85
25
WAVEFORMS
CL
MIN.
TYP.
40 to +125
UNIT
15 pF
3.7
7.3
1.0
8.5
1.0
9.5
ns
3.7
7.7
1.0
9.0
1.0
10.0
ns
fmax
maximum clock
pulse frequency
130
170
110
110
ns
tPHL/tPLH
propagation delay
nCP to nQ, nQ
50 pF
5.2
9.3
1.0
10.5
1.0
12.0
ns
propagation delay
nSD to nQ, nQ
5.3
9.7
1.0
11.0
1.0
12.5
ns
5.0
5.0
5.0
ns
5.0
5.0
5.0
ns
3.0
3.0
3.0
ns
5.0
5.0
5.0
ns
tPHL/tPLH
tW
propagation delay
nCP to nQ, nQ
trem
tsu
set-up time
nD to nCP
th
hold time
nD to nCP
0.5
0.5
0.5
ns
fmax
maximum clock
pulse frequency
90
115
75
75
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 23
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
Type 74AHCT74
GND = 0 V; tr = tf 3.0 ns.
TEST CONDITIONS
SYMBOL
Tamb (C)
PARAMETER
40 to +85
25
WAVEFORMS
CL
MIN.
TYP.
40 to +125
UNIT
15 pF
3.3
7.8
1.0
9.0
1.0
10.0
ns
3.7
10.4
1.0
12.0
1.0
13.0
ns
fmax
maximum clock
pulse frequency
100
160
80
80
ns
tPHL/tPLH
propagation delay
nCP to nQ, nQ
tPHL/tPLH
propagation delay
nCP to nQ, nQ
50 pF
4.8
8.8
1.0
10.0
1.0
11.0
ns
5.3
11.4
1.0
13.0
1.0
14.5
ns
tW
5.0
5.0
5.0
ns
tW(st)(rst)
5.0
5.0
5.0
ns
trem
3.5
3.5
3.5
ns
tsu
set-up time
nD to nCP
5.0
5.0
5.0
ns
th
hold time
nD to nCP
ns
fmax
maximum clock
pulse frequency
80
140
65
65
ns
Note
1. Typical values at VCC = 5.0 V.
1999 Sep 23
10
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
AC WAVEFORMS
VI
VM(1)
nD INPUT
GND
th
th
t su
t su
1/fmax
VI
VM(1)
nCP INPUT
GND
tW
t PHL
t PLH
VOH
VM(1)
nQ OUTPUT
VOL
VOH
VM(1)
nQ OUTPUT
VOL
t PLH
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
t PHL
MNA422
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.6
The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the
nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
1999 Sep 23
11
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
VI
VM(1)
nCP INPUT
GND
t rem
VI
VM(1)
nSD INPUT
GND
tW
tW
VI
VM(1)
nRD INPUT
GND
t PHL
t PLH
VOH
VM(1)
nQ OUTPUT
VOL
VOH
VM(1)
nQ OUTPUT
VOL
MNA423
t PHL
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
Fig.7
t PLH
The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRD to nCP removal time.
1999 Sep 23
12
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
S1
VCC
PULSE
GENERATOR
VI
1000
VO
D.U.T.
CL
RT
MNA183
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Fig.8 Load circuitry for switching times.
1999 Sep 23
13
VCC
open
GND
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
1
7
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06S
MS-012AB
1999 Sep 23
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
14
8
0o
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
c
y
HE
v M A
14
Q
(A 3)
A2
A1
pin 1 index
Lp
L
7
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (2)
HE
Lp
Z (1)
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
1999 Sep 23
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
15
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
If wave soldering is used the following conditions must be
observed for optimal results:
Reflow soldering
Wave soldering
Manual soldering
1999 Sep 23
16
Philips Semiconductors
Product specification
74AHC74; 74AHCT74
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
suitable
suitable(2)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 23
17
Philips Semiconductors
Product specification
1999 Sep 23
18
74AHC74; 74AHCT74
Philips Semiconductors
Product specification
1999 Sep 23
19
74AHC74; 74AHCT74
Internet: http://www.semiconductors.philips.com
SCA 68
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
545002/02/pp20
Sep 23