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ENC28J60 Data Sheet
ENC28J60 Data Sheet
Data Sheet
Stand-Alone Ethernet Controller
with SPI Interface
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ENC28J60
NC*
• Hardware Managed Circular Receive FIFO SO 6 23 OSC1
SI 7 22 VSSOSC
• Byte-Wide Random and Sequential Access with
SCK 8 21 VSSPLL
Auto-Increment CS 9 20 VDDPLL
• Internal DMA for Fast Data Movement RESET 10 19 VDDRX
• Hardware Assisted Checksum Calculation for VSSRX 11 18 VSSTX
TPIN- 12 17 TPOUT+
Various Network Protocols 16
TPIN+ 13 TPOUT-
RBIAS 14 15 VDDTX
Medium Access Controller (MAC)
Features
CLKOUT
28-pin QFN
• Supports Unicast, Multicast and Broadcast
LEDA
LEDB
VCAP
VDD
VSS
INT
Packets
• Programmable Receive Packet Filtering and Wake-up
Host on Logical AND or OR of the Following:
- Unicast destination address 28 27 26 25 24 23 22
- Multicast address NC* 1 21 VDDOSC
- Broadcast address SO 2 20 OSC2
SI 3 19 OSC1
- Magic Packet™ 4 ENC28J60 18 VSSOSC
SCK
- Group destination addresses as defined by CS 5 17 VSSPLL
64-bit Hash Table RESET 6 16 VDDPLL
VSSRX 7 15 VDDRX
- Programmable Pattern Matching of up to
8 9 10 11 12 13 14
64 bytes at user-defined offset
TPOUT-
TPIN+
TPOUT+
VDDTX
VSSTX
• Loopback mode
• Two Programmable LED Outputs for LINK, TX,
RX, Collision and Full/Half-Duplex Status * Reserved pin; always leave disconnected.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
LEDA
Buffer
RX LEDB
8 Kbytes
Dual Port RAM MAC
RXBM
TPOUT+
RXF (Filter)
MII TX TPOUT-
ch0 Interface
CLKOUT DMA &
Control
Arbiter ch0 Checksum
Registers PHY
TPIN+
ch1 TX
ch1
RX TPIN-
TXBM
CS(1)
SI(1) OSC1
SPI 25 MHz
SO Power-on Voltage OSC2
System Control Oscillator
Reset Regulator
SCK(1)
VCAP
RESET(1)
Note 1: These pins are 5V tolerant.
INT LEDA
INTX
LEDB
RS(1)
C2 OSC2
ENC28J60
3.3V Clock from
OSC1
External System
Open(2) OSC2
ECOCON
Changed 80 ns to 320 ns Delay
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
8
2.32 kΩ, 1% 75Ω(3) 75Ω(3) 75Ω(3) 75Ω(3)
10 μF
1 nF, 2 kV(3)
OSC1 CLKOUT
LEDB
INT0 INT
Half-Duplex Operation:
PDPXMD = 0
MCU ENC28J60
I/O CS
SCK SCK
SO SI
The LEDs can also be configured separately to control
their operating polarity (on or off when active), blink rate
SI SO and blink stretch interval. The options are controlled by
the LACFG3:LACFG0 and LBCFG3:LBCFG0 bits.
OSC1 CLKOUT
Typical values for blink stretch are listed in Table 2-1.
INT0 INT
TABLE 2-1: LED BLINK STRETCH
LENGTH
Stretch Length Typical Stretch (ms)
TNSTRCH (normal) 40
TMSTRCH (medium) 70
TLSTRCH (long) 140
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
00h 0000h
Buffer Pointers in Bank 0
= 00
Bank 0 19h
1Ah Common
1Fh Registers
00h
= 01
Bank 1
19h
1Ah Common
1Fh Registers
00h
= 10
Bank 2
19h
1Ah Common
1FFFh
1Fh Registers
00h
= 11
Bank 3 PHY Registers
19h
1Ah Common 00h
Registers
1Fh 1Fh
Note: Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail.
EIE INTIE PKTIE DMAIE LINKIE TXIE r TXERIE RXERIE 0000 0000 65
EIR — PKTIF DMAIF LINKIF TXIF r TXERIF RXERIF -000 0000 66
ESTAT INT BUFER r LATECOL — RXBUSY TXABRT CLKRDY(1) 0000 -000 64
ECON2 AUTOINC PKTDEC PWRSV r VRPS — — — 1000 0--- 16
ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 0000 0000 15
ERDPTL Read Pointer Low Byte ERDPT<7:0>) 1111 1010 17
ERDPTH — — — Read Pointer High Byte (ERDPT<12:8>) ---0 0101 17
EWRPTL Write Pointer Low Byte (EWRPT<7:0>) 0000 0000 17
EWRPTH — — — Write Pointer High Byte (EWRPT<12:8>) ---0 0000 17
ETXSTL TX Start Low Byte (ETXST<7:0>) 0000 0000 17
ETXSTH — — — TX Start High Byte (ETXST<12:8>) ---0 0000 17
ETXNDL TX End Low Byte (ETXND<7:0>) 0000 0000 17
ETXNDH — — — TX End High Byte (ETXND<12:8>) ---0 0000 17
ERXSTL RX Start Low Byte (ERXST<7:0>) 1111 1010 17
ERXSTH — — — RX Start High Byte (ERXST<12:8>) ---0 0101 17
ERXNDL RX End Low Byte (ERXND<7:0>) 1111 1111 17
ERXNDH — — — RX End High Byte (ERXND<12:8>) ---1 1111 17
ERXRDPTL RX RD Pointer Low Byte (ERXRDPT<7:0>) 1111 1010 17
ERXRDPTH — — — RX RD Pointer High Byte (ERXRDPT<12:8>) ---0 0101 17
ERXWRPTL RX WR Pointer Low Byte (ERXWRPT<7:0>) 0000 0000 17
ERXWRPTH — — — RX WR Pointer High Byte (ERXWRPT<12:8>) ---0 0000 17
EDMASTL DMA Start Low Byte (EDMAST<7:0>) 0000 0000 71
EDMASTH — — — DMA Start High Byte (EDMAST<12:8>) ---0 0000 71
EDMANDL DMA End Low Byte (EDMAND<7:0>) 0000 0000 71
EDMANDH — — — DMA End High Byte (EDMAND<12:8>) ---0 0000 71
EDMADSTL DMA Destination Low Byte (EDMADST<7:0>) 0000 0000 71
EDMADSTH — — — DMA Destination High Byte (EDMADST<12:8>) ---0 0000 71
EDMACSL DMA Checksum Low Byte (EDMACS<7:0>) 0000 0000 72
EDMACSH DMA Checksum High Byte (EDMACS<15:8>) 0000 0000 72
EHT0 Hash Table Byte 0 (EHT<7:0>) 0000 0000 52
EHT1 Hash Table Byte 1 (EHT<15:8>) 0000 0000 52
EHT2 Hash Table Byte 2 (EHT<23:16>) 0000 0000 52
EHT3 Hash Table Byte 3 (EHT<31:24>) 0000 0000 52
EHT4 Hash Table Byte 4 (EHT<39:32>) 0000 0000 52
EHT5 Hash Table Byte 5 (EHT<47:40>) 0000 0000 52
EHT6 Hash Table Byte 6 (EHT<55:48>) 0000 0000 52
EHT7 Hash Table Byte 7 (EHT<63:56>) 0000 0000 52
EPMM0 Pattern Match Mask Byte 0 (EPMM<7:0>) 0000 0000 51
EPMM1 Pattern Match Mask Byte 1 (EPMM<15:8>) 0000 0000 51
EPMM2 Pattern Match Mask Byte 2 (EPMM<23:16>) 0000 0000 51
EPMM3 Pattern Match Mask Byte 3 (EPMM<31:24>) 0000 0000 51
EPMM4 Pattern Match Mask Byte 4 (EPMM<39:32>) 0000 0000 51
EPMM5 Pattern Match Mask Byte 5 (EPMM<47:40>) 0000 0000 51
EPMM6 Pattern Match Mask Byte 6 (EPMM<55:48>) 0000 0000 51
EPMM7 Pattern Match Mask Byte 7 (EPMM<63:56>) 0000 0000 51
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify.
Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
2: EREVID is a read-only register.
3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Receive
Buffer
(Circular FIFO)
Buffer Read Pointer
Receive Buffer Data
(ERDPTH:ERDPTL) 55h
(RBM 55h)
The PHY registers provide configuration and control of 1. Write the address of the PHY register to write to
the PHY module, as well as status information about its into the MIREGADR register.
operation. All PHY registers are 16 bits in width. There 2. Write the lower 8 bits of data to write into the
are a total of 32 PHY addresses; however, only 9 loca- MIWRL register.
tions are implemented. Writes to unimplemented 3. Write the upper 8 bits of data to write into the
locations are ignored and any attempts to read these MIWRH register. Writing to this register auto-
locations will return ‘0’. All reserved locations should be matically begins the MIIM transaction, so it must
written as ‘0’; their contents should be ignored when be written to after MIWRL. The MISTAT.BUSY
read. bit becomes set.
Unlike the ETH, MAC and MII control registers, or the The PHY register will be written after the MIIM opera-
buffer memory, the PHY registers are not directly tion completes, which takes 10.24 μs. When the write
accessible through the SPI control interface. Instead, operation has completed, the BUSY bit will clear itself.
access is accomplished through a special set of MAC The host controller should not start any MIISCAN or
control registers that implement Media Independent MIIRD operations while busy.
Interface Management (MIIM). These control registers
are referred to as the MII registers. The registers that 3.3.3 SCANNING A PHY REGISTER
control access to the PHY registers are shown in The MAC can be configured to perform automatic
Register 3-3 and Register 3-4. back-to-back read operations on a PHY register. This
can significantly reduce the host controller complexity
3.3.1 READING PHY REGISTERS when periodic status information updates are desired.
When a PHY register is read, the entire 16 bits are To perform the scan operation:
obtained. 1. Write the address of the PHY register to read
To read from a PHY register: from into the MIREGADR register.
1. Write the address of the PHY register to read 2. Set the MICMD.MIISCAN bit. The scan opera-
from into the MIREGADR register. tion begins and the MISTAT.BUSY bit is set. The
2. Set the MICMD.MIIRD bit. The read operation first read operation will complete after 10.24 μs.
begins and the MISTAT.BUSY bit is set. Subsequent reads will be done at the same
interval until the operation is cancelled. The
3. Wait 10.24 μs. Poll the MISTAT.BUSY bit to be
MISTAT.NVALID bit may be polled to determine
certain that the operation is complete. While
when the first read operation is complete.
busy, the host controller should not start any
MIISCAN operations or write to the MIWRH After setting the MIISCAN bit, the MIRDL and MIRDH
register. registers will automatically be updated every 10.24 μs.
When the MAC has obtained the register There is no status information which can be used to
contents, the BUSY bit will clear itself. determine when the MIRD registers are updated. Since
4. Clear the MICMD.MIIRD bit. the host controller can only read one MII register at a
time through the SPI, it must not be assumed that the
5. Read the desired data from the MIRDL and
values of MIRDL and MIRDH were read from the PHY
MIRDH registers. The order that these bytes are
at exactly the same time.
accessed is unimportant.
When the MIISCAN operation is in progress, the host
3.3.2 WRITING PHY REGISTERS controller must not attempt to write to MIWRH or start
an MIIRD operation. The MIISCAN operation can be
When a PHY register is written to, the entire 16 bits is
cancelled by clearing the MICMD.MIISCAN bit and
written at once; selective bit writes are not imple-
then polling the MISTAT.BUSY bit. New operations may
mented. If it is necessary to reprogram only select bits
be started after the BUSY bit is cleared.
in the register, the controller must first read the PHY
register, modify the resulting data and then write the
data back to the PHY register.
00h PHCON1 PRST PLOOPBK — — PPWRSV r — PDPXMD(1) r — — — — — — — 00-- 00-q 0--- ----
01h PHSTAT1 — — — PFDPX PHDPX — — — — — — — — LLSTAT JBSTAT — ---1 1--- ---- -00-
02h PHID1 PHY Identifier (OUI3:OUI18) = 0083h 0000 0000 1000 0011
DS39662C-page 20
03h PHID2 PHY Identifier (OUI19:OUI24) = 000101 PHY P/N (PPN5:PPN0) = 00h PHY Revision (PREV3:PREV0) = 00h 0001 0100 0000 0000
10h PHCON2 — FRCLNK TXDIS r r JABBER r HDLDIS r r r r r r r r -000 0000 0000 0000
11h PHSTAT2 — — TXSTAT RXSTAT COLSTAT LSTAT DPXSTAT(1) — — — PLRITY — — — — — --00 00q- --0- ----
ENC28J60
Preliminary
© 2008 Microchip Technology Inc.
ENC28J60
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Reset values of the Duplex mode/status bit depends on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).
CS
SCK
SI
MSb In LSb In
SO High-Impedance State
CS
SCK
Don’t Care
SI
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Opcode Address
SI 0 0 0 4 3 2 1 0
Data Out
High-Impedance State
SO 7 6 5 4 3 2 1 0
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Opcode Address
SI 0 0 0 4 3 2 1 0
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Opcode Address Data Byte
SI 0 1 0 A4 3 2 1 0 D7 6 5 4 3 2 1 D0
High-Impedance State
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI 0 1 1 1 1 0 1 0 7 6 5 4 3 2 1 D0 7 6 5 4 3 2 1 0
High-Impedance State
SO
CS
0 1 2 3 4 5 6 7
SCK
SI 1 1 1 1 1 1 1 1
High-Impedance State
SO
Start-Of-Frame Delimiter
1 SFD (filtered out by the module)
Destination Address,
6 DA such as Multicast, Broadcast or Unicast
6 SA Source Address
Used in the
Calculation
of the FCS
Data
Packet Payload
46-1500 (with optional padding)
Padding
Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Destination Address,
Data Packet Source Address,
Type/Length and Data
To achieve the example layout shown in Figure 7-2 and DMA and transmission engine share the same memory
to transmit a packet, the host controller should: access port. Similarly, if the DMAST bit in ECON1 is set
1. Appropriately program the ETXST Pointer to after TXRTS is already set, the DMA will wait until the
point to an unused location in memory. It will TXRTS bit becomes clear before doing anything. While
point to the per packet control byte. In the the transmission is in progress, none of the unshaded
example, it would be programmed to 0120h. It is bits (except for the EECON1 register’s bits) in Table 7-2
recommended that an even address be used for should be changed. Additionally, none of the bytes to be
ETXST. transmitted should be read or written to through the SPI.
If the host controller wishes to cancel the transmission,
2. Use the WBM SPI command to write the per
it can clear the TXRTS bit.
packet control byte, the destination address, the
source MAC address, the type/length and the When the packet is finished transmitting or is aborted
data payload. due to an error/cancellation, the ECON1.TXRTS bit will
3. Appropriately program the ETXND Pointer. It be cleared, a seven-byte transmit status vector will be
should point to the last byte in the data payload. written to the location pointed to by ETXND + 1, the
In the example, it would be programmed to EIR.TXIF will be set and an interrupt will be generated
0156h. (if enabled). The ETXST and ETXND Pointers will not
be modified. To check if the packet was successfully
4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE
transmitted, the ESTAT.TXABRT bit should be read. If
to enable an interrupt when done (if desired).
it was set, the host controller may interrogate the
5. Start the transmission process by setting ESTAT.LATECOL bit in addition to the various fields in
ECON1.TXRTS. the transmit status vector to determine the cause. The
If a DMA operation was in progress while the TXRTS bit transmit status vector is organized as shown in
was set, the ENC28J60 will wait until the DMA opera- Table 7-1. Multi-byte fields are written in little-endian
tion is complete before attempting to transmit the format.
packet. This possible delay is required because the
7.2.3 READING RECEIVED PACKETS In the event that the application needed to do random
access to the packet, it would be necessary to manu-
To process the packet, the host controller will normally
ally calculate the proper ERDPT, taking care to not
use the RBM SPI command and start reading from the
exceed the end of the receive buffer if the packet spans
beginning of the next Packet Pointer. The host controller
the ERXND-to-ERXST buffer boundary. In other words,
will save the next Packet Pointer, any necessary bytes
given the packet start address and a desired offset, the
from the receive status vector and then proceed to read
application should follow the logic shown in
the actual packet contents. If ECON2.AUTOINC is set, it
Example 7-1.
will be able to sequentially read the entire packet without
ever modifying the ERDPT registers. The Read Pointer
would automatically wrap at the end of the circular
receive buffer to the beginning.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
No
Yes
No No
Yes
CRCEN valid? Accept Packet
Yes Pattern Yes
PMEN set?
matches?
No
No No
Reject Packet
Yes Yes
MPEN set? Magic Packet™
for us?
No No
Yes Yes
HTEN set? Hash table
bit set?
No No
No No
No No
Yes Unicast No
UCEN set?
packet?
No Yes
Yes Pattern No
PMEN set? matches?
No Yes
Yes No
MPEN set? Magic Packet™
for us?
No Yes
No Yes
Yes Multicast No
MCEN set?
destination?
No Yes
Yes Broadcast No
BCEN set?
destination?
No Yes
No
CRCEN set?
Yes
No
CRC valid?
Yes
Input Configuration:
EMPOH:EPMOL = 0006h
EPMM7:EPMM0 = 0000000000001F0Ah
EPMCSH:EPMCSL = 563Fh
Received
Data 11 22 33 44 55 66 77 88 99 AA BB CC 00 5A 09 0A 0B 0C 0D . . . 40 . . . FE 45 23 01
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 . . . 70 . . .
Values Used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h}
(00h padding byte added by hardware)
Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format.
Received
Data Field Comments
11 22 33 44 55 66 DA
77 88 99 AA BB CC SA
00 FE Type/Length
09 0A 0B 0C 0D 0E
FF FF FF FF FF 00
FF FF FF FF FF FF Sync Pattern
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
Data
11 22 33 44 55 66 Sixteen Repeats of
11 22 33 44 55 66 the Station Address
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
11 22 33 44 55 66
19 1A 1B 1C 1D 1E
EF 54 32 10 FCS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Hardware Reset
System Reset
POR
Reset Transmit
Transmit Reset
Reset Receive
Receive Reset
The ENC28J60 can also be reset via the SPI using the
System Reset Command. See Section 4.0 “Serial
Peripheral Interface (SPI)”.
The RESET pin will not be driven low by any internal
Resets, including a System Reset command via the
SPI interface.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).
PKTIF
PKTIE
DMAIF
PLNKIF PGIF DMAIE
LINKIF
PLNKIE
PGEIE INT
LINKIE
INT
TXIF
TXIE
INTIE
TXERIF
TXERIE
RXERIF
RXERIE
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit SC = Self-clearing bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
1. Program the EDMAST register pair to 0000h. Because of the LFSR implementation, an initial seed of
zero will generate a continuous pattern of zeros. As a
2. Program EDMAND and ERXND register pairs to
result, a non-zero seed value will likely perform a more
1FFFh.
extensive memory test. Selecting the same seed for
3. Configure the DMA for checksum generation by two separate trials will allow a repeat of the same test.
setting CSUMEN in ECON1.
4. Write the seed/initial shift value byte to the 15.3 Address Fill Mode
EBSTSD register (this is not necessary if
Address Fill mode is used). In Address Fill mode, the BIST controller will write the
5. Enable Test mode, select the desired test, select low byte of each memory address into the associated
the desired port configuration for the test. buffer location. As an example, after the BIST is oper-
ated, the location 0000h should have 00h in it, location
6. Start the BIST by setting EBSTCON.BISTST.
0001h should have 01h in it, location 0E2Ah should
7. Start the DMA checksum by setting DMAST in have 2Ah in it and so on. With this fixed memory
ECON1. The DMA controller will read the pattern, the BIST and DMA modules should always
memory at the same rate the BIST controller will generate a checksum of F807h. The host controller
write to it, so the DMA can be started any time may use Address Fill mode to confirm that the BIST
after the BIST is started. and DMA modules themselves are both operating as
8. Wait for the DMA to complete by polling the intended.
DMAST bit or receiving the DMA interrupt (if
enabled). 15.4 Pattern Shift Fill Mode
9. Compare the EDMACS registers with the
EBSTCS registers. In Pattern Shift Fill mode, the BIST controller writes the
value of EBSTSD into memory location 0000h. Before
To ensure full testing, the test should be redone with
writing to location 0001h, it shifts the contents of
the Port Select bit, PSEL, altered. When not using
EBSTSD to the left by the value specified by the
Address Fill mode, additional tests may be done with
PSV2:PSV0 bits in EBSTCON. Bits that leave the most
different seed values to gain greater confidence that
significant end of EBSTSD are wrapped around to the
the memory is working as expected.
least significant side. This shift is repeated for each
new address. As a result of shifting the data, a checker-
board pattern can be written into the buffer memory to
confirm that adjacent memory elements do not affect
each other when accessed.
Note 1: VCAP is not designed to supply an external load. No external voltage should be applied to this pin.
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
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Revision A
Original data sheet for the ENC28J60.
From: Name
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Application (optional):
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Questions:
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E P
Electrical Characteristics..................................................... 79 Packaging Information ........................................................ 83
Absolute Maximum Ratings ........................................ 79 Details......................................................................... 84
AC Characteristics ...................................................... 81 Marking....................................................................... 83
CLKOUT Pin AC ......................................................... 81 Packet Format .................................................................... 31
DC Characteristics ...................................................... 80 CRC Field ................................................................... 32
Oscillator Timing ......................................................... 81 Data Field ................................................................... 32
Requirements for External Magnetics......................... 81 Destination Address ................................................... 32
Reset AC..................................................................... 81 Padding Field.............................................................. 32
SPI Interface AC ......................................................... 82 Preamble/Start-Of-Frame Delimiter............................ 31
EREVID Register ................................................................ 22 Source Address .......................................................... 32
Errata .................................................................................... 2 Type/Length Field....................................................... 32
Ethernet Buffer .................................................................... 17 Per Packet Control Byte Format ......................................... 39
Ethernet Module PHID Registers ................................................................... 22
Transmitting and Receiving Data PHSTAT Registers ............................................................. 22
Receive Packet Layout ....................................... 43 PHY Register Summary...................................................... 20
Transmit Packet Layout ...................................... 40
Ethernet Overview .............................................................. 31
01/02/08