FPGA vs.

ASIC Design
Flow

FPGA and ASIC Technology

Comparison - 1

2009 Xilinx, Inc. All Rights Reserved

Intro to VHDL or
3
Intro to VHDL or
Intro to Verilog
days
Intro to Verilog

FPGA and
ASIC
Technology
Comparison
FPGA vs.
ASIC
Design
ASIC
to FPGA
Flow
Coding
Conversion

Curriculum
Path

Virtex-5 Coding
Techniques
Spartan-3 Coding
Techniques

for

1
Fundamentals of
Fundamentals of
day
FPGA Design
FPGA Design
Designing for
Designing for
Performance
Performance

2
da
ys

ASIC Design

Advanced FPGA
2
Advanced FPGA
Implementation
days
Implementation

Welcome
If you are an experienced ASIC designer
transitioning to FPGAs, this course will help
you reduce your learning curve by
leveraging your ASIC experience
Careful attention to how FPGAs are different
than ASICs will help you create a fast and
reliable FPGA design

After completing this

module, you will able
to:
Describe key differences between ASIC and
FPGA design flows, including
Design methodology
Verification techniques
Test-generation logic
Tools

Design Flow
ASIC and FPGA design and implementation
methodologies differ moderately
Xilinx FPGAs provide for reduced design time and later
bug fixes

No design for test logic is required

Deep sub-micron verification is done
No waiting for prototypes

Coding style
For high-performance designs, FPGAs may require
some pipelining
When retargeting code from an ASIC to an FPGA, the
code usually requires optimization (instantiation)
FPGA and ASIC Technology
Comparison - 5

2009
2007 Xilinx, Inc. All Rights Reserved

ASIC Design Flow

ASIC tools are generally driven by
scripts
Post-synthesis static timing
analysis and equivalency checking
are musts for sign off to foundry
Verification of deep sub-micron
effects (second- and third-order
effects) is required for ASICs
Internal, deep sub-micron effects
are already verified for Xilinx
FPGAs

FPGA and ASIC Technology

Comparison - 6

2009
2007 Xilinx, Inc. All Rights Reserved

FPGA Design Flow

FPGA tools are generally
GUI-driven, pushbutton flows
FPGA tools also have scripting
capabilities

After the design passes behavioral

simulation and static timing analysis,
verification is completed most efficiently
by verifying in circuit
Fast turnaround times
Static timing analysis is used to verify
timing of the design
Timing simulation is supported
This is a simplified/typical design flow
FPGA and ASIC Technology
Comparison - 7

2009
2007 Xilinx, Inc. All Rights Reserved

ASIC Implementation
Create HDL
Optimized for ASIC technology and
area

Synthesis
Primarily driven by scripts
Synopsys design compile
Design for test logic insertion
(BIST, Scan, and JTAG)

Place & route

Foundry tools, Cadence, AVANT

FPGA and ASIC Technology

Comparison - 8

2009
2007 Xilinx, Inc. All Rights Reserved

FPGA Implementation
Create HDL
Optimized for Xilinx FPGAs and
performance

Synthesis
Synopsys, Mentor, XST
Pushbutton flow with
scripting capabilities

Place & route

Completed by the user
Xilinx implementation tools ISE software
Pushbutton flow, scripting capabilities

FPGA and ASIC Technology

Comparison - 9

2009
2007 Xilinx, Inc. All Rights Reserved

ASIC Verification
Key ASIC verification points
Behavioral simulation*
Post-synthesis static timing analysis
Post-synthesis equivalency checking
Post-place & route static timing analysis*
Post-place & route equivalency checking
Post-place & route timing simulation*
Verification of second- and third-order
effects
Verify in circuit*

* Applies to both FPGA and ASIC design

flows
FPGA and ASIC Technology
Comparison - 10

2009
2007 Xilinx, Inc. All Rights Reserved

FPGA Verification
Three key verification points for FPGA
implementation
Behavioral simulation
Post-place & route static timing analysis
Download and verify in circuit

Post-synthesis gate-level simulation

and post-place & route timing simulations
can be done for production sign off
Post-place & route timing
simulations are also often done
to verify board- and system-level timing

FPGA and ASIC Technology

Comparison - 11

2009
2007 Xilinx, Inc. All Rights Reserved

Deep Sub-Micron Effects

Second- and third-order effects
Silicon-induced design flaws due to the small
wire delays and narrow silicon of deep submicron processes
They include cross talk, interconnect delays,
and Simultaneously Switching Outputs (SSO)

Xilinx FPGAs inherently have fewer deep submicron silicon issues

Pre-engineered standard product alleviates
complex deep sub-micron design issues
Recovers design innovation time and
facilitates time-to-market
FPGA and ASIC Technology
Comparison - 12

2009
2007 Xilinx, Inc. All Rights Reserved

Design for Test Logic

ASIC test-generation logic is not required
in a Xilinx FPGA
Because of the capability to test in-circuit,
automatic test pattern generation logic is
normally not included

This reduces the time spent on creating and

inserting test logic, and allows more time to be
spent on the bench testing the design

Xilinx FPGAs already contain JTAG (boundary scan) logic

Xilinx FPGAs have readback capability that is similar to scan logic
Readback can verify the configuration as well as the internal status of
registers and memory

FPGA and ASIC Technology

Comparison - 13

2009
2007 Xilinx, Inc. All Rights Reserved

In-Circuit Verification
Tools
ChipScope Pro software
Integrated Logic Analysis (ILA)
provides in-circuit logic
verification through the
dedicated JTAG pins
No need for extra headers
The ChipScope Pro software is
a standalone tool for logic
analysis
Data channels from 1 to 256;
sample sizes from 256 to 4096

FPGA and ASIC Technology

Comparison - 14

2009
2007 Xilinx, Inc. All Rights Reserved

Firmware Development
ASIC Design Flow
Firmware development begins much earlier
in the design cycle for FPGAs
No waiting time for prototypes
Hardware and software can develop in
tandem

FPGA and ASIC Technology

Comparison - 15

2009
2007 Xilinx, Inc. All Rights Reserved

Design Flow
Comparison

ASIC

FPGA and ASIC Technology

Comparison - 16

FPGA

2009
2007 Xilinx, Inc. All Rights Reserved

Advanced FPGA Tool

Flow
Equivalency checking
Synopsys Formality

Floorplanning and layout

Synopsys Amplify (physical synthesis)
Xilinx Floorplanner or PlanAhead software

Static timing analysis

Synopsys PrimeTime

Calculating power use

Xilinx XPower

Edit routing and placement

Xilinx FPGA Editor
FPGA and ASIC Technology
Comparison - 17

2009
2007 Xilinx, Inc. All Rights Reserved

Equivalency Checking
Equivalency checking (also known as formal verification) determines if
two versions of a design are functionally equivalent
For example, an RTL versus a post-synthesis design
Fast and efficient verification of large designs without the use of test vectors

Far faster than simulating post-synthesis and post-place & route netlists

FPGA and ASIC Technology

Comparison - 19

2009
2007 Xilinx, Inc. All Rights Reserved

Floorplanning and
Layout
The Floorplanner utility and
PlanAhead software are used for
design layout

FPGA and ASIC Technology

Comparison - 20

2009
2007 Xilinx, Inc. All Rights Reserved

ISE Tool Floorplanner

Grey
Placement
window shows
the placement
found by the
implementation
tools

Design Hierarchy
Displays colorcoded hierarchical
blocks

Design Nets
Highlights a selected net
in the design
FPGA and ASIC Technology
Comparison - 21

White Floorplan window

shows the area constraints
you have made
2009
2007 Xilinx, Inc. All Rights Reserved

PlanAhead Software
Challenging designs
Large devices, complex constraints, heavy utilization

Designs experiencing implementation issues

Performance, capacity, run time, and repeatability
Significant run-time reductions realized after
floorplanning

Designs requiring implementation control

Users looking for options other than pushbutton flow
Visualize design issues from many aspects

Block-based designs
Module-level incremental updates
Provides an IP reuse solution
FPGA and ASIC Technology
Comparison - 22

2009
2007 Xilinx, Inc. All Rights Reserved

Virtex-4 FX140 FPGA

24 clock domains
2 processors
1760 I/Os
Many resource types

PinAhead
Pin assignment analysis
Tool includes a DRC
check and WASSO
analysis

Properties,
Selection Views

Package View

Allows you to see both a

Package and Pin view of Clock Regions View
your design
Makes it easy to make
pin assignments and
attributes
FPGA and ASIC Technology
Comparison - 23

I/O Ports View

Package Pins View

2009
2007 Xilinx, Inc. All Rights Reserved

Device View

Xilinx SmartGuide
Technology and Partitions
SmartGuide technology is used to maintain as much of the place &
route as possible, while still enabling place & route changes to improve
timing
Works best when there are small design changes and the original design
met timing
Saves place & route run time

Partitions are used to maintain a place & route solution for unmodified
logic in a partition
Works best if you have large amounts of design changes between each
iteration
Works best if a single partition has a high percentage of changes
Timing-critical paths should not cross any boundaries
Saves place & route run time
FPGA and ASIC Technology
Comparison - 24

2009
2007 Xilinx, Inc. All Rights Reserved

FPGA Editor
The FPGA Editor is a graphical
application that displays
Device resources
Precise layout of the chosen
device

The FPGA Editor is commonly used

to
View device resources
Make minor modifications

Done late in the design cycle

Does not require reimplementation of the design

Changes are NOT backannotated to the source files

Insert probes
Make short-term functional
for in-circuit verification
FPGA andchanges
ASIC Technology
2009
2007 Xilinx, Inc. All Rights Reserved
Comparison - 25

Xilinx XPower
XPower is used to estimate
the power consumption and
junction temperature of
your FPGA
Reads an implemented
design (NCD file) and
timing constraint data
You supply activity rates,
clock frequencies, capacitive
loading on output pins,
power supply data, and
ambient temperature

You can also supply design activity data from simulation (VCD file)

FPGA and ASIC Technology

Comparison - 26

2009
2007 Xilinx, Inc. All Rights Reserved

Synopsys PrimeTime
PrimeTime is a full-chip static timing analysis
tool targeting complex multimillion gate designs
Ideal for system-on-a-chip designs

PrimeTime provides ASIC-quality sign off of

multimillion-gate FPGAs

FPGA and ASIC Technology

Comparison - 27

2009
2007 Xilinx, Inc. All Rights Reserved

Summary
FPGAs provide for reduced design time and later bug fixes
No design for test logic is required
Deep sub-micron verification has been completed
No waiting for prototypes

Firmware development starts sooner in the design cycle for the FPGA design
flow
Faster production ramp up

Xilinx provides powerful tools for advanced control over implementation

The Xilinx ChipScope Pro software tool provides powerful in-circuit
verification

FPGA and ASIC Technology

Comparison - 29

2009
2007 Xilinx, Inc. All Rights Reserved

Where Can I Learn

More?
Xilinx online documents
www.support.xilinx.com

Virtex-5 FPGA User Guide (Detailed architecture information)

Virtex-5 FPGA Packaging and Pinout Specifications (Pinout tables, PCB design rules, etc.)
Virtex-5 FPGA Configuration User Guide (Configuration overview, JTAG, readback, etc.)

Xilinx Training
www.xilinx.com/training

ChipScope Pro software course

PlanAhead software course
Timing Analyzer is taught in the Designing for Performance course
FPGA Editor, Floorplanner, SmartGuide technology, and partitions are taught in the
Advanced FPGA Implementation course
Free recorded e-Learning modules

ChipScope Pro and PlanAhead software are add-on products

www.support.xilinx.com/chipscopepro
Both are free for 60 days
FPGA and ASIC Technology
Comparison - 30

2009
2007 Xilinx, Inc. All Rights Reserved

End of Design Flow

You have completed
FPGA vs. ASIC Design Flow.
The next course in the ASIC curriculum sequence is

ASIC to FPGA Coding Conversion, Part 1

Continue

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FPGA and ASIC Technology
Comparison - 31

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2007 Xilinx, Inc. All Rights Reserved

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FPGA and ASIC Technology
Comparison - 32

2009
2007 Xilinx, Inc. All Rights Reserved