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Bram
Bram
Use IEEE.STD_LOGIC_1164.ALL;
entity bram is
port(clk:in std_logic;
addr:in integer;
we:in std_logic;
d_in:in std_logic_vector(7 downto 0);
d_out:out std_logic_vector(7 downto 0));
end bram;
architecture arch_bram of bram is
type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
signal r:ram_t:=(others=>(others=>'0'));
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we='1') then
r(addr)<=d_in;
else
d_out<=r(addr);
end if;
end if;
end process;
end arch_bram;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY bram_tb IS
END bram_tb;
ARCHITECTURE behavior OF bram_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bram
PORT(
clk : IN std_logic;
addr : IN integer;
we : IN std_logic;
d_in : IN std_logic_vector(7 downto 0);
d_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal addr : integer := 0;
signal we : std_logic := '0';
signal d_in : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal d_out : std_logic_vector(7 downto 0);