LIBRARY ieee;

USE

ieee.std_logic_1164.ALL;

ENTITY Compuertas_Instancia
IS
PORT(
A, B, C :
F
);
END Compuertas_Instancia;
ARCHITECTURE
Circuito
OF
COMPONENT
Compuerta_AND
PORT
(

IN
:

std_logic;
OUT
std_logic

Compuertas_Instancia

IS

A, B

IN

std_logic;
C

OUT

std_logic
);
END COMPONENT;
COMPONENT
PORT

Compuerta_OR
(
X, Y

IN

std_logic;
Z

std_logic
);
END COMPONENT;
SIGNAL union, union1

std_logic;

BEGIN
C1:
C2:
C3:

Compuerta_AND
Compuerta_OR
Compuerta_AND

PORT MAP (A=>A, B=>B, C=>union);

PORT MAP (X=>B, Y=>C, Z=>union1);
PORT MAP (A=>union, B=>union1, C=>F);

END Circuito;
-------------------COMPUERTA AND-------------------------LIBRARY ieee;
USE
ieee.std_logic_1164.ALL;
ENTITY Compuerta_AND
PORT(

IS
A, B
C
);

IN
:

OUT

std_logic;
std_logic

END Compuerta_AND;
ARCHITECTURE
BEGIN

Compuerta_A

OF

Compuerta_AND

IS

C <= A AND B;
END Compuerta_A;
---------------COMPUERTA OR-------------------------------LIBRARY ieee;
USE

ieee.std_logic_1164.ALL;

OUT

ENTITY Compuerta_OR
PORT(

IS
X, Y
Z
);

IN
:

OUT

END Compuerta_OR;
ARCHITECTURE
BEGIN

Compuerta_O OF Compuerta_OR

Z <= X OR Y;
END Compuerta_O;

IS

std_logic;
std_logic