This document discusses developing a UVM-based verification intellectual property (VIP) for a USB 2.0 host controller using SystemVerilog. It aims to verify all basic functionalities of the USB 2.0 host controller by validating various aspects of data and control flow and the four different transfer types defined in USB - control, interrupt, isochronous and bulk transfers. UVM is a simulator-independent methodology that provides automation to the digital verification process. It offers reusable base class libraries to help improve reusability of VIP blocks and accelerate the verification process.
This document discusses developing a UVM-based verification intellectual property (VIP) for a USB 2.0 host controller using SystemVerilog. It aims to verify all basic functionalities of the USB 2.0 host controller by validating various aspects of data and control flow and the four different transfer types defined in USB - control, interrupt, isochronous and bulk transfers. UVM is a simulator-independent methodology that provides automation to the digital verification process. It offers reusable base class libraries to help improve reusability of VIP blocks and accelerate the verification process.
This document discusses developing a UVM-based verification intellectual property (VIP) for a USB 2.0 host controller using SystemVerilog. It aims to verify all basic functionalities of the USB 2.0 host controller by validating various aspects of data and control flow and the four different transfer types defined in USB - control, interrupt, isochronous and bulk transfers. UVM is a simulator-independent methodology that provides automation to the digital verification process. It offers reusable base class libraries to help improve reusability of VIP blocks and accelerate the verification process.
The ever increasing advancement in IC technology escalated the complexity of electronic
system designs, which in turn demands sophisticated verification procedures to ensure the functional correctness of the same. This is indeed a challenging task which consumes around 70-80% of design resources in the design cycle of most design IPs. In order to overcome these challenges, standardised methodologies incorporating a higher level of automation and reusability are introduced in the functional verification procedure. The process involves the generation of input stimuli in conformance with various functional operating conditions, and the system response for each stimulus is measured and compared against the corresponding response from a golden design model. The project aims to develop Universal Verification Methodology (UVM) based Verification Intellectual Property (VIP) for USB2.0 Host Controller using System Verilog language. System Verilog is a combined Hardware Description Language (HDL) and Hardware Verification Language (HVL) which proves to be advantageous in the verification of larger, complex semiconductor designs since it provides a built-in support for advanced coveragedriven, constrained-random and assertion-based methodologies. UVM is a simulator vendor independent methodology that brings about much automation to the digital verification world. It offers base class libraries and its reconfigurable structure helps in improving the reusability of various VIP blocks across different designs to accelerate the verification process. Universal Serial Bus (USB) is an industry-standard extension which supports a wide range of devices. With USB2.0 data rates of over 480Mbps is supported. The USB Host Controller is the USB interface to the host through which actual communications take place. The project targets to verify all the basic functionalities of USB2.0 Host Controller by validating various aspects of data and control flow. It also attempts to verify the four different transfer types defined in USB control, interrupt, isochronous and bulk transfers.