Ruozhen Zhang

rxz131230
EECT5340
Dr. Liu Jin
Cadence Project

Transistor Sizing:
Transistor

Width

Length

N1

2 m

1 m

N4

2 m

1 m

N2

1.2 m

400 nm

N3

600 nm

400nm

P0

600 nm

1.6 m

P2

600 nm

1.6 m

The ICMR is 2V from the above plot of output voltage (net58) and common mode voltage. The output
voltage becomes flat below 0V and above 2V indicating a transistor has exited the saturation region.

The common mode voltage is set at 1V in the middle of the ICMR. The output (net58) vs differential
mode input is plotted across a DC sweep from -3 to 3 volts. The derivative of this transfer function is
also plotted indicating that the maximum slope is around 12.5.

The differential input is set at 1V and the output small signal gain at net58 is plotted in decibels over a
AC sweep from 1 to 1 giga hertz. At low frequencies, the gain is 40 dBs. At 14.07MHz, the gain
decreases by 3 decibels to 37dB. At 738MHz, the gain becomes 0 decibels (unity gain).