EE4340 / EECT 5340

Analog IC Analysis and Design

Fall 2014

Topic 7. Differential Amplifiers

Jin Liu Ph.D.
Professor
UT Dallas

Differential Amplifiers Very Important

Differential amplifier is among the most important
circuit inventions
Differential operation has become the dominant choice
in todays high-performance analog and mixed signal
circuits

Page 2

Single-ended and Differential Operation

A single-ended signal is measured with respect to a
fixed potential
A differential signal is measured between two nodes
that have equal and opposite signal excursions around a
fixed potential.
Common-mode (CM) level.

Page 3

Immunity of Environmental Noise

Corruption of a signal due to

coupling

V+ = Vcm+Vid/2
V- = Vcm-Vid/2

Reduction of coupling
by differential operation

Vcm = (V+ + V-)/2

Vid = V+ - V-

Page 4

Effect of Supply Noise

Page 5

Differential Distribution of Noisy Lines

Page 6

Major Advantages of Differential Signaling

Immunity of Environmental Noise
Noise coupling from digital lines
Power supply noise
Differential noisy lines
Increase the maximum achievable voltage swing (x2)
1v
0v
-1v

Single-ended swing: 2v
-1v to 1v
Differential swing: 4v
-2v to 2v
Page 7

Basic Differential Pair

AKA: Source-coupled pair or long tailed pair

Page 8

Input-output Characteristics
When Vin1<<Vin2, M1 off, M2 on,
ID2=ISS, Vout1=VDD, Vout2=VDD-RDISS
Vice versa
When Vin1=Vin2, both M1 and M2 are on,
Each get half the current,
Vout1=Vout2=VDD-RDISS/2
Nonlinear

Page 9

Input Common Mode Range (ICMR)

1. Tie both inputs together
2. Sweep the input voltage and
find the input voltage range in
which all transistors are
saturated

Vin,CM=Vgs1+Vod3=Vth1+Vod1+Vod3
Page 10

Input Common Mode Range

Iss

Id1=Id2=Id3/2=Iss/2

I SS
VT 1, 2 ,VDD ]
2
VGS1=VT1+sqrt{2*Iss/2/[K*(W/L)1]}

VGS1 VOD3 Vin ,CM min[VDD RD

VOD3=sqrt{2*Iss/[K*(W/L)3]}

Page 11

Large Signal Analysis

Suppose M1 and M2 are saturated

Vin1 Vin 2 VGS1 VGS 2
ID

1
W
nCox (VGS VT ) 2 ,VGS
2
L

2I D
W
nCox
L

VT

2 I D1
2I D2

W
W
nCox
nCox
L
L
2
(Vin1 Vin 2 ) 2
( I 2 I D1 I D 2 )
W SS
nCox
L
1
W
nCox (Vin1 Vin 2 ) 2 I SS 2 I D1 I D 2
2
L

Vin1 Vin 2

Page 12

Large Signal Analysis

Squaring both sides,

Also
Then

1
W
nCox (Vin1 Vin 2 ) 2 I SS 2 I D1 I D 2
2
L
1
W
W
2
( nCox ) 2 (Vin1 Vin 2 ) 4 I SS nCox (Vin1 Vin 2 ) 2 I SS 4 I D1 I D 2
4
L
L
2
4 I D1 I D 2 ( I D1 I D 2 ) 2 ( I D1 I D 2 ) 2 I SS ( I D1 I D 2 ) 2
1
W
W
( I D1 I D 2 ) 2 ( nCox ) 2 (Vin1 Vin 2 ) 4 I SS nCox (Vin1 Vin 2 ) 2
4
L
L
4 I SS
1
W
( I D1 I D 2 ) 2 ( nCox ) 2 (Vin1 Vin 2 ) 2 [
(Vin1 Vin 2 ) 2 ]
W
4
L
nCox
L
4 I SS
1
W
I D1 I D 2 nCox (Vin1 Vin 2 )
(Vin1 Vin 2 ) 2
W
2
L
nCox
L
Page 13

Large Signal Analysis

4 I SS
1
W
nCox | (Vin1 Vin 2 ) |
(Vin1 Vin 2 ) 2
W
2
L
nCox
L
I D I D1 I D 2 , Vin Vin1 Vin 2
I D1 I D 2

4 I SS
2
2Vin
W

C
I D 1
W n ox L
|
| nCox
Vin 2
L
4 I SS
2
Vin
W
nCox
L
Gm nCox

Sign of Id1-Id2, and Vin1-Vin2

W
I SS , Vin 0
L
Page 14

Large Signal Analysis

W
Gm nCox I SS , Vin 0
L
Vout1 Vout 2 (VDD RD I D 2 ) (VDD RD I D1 ) RD I D
W
| Av | nCox I SS RD
L
Page 15

Small Signal Analysis Differential Mode

Half-circuit concept

Node P is a virtual AC ground

Page 16

Lemma

Consider above circuit, where D1 and D2 represent any

three-terminal active device. Suppose Vin1 changes from Vo
to Vo+Vin and Vin2 from Vo to Vo-Vin. Then, if the
circuit remains linear, Vp does not change
Page 17

Prove

Assume V1 and V2 have equilibrium value of Va and change

by V1 and V2. The output currents then change by gmV1
and gmV2. Since I1+I2=IT, gmV1+gmV2=0, i.e. V1= V2. Also, Vin1-V1=Vin2-V2, thus Vo+Vin-(Va+V1)=VoVin-(Va+V2). Consequently, 2Vin=V1-V2=2V1.
Page 18

Small Signal Gain - Differential

vx
g m1 ( RD || ro1 )
vin1
vy
vin 2

vy
vin1

vin 2 vin1

g m 2 ( RD || ro 2 )

vx v y
vx v y
vout1 vout 2
gain

vin1 vin 2
vin1 (vin1 )
2vin1
vy
1 vx
gain (

)
2 vin1 vin1
1
gain [ g m1 ( RD || ro1 ) g m 2 ( RD || ro 2 )]
2
g m1 g m 2 g m1, 2 , ro1 ro 2 ro1, 2
gain g m1, 2 ( RD || ro1, 2 )
Page 19

Differential Pair with MOS Loads - Gain

Av g m1, 2

1
g m 3, 4 g o 3, 4 g o1, 2
1

Av g m1, 2 (ro1, 2 || ro 3, 4 || g m 3, 4 )
Av

g m1, 2
g m 3, 4

n (W / L)1, 2

p (W / L) 3, 4

Av g m1, 2

1
g o1, 2 g o 3, 4

Av g m1, 2 (ro1, 2 || ro 3, 4 )

Page 20

Differential Pair with MOS Loads _ICMR

Vin>Vgs1+Vds(sat, Iss), Vgs1=sqrt[2*Iss/2/(KW/L)]+Vth1

For M1 in sat, Vout>Vin-Vth1,
Vin<Vdd-Vsg3+Vth1, Id3=Iss/2
alt.

Vin<Vout_CM+Vth1
Vin<Vdd-Von3+Vth1
Von3=(Vdd-Vb)-|Vth3|
Page 21

Differential Pair with MOS Loads _Output Swing

Vcm+Vid/2

Vcm+Vid/2

Vcm-Vid/2

Vcm-Vid/2

Vout1<Vdd-|Vth3|, (Id3=0)
Maximum between
Vout1>Vdd-Vsg3, (Id3=Iss)
Vout1>Vcm-Vth1

Vout1<Vdd-Von3, (Id3=Iss/2)
Vout1>Vcm-Vth1

Page 22

Differential Pair with MOS Loads

Av g m1 ( g m3ro3ro1 || g m5 ro5 ro 7 )
Page 23

Common Mode Response

Vin1 VCM 0.5Vd
Vin 2 VCM 0.5Vd
Vin1 Vin 2
2
Vd Vin1 Vin 2
VCM

Av ,CM

Node P is not a AC ground!!

vout ( vout1 vout 2 vCM )

RD / 2

1
vin ,CM
RSS
2gm

In symmetric circuit, input CM

variations disturb the bias points,
alternating the small signal gain
and possibly limiting the output
voltage swings.
Page 24

Common Mode Response (2)

VDD

VDD

RD

RD
X

RD

Vout

M2

Vin,CM

Vin,CM

M1

M1

2RSS

Gm

2RSS

2RSS

gm
1 2g m RSS

Rout

RD [ro (1 2g m RSS )] RD [ro (1 2g m RSS )]

RD ro (1 2g m RSS )
ro (1 2g m RSS )

Av ,CM Gm Rout

g m RD
(1 2g m RSS )
Page 25

Common Mode Response

Variation of output CM level, in the absence of
mismatch
Av,CM
Conversion of input common-mode variations to
differential variation at the output
Circuit component mismatch
Asymmetrical topology
Av,CM-DM

Page 26

Component Mismatch

Common mode change at the

input introduces differential
change at the output
gm
V X Vin ,CM
RD
1 2 g m RSS
gm
V y Vin ,CM
( RD RD )
1 2 g m RSS
V X V y
gm
ACM DM

RD
Vin ,CM
1 2 g m RSS

Page 27

CMRR Common Mode Rejection Ratio

CMRR

ADM
ACM DM

Page 28

Differential Amplifier with Active Current Mirror

Load
Active current mirror
that process signal

When Vin1 decreases and Vin2 increase, more current flows through
M2 and M4, Vout decreases. When Vin1<<Vin2, M1 is off, zero
current flows through M1,M3. M3 is off, turns off M4. Zero current
flows through M4. This causes M2 and M5 to operate in deep triode
region, Vout=0.
Page 29

Differential Amplifier with Active Current Mirror

Load Large signal analysis cont.
Active current mirror
that process signal

When Vin1 increase and Vin2 decreases, more current flows through
M1 and M3, Vout increases. When Vin1>>Vin2, M2 is off, zero
current flows through M2,M4. M4 operates in deep triode region,
Vout=VDD
Page 30

Differential Amplifier with Active Current Mirror

Load Large signal analysis cont.
Active current mirror
that process signal

When Vin1=Vin2, each branch has half the tail current, Vout = VF
assuming perfect symmetry.
In reality, however, asymmetries in the circuit may result a large
deviation in Vout, possibly driving M2 or M4 into the triode region.
Page 31

Large signal analysis Input & Output Swing

Active current mirror
that process signal

For M2 to be saturated, Vout>Vin2-Vth2. For maximum swing

range, the input common mode level should be as small as possible.
Minimum input common mode level to keep all transistors saturated
is Vod5+Vgs1,2
The direct relationship between the input CM level and the output
swing in this circuit is a critical drawback.
Page 32

Small Signal Analysis

Asymmetry in two branches causes

small voltage swing in P.
If ignore this swing, P can be assumed
to be virtual ground.
(Refer to the Razavi book on analysis
when P is NOT assumed virtual ground.
The final result after approximation
leads to the same answer
here.)

Page 33

Small Signal Analysis Av, Gm and Rout

g m1

vin
g m1
2

vin
2

gm2

vin
2

Av=Gm Rout
Gm is short circuit transconductance;
it is calculated with the circuit setup
on the left.
vin
vin
iout g m1
gm 2
2
2
i
g gm 2
Gm out m1
g m1, 2
vin
2
Rout ro 4 || ro 2
Av Gm Rout g m1, 2 ( ro 4 || ro 2 )
Page 34

Common Mode Properties

Assuming symmetry,
Vout=VF

ACM

Vout
Vin ,CM

CMRR |

Even with perfect

symmetry, the output signal
is corrupted by input CM
variation a drawback that
does not exist in fully
differential circuits.

r
1
|| O 3, 4
2 g m 3, 4
2
g m1, 2
1

1
g m 3, 4 1 2 g m1, 2 Rss
Rss
2 g m1, 2

g (r || r )
ADM
| m1, 2 O1, 2 O 3, 4 (1 2 g m1, 2 Rss) g m3, 4 (rO1, 2 || rO 3, 4 )
g m1, 2
1
ACM
Page 35
g m 3, 4 1 2 g m1, 2 Rss

Homework #6
Due on 10/23/2014