SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

Volume 1, Number 1, December 2014

SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

Modeling of Discrete Systems Using State

Charts and Using VHDL Language in
Electronic Circuits
T. C. Manjunath1 *, Latha Parthiban2
1

HKBK College of Engineering, S.No. 22/1, Nagawara, Arabic College Post, Bangalore-45
Department of Computer Science, Pondicherry University, Lawspet, Pondicherry-605 008
*Corresponding author: dr.manjunath.phd@ieee.org
2

Abstract:
Design is a complex process which can be thought of as a top down refinement of a specification. The main aim of this algorithm is to propose a Verilog Hardware Description Language
(VHDL) code generator for real-time systems. Its importance lies in giving graphical interface
to the designer. Here, a discrete event model for a digital circuit using VHDL is designed and
implemented. This paper presents the design of state charts for 4 types of systems, viz., a
voice-mailing system, a washing machine, a microwave oven and a fax system. Once the state
chart is drawn, a software is designed which will automatically generate the corresponding
VHDL code for it.
Keywords:

1. INTRODUCTION
VHDL [1] is a language for describing digital electronic systems. A VHDL is designed in this paper
to fill a number of needs in the design process. Firstly, it allows description of the structure of a design,
i.e. how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, it
allows the specification of the function of designs using familiar programming language forms. Thirdly,
as a result, it allows a design to be simulated before being manufactured, so that designers can quickly
compare alternatives and test for correctness without the delay and expense of hardware prototyping.
A digital electronic system is designed as a module with inputs and / or outputs. The electrical values
on the outputs are some function of the values on the inputs. Figure 1 shows an example of this view of a
digital system as a structural description. The module F has two inputs, A and B, and an output Y. Using
VHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports. One
way of describing the function of a module is to describe how it is composed of sub-modules. Each of
the sub-modules is an instance of some entity, and the ports of the instances are connected using signals.
Figure 1 also shows how the entity F might be composed of instances of entities G, H and I. This kind of
description is called a structural description. Note that each of the entities G, H and I might also have a
structural description [2].
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Modeling of Discrete Systems Using State Charts and Using VHDL Language in Electronic Circuits

Figure 1. A digital electronic designed system

2. DESCRIBING BEHAVIOR
In many cases, it is not appropriate to describe a module structurally. One such case is a module which
is at the bottom of the hierarchy of some other structural description. For example, for designing a system
using Integrated Circuit (IC) packages bought from an IC shop, there is no need to describe the internal
structure of an IC. In such cases, a description of the function performed by the module is required,
without reference to its actual internal structure. Such a description is called a functional or behavioral
description. To illustrate this, suppose that the function of the entity F in Figure 1 is the exclusive-or
function. Then a behavioral description of F could be the Boolean function [3]:
+ A.B

Y = A.B

(1)

More complex behaviors cannot be described purely as a function of inputs. In systems with feedback,
the outputs are also a function of time. VHDL solves this problem by allowing description of behavior in
the form of an executable program.

3. DISCRETE EVENT TIME MODELING

Once the structure and behavior of a module have been specified, it is possible to simulate the module
by executing its behavioral description. This is done by simulating the passage of time in discrete steps.
At some simulation time, a module input may be stimulated by changing the value on an input port. The
module reacts by running the code of its behavioral description and scheduling new values to be placed
on the signals connected to its output ports at some later simulated time. This is called scheduling a
transaction on that signal. If the new value is different from the previous value on the signal, an event
occurs, and other modules with input ports connected to the signal may be activated [4].
The simulation starts with an initialization phase, and then proceeds by repeating a two-stage simulation
cycle. In the initialization phase, all signals are given initial values, the simulation time is set to zero,
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SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

and each modules behavior program is executed. This usually results in transactions being scheduled on
output signals for some later time. In the first stage of a simulation cycle, the simulated time is advanced
to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are
executed, and this may cause events to occur on some signals. In the second stage, all modules which
react to events occurring in the first stage have their behavior program executed. These programs will
usually schedule further transactions on their output signals. When all of the behavior programs have
finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole
simulation is completed [5, 6].
The purpose of the simulation is to gather information about the changes in system state over time.
This can be done by running the simulation under the control of a simulation monitor. The monitor allows
signals and other state information to be viewed or stored in a trace file for later analysis. It may also
allow interactive stepping of the simulation process, much like an interactive program debugger. We start
the description of an entity by specifying its external interface, which includes a description of its ports.
So, the counter is defined as:
entity count2 is
generic (prop delay: Time := 10 ns);
port (clock: in bit;
q1, q0: out bit);
end count2;
This specifies that the entity count2 has one input and two outputs, all of which are bit values, that is,
they can take on the values 0 or 1. It also defines a generic constant called prop delay which can be
used to control the operation of the entity (in this case its propagation delay). If no value is explicitly
given for this value when the entity is used in a design, the default value of 10 ns will be used. An
implementation of the entity is described in an architecture body. There may be more than one architecture
body corresponding to a single entity specification, each of which describes a different view of the entity.
The behavioral description of the counter is written as:
architecture behavior of count2 is
begin
count up: process (clock)
variable coun value : natural := 0;
begin
if clock = 1 then
count value:= (count value + 1) mod 4;
q0 <= bitval(count value mod 2) after prop delay;
q1 <= bitval(count value / 2) after prop delay;
end if;
end process count up;
end behavior;
In this description of the counter, the behavior is implemented by a process called count up, which is
sensitive to the input clock. A process is a body of code which is executed whenever any of the signals it
is sensitive to changes value. This process has a variable called count value to store the current state of
the counter.
The variable is initialized to zero at the start of simulation, and retains its value between activations
of the process. When the clock input changes from 0 to 1, the state variable is incremented, and
transactions are scheduled on the two output ports based on the new value [7].
The assignments use the generic constant prop delay to determine how long after the clock change
the transaction should be scheduled. When control reaches the end of the process body, the process is
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Modeling of Discrete Systems Using State Charts and Using VHDL Language in Electronic Circuits

Figure 2. Designed counter system

Figure 3. A Designed voice mail controller system

suspended until another change occurs on clock. The two-bit counter is also designed alternatively as a
combination of 2 flops and an inverter, as shown in Figure 3. This can be written in VHDL as:
architecture structure of count2 is
component t flipflop
port (ck : in bit; q : out bit);
end component;
component inverter
port (a : in bit; y : out bit);
end component;
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SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

signal 00, ff1, inv ff0 : bit;

begin
bit 0: t flipflop port map (ck => dock, q => ff0);
inv: inverter port map (a => ff0, y => inv ff0);
bit 1 : t flipflop port map (ck => inv ff0, q => ff1);
q0 <= ff0;
q1 <= ff1;
end structure;
In this architecture, two component types are declared, t flipflop and inverter, and three internal signals
are declared. Each of the components is then instantiated, and the ports of the instances are mapped onto
signals and ports of the entity. For example, bit 0 is an instance of the t flipflop component, with its ck
port connected to the clock port of the count2 entity, and its q port connected to the internal signal ff0.
The last two signal assignments update the entity ports whenever the values on the internal signals change.

4. STATECHART MODELING
Statecharts is a behavioral specification language proposed for specifying large real-time, event-driven,
reactive systems. It is a graphical language based on state-transition diagrams for Finite State Machines
(FSM) extended with many features like hierarchy, concurrency, broadcast communication and timeout.
A specification written in the language of Statecharts is called a statechart.
The language is built upon so-called basic states, like the states in a FSM, and transitions. Depth is
obtained by allowing super-states that contain sub states and internal transitions, leading to a hierarchy
of states, corresponding to AND/OR decomposition. Accordingly there are two types of superstates,
AND-states and OR-states. If the system is in an AND-state then it is simultaneously in all its immediate
sub-states. To be in an OR-state means to be in exactly one of its immediate sub-states. When a super-state
is exited, any computation inside is terminated. The immediate sub states of an AND-state are called
orthogonal components and they are executed in parallel.
Orthogonal components interact with each other and with their environment by means of events, i.e.
signals without measurable duration. Transitions have labels to specify when a transition is taken. Events
generated by a transition in one orthogonal component are broadcast, possibly triggering transitions in
other components which, in turn, might produce new events, etc. Thus a single event can initiate a whole
chain of events [8].

State charts =

State transition diagram +

Depth +

Orthogonality +
Broadcast

(2)

A statechart is designed for a generalized voice-mail system. The voice-mail controller behavior is as
follows:
1. It is either normal (working) or error (not working) i.e. it is either ON or OFF.
2. When it is normal, the system is in either review mode or send mode.
3. In review mode the system performs the functions like, repeat, save, erase. Similarly when in send
mode functions like, address & record are performed.
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Modeling of Discrete Systems Using State Charts and Using VHDL Language in Electronic Circuits

Figure 4. Implementation scheme algorithm

The statechart given below describes the behavior of the voice-mail controller system. In the Figure
3, states are represented by boxes with names. Transitions between states are represented by labeled
arrows. The states are either basic states like FSM states (e.g. address, repeat) or structured states
containing sub-statecharts, the latter being classified as either an AND (concurrent) state or an OR state;
e.g. voice-mail is an OR-state and send is a basic state.
The designed AND-OR tree representation for the voice-mail is shown above:

5. IMPLEMENTATION SCHEME
A statechart implementation as given in [7] consists in implementing all terms for all state chart
transitions, in a way that is similar to the conventional FSM implementation. An Implementation scheme,
simplified algorithm and flow chart for the proposed technique are as follows [9]:
Basic Proposed Program Algorithm:
1. Start
2. Input the no of OR and AND states.
3. Generate Schematic
4. Implement the VHDL code.
5. Compile the structure.
6. If compilation error then detect the error.
7. Display the VHDL code.
8. Stop
A semi-automatic washing machine is designed as a concurrent state chart. This example has hierarchy
(OR) and concurrency (AND) both, but we concentrate only on the concurrency aspect here. The semiautomatic washing machine has two tubs, one that washes the clothes and the other that dries them. Now
the process of washing and drying can take place simultaneously. Thus there exists Concurrency (AND)
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SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

Figure 5. Flow-chart of the proposed algorithm

Figure 6. Design of state chart for a washing machine

property. To maintain concurrency in the VHDL Code we can have designed separate architectures
for each sub-state. Thus the coding will be implemented using an entity, followed by the number of
architectures equal to the number of concurrent states.
A microwave oven is designed as a Hierarchical State Chart. The simplified State Chart would be
as under. In the oven, food can either be heated OR cooled; both cannot take place simultaneously.
Thus hierarchy (OR) property exists. To maintain hierarchy, we have used processor components while
implementing the VHDL Code [10].

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Modeling of Discrete Systems Using State Charts and Using VHDL Language in Electronic Circuits

Figure 7. Design of state chart for a microwave oven

6. FORMULATION OF AN GENERALIZED ALGORITHM FOR TRANSLATION OF STATE CHARTS TO VHDL

1. Start
2. Input the State-name, which can be declared as Entity.
3. Enter the set of Inputs, Outputs useful for interfacing with environment.
4. Define a Package containing all the signals useful for communication between the Statechart & its
components, basically the global signals.
5. Define hierarchical states as components (OR-states).
6. The component (OR-states) will have a separate Entity,
7. Architecture, etc for their sub states (AND-states) and more components for basic OR-states.
8. The concurrent states (AND-states) have their behaviors in separate architecture.
9. The main entity is mapped to the components (OR-state) of sub states.
10. Stop.

7. CODE TESTING
The Program code was tested for its accuracy & correctness using a Statechart for a Car Audio &
Light System, which is as shown below. The reason this typical example was used was that it involves
all possible aspects of Statecharts [11]. Once parsing has completed and the internal object model is
constructed, VHDL generation begins. The challenges associated with VHDL generation can be broken
into two general categories: converting Statechart syntax and semantics into functionally equivalent
VHDL, and creating VHDL code that will synthesize properly into hardware with functional and timing
equivalence with the rest of the system. The two types of problems are somewhat independent. For
example, you can have a solid methodology for converting Statechart syntax and execution order into
VHDL, but after synthesis the hardware may not match as expected, or may induce timing incompatibility
with other components in the system. Therefore, the two problems were discussed separately.

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SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

8. CONCLUSIONS
A discrete event model for a digital circuit using VHDL is designed and implemented. The design of
state charts for 4 types of systems, viz., a voice-mailing system, a washing machine, a microwave oven
and a fax system is herewith considered. A software is designed which will automatically generate the
corresponding VHDL code for it after designing the statechart.

References
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[4] D. Drusinsky-Yoresh, A state assignment procedure for single-block implementation of state charts,
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[7] D. Harel, Statecharts: A visual formalism for complex systems, Science of computer programming,
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[8] J. J. Hooman, S. Ramesh, and W.-P. de Roever, A compositional axiomatization of Statecharts,
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[11] Xilinx Tutorial for Statemachine encoding.

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