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Finite State Machines
Finite State Machines
12.1
Nov 2007
Current State
Q2 Q1 Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Procedure
Step 1: Start with the transition table of the flip-flop to be used
Output Transition
Required
Input
0 to 0
0 to 1
1 to 0
1 to 1
12.3
Nov 2007
Step 2: Construct Karnaugh maps for each input from the state
transition table and the flip-flop transition table
E.g. D-type
12.2
Nov 2007
Next State
Q2+ Q1+ Q0+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
12.4
Nov 2007
D2
Q2\Q1Q0
0
1
D1
D0
00
0
1
01
0
1
11
1
0
Q2\Q1Q0
0
1
00
0
0
01
1
1
11
0
0
10
1
1
Q2\Q1Q0
0
1
00
1
1
01
0
0
11
0
0
10
1
1
10
0
1
Q2\Q1Q0
0
1
00
0
1
01
0
1
11
1
0
10
0
1
Q2\Q1Q0
0
1
00
0
0
01
1
1
11
0
0
10
1
1
D1 = Q1. Q0 + Q1. Q0 = Q1 Q0
Q2\Q1Q0
0
1
12.5
Nov 2007
00
1
1
01
0
0
11
0
0
10
1
1
D0 = Q0
12.6
Nov 2007
1
=1
CLOCK
1
1
Q2
Q1
Q2
Q1
Q0
Q2
Q1
Q0
D0
&
&
D1
&
C1
D2
1D
Q0
Q1
Q2
&
12.7
Nov 2007
12.8
Nov 2007
Example
A 3-bit counter to count the decimal sequence
0, 2, 5, 6.
Counting sequence:
Decimal Q2
Q1
0
2
5
6
Current State
0
0
1
1
0
1
0
1
Q0
0
0
1
0
Next State
Q2
Q1
Q0
Undefined States
In this example, some of the possible 8 states are undefined
What happens if the circuit gets into one of the undefined states?
State Diagram:
e.g. at power-on
101
010
1.
110
2.
12.9
Nov 2007
12.10
Nov 2007
D2
CLOCK
Q0
Q1
Q2
D0
D1
C1
1D
Q0
D1
Q1
D2
Q2
D0
C u rre n t S ta te
12.11
Nov 2007
N e x t S ta te
Q2\Q1Q0
0
1
00
0
X
01
X
1
11
X
X
Q2\Q1Q0
0
1
00
1
X
01
X
1
11
X
X
10
0
0
Q2\Q1Q0
0
1
00
0
X
01
X
0
11
X
X
10
1
0
Q2
Q1
Q0
Q 2+
Q 1+
Q 0+
D2 = Q0 + Q2. Q1. Q0
D1 = Q1
10
1
0
D0 = Q2. Q1
12.12
Nov 2007
Modified State
Transition Table
Modified State
Diagram
111
Q2+
0
0
1
0
0
1
0
0
Next State
Q1+ Q0+
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
D2
Q2\Q1Q0
0
1
00
0
0
01
0
1
11
0
0
10
1
0
Q2\Q1Q0
0
1
00
1
0
01
0
1
11
0
0
10
0
0
Q2\Q1Q0
0
1
00
0
0
01
0
0
11
0
0
10
1
0
D1
D0
D0 = Q2. Q1. Q0
100
011
000
001
010
101
110
12.13
Nov 2007
12.14
000
101
010
CLOCK
Q0
Q1
Q2
ROM
110
C1
D0
D1
D2
1D
Data D2:0
A2
A1
A0
D2
D1
D0
12.15
CLOCK
Q0
Q1
Q0
Q2
Q1
Q2
Nov 2007
Nov 2007
C1
D0
ROM
D1
D2
12.16
1D
Q0
Q1
Q2
Nov 2007