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Khoa CN in T
- HCN TPHCM
Th nghim thit
k FPGA
Rev 1.0
Contents
Phn 1 :
I.
II.
III.
Phn 2 :
1.
2.
Fail
Fail
Schematic
Design
Function Design
Function And
Timing
verification
Pass
Layout
Design
Post-Layout Pass
Simulation
Fabrication
Hin nay, theo qui trnh sn xut Chip fabless, cc nh sn xut chip khng trc tip ch
to ra chip m h ch thit k cp cao ri outsource cho cc cng ty sn xut chuyn sn xut
chip nh TSMC, Samsung gia cng. Phng php thit k ny da trn cc standard-cell do
cc nh sn xut chip cung cp sn.
Logic Gate
Library
VHDL or Verilog
Coding
VHDL or Verilog
Cimulation
RTL Design
High-Level
Simulation
Fail
Logic
Synthesis
Gate-level
Simulation
Cell Layout
Library
Placement
& Routing
Post-Layout
Simulation
Fail
Fail
Fabrication
Phng php thit k da trn FPGA , cng gn ging nh phng php thit k standardcell Based . Nhng n s dng cc FPGAs logic cell , phng php ny cho thi gian thit k
v sn xut rt nhanh, v cc Chip FPGA c sn xut t trc , ri ro cng thp. Tuy nhin
nhc im ca n l mt tch hp khng cao lm, tc cng khng bng hai phng php
thit k trn. Tuy nhin phng php thit k da trn FPGA vn c s dng rt nhiu do thi
gian thit k nhanh, c kh nng ti cu hnh ng.
FPGA Cell
Library
VHDL or Verilog
Coding
VHDL or Verilog
Cimulation
RTL Design
High-Level
Simulation
Logic
Synthesis
Fail
Placement
& Routing
Post-Layout
Verification
Generate
FPGA
bitstream
Download
FPGA
Fail
Hnh sau l mt v d v kin trc ca mt FPGA cng nghip v chip FPGA trong thc t.
ng dng ca FPGA :
Logic Element
y l phn t logic nh nht trong kin trc FPGA thng thng, gi tt l LE, n cho php
thc hin cc chc nng logic hiu qu. c tnh ca mt LE :
L mt bng tra 4 ng vo (hoc nhiu hn ty kin trc FPGA) gi l look-up table
(LUT), m c th thc hin hm logic 4 bin bt k.
Mt thanh ghi c th lp trnh c (programmable register)
Mt chui cc kt ni mt xch.
Mt chui kt ni cc thanh ghi.
C kh nng li tt c cc loi lien kt ni bao gm : local, row, column, register chain,
hoc ni trc tip
Lin kt ni.
H tr register packing
H tr register feedback
LE Features
Ta c th cu hnh mi thanh ghi ca LE thnh D, T, JK, hoc SR flip-flop. Mi thanh
ghi c data, clock, clock enable, v chn clear. Tn hiu c th l global clock network, cc chn
I/O pins, hoc bt k logic ni no.
Cc chn I/O pins hoc logic ni c th li cc chn enable. Nu mun LE thc hin chc nng
ca cc mch t hp, LUT s c bypass qua khi thanh ghi.
Mng Logic (Logic Array Block)
Mt mng logic bao gm nhiu khi LE v cc h thng lin kt ni hng ,ct , h thng bus ni
b
Hnh 7 : LAB
I/O Pins
H thng IO ca FPGA thng t chc thnh cc Bank, mi bank gm nhiu chn IO c
cng tnh nng. h tr nhiu h thng phn cng khc nhau, cc chn IO ca FPGA gm
hng chc kiu khc nhau vi cc tnh cht v in cng khc nhau (xem bng).
Hnh 9 : IO Pins
Hnh 10 : IO Banks
III.
1. Gii thiu
Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc lnh vc lun
l s hc (digital logic), t chc my tnh (computer organization) v FPGA.
Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht trin, di y
l thng tin chi tit ca mt board DE2:
FPGA:
- Vi mch FPGA Altera Cyclone II 2C35.
- Vi mch Altera Serial Configuration EPCS16.
Cc thit b xut nhp:
- USB Blaster cho lp trnh v iu khin API ca ngi dung; h tr c 2 ch lp
trnh JTAG v AS.
- B iu khin Cng 10/100 Ethernet.
- Cng VGA-out.
- B gii m TV v cng ni TV-in.
- B iu khin USB Host/Slave vi cng USB kiu A v kiu B.
- Cng ni PS/2 chut/bn phm.
- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in, lineout, v microphone.
- 2 Header m rng 40-pin vi lp bo v diode.
- Cng giao tip RS-232 v cng ni 9-pin.
- Cng giao tip hng ngoi.
B nh:
- SRAM 512-Kbyte.
- SDRAM 8-Mbyte.
- B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte).
- Khe SD card.
Switch, cc n led, LCD, xung clock
- 4 nt nhn, 18 nt gt.
- 18 LED , 9 LED xanh, 8 Led 7 on
- LCD 16x2
- B dao ng 50-MHz v 27-MHz cho ng h ngun.
3. Mt vi ng dng ca board DE2
ng dng lm TV box
IV.
1. Gii thiu
Ci t Quartus II v Nios II
Qu trnh ci t Quartus II v Nios n gin ch cn a a vo my v thc hin theo
hng dn ca chng trnh ci t nh bt k phn mm no .
Kt tip bn chn Search for the best driver in these location v sau nhn Browse.
Ca s thng bo vic kim tra logo window khng thnh cng, tuy nhin vic ny s
khng b nh hng n vic kt ni ca chng trnh sau ny. Bn tip tc nhn Continue
Anyway. Nhn Finish hon tt vic ci t.
Ch driver USB blaster c th nm trong th mc khc so vi hng dn ty thuc vo
phin bn quartus m bn ci t, thm ch bn c th copy driver ti mt th mc khc v tr
ng dn ti th mc ny khi ci t.
Hnh 22 : To mi mt project
Hnh 23 : Chn tn v ng dn
1:Chn dng dn th mc
2: Chn tn th mc
Bc 3. Sau ta chn hng sn xut chip v tn loi chip trn mch (EP2C35F672C6)
Hnh 25 : To mi file
Bc 2. Sau chn loi file m chng ta mun vit chng trnh. y ta chn loai
file Verilog HDL
Bc 4. Sau khi vit xong th ta phi lu tn file trng vi tn module ca chng trnh
Trong thit k ny ta c 3 chn : f,x1,x2 .vi f l chn output, ta s gn cho LEDR[0]. x1,x2 l
input, ta s gn cho SW[0] v SW[1].
Sau khi gn xong, ta s c nh sau:
Sau khi gn chn xong, ta thc hin bin dch li thit k cp nht thng tin v pin.
Mt cu hi t ra l : ta ly thng tin v cc chn ny u ?
Tr li :
V cc chn ny c ghp ni vi phn cng trn board bi nh thit k board DE2,
do c thng tin v chn IO, ta tm trong ti liu DE2 manual.
Mt cch khc, cc nh thit k board FPGA thng cung cp mt file CSV (mt dng
ging excel) c th import trc tip vo phn mm quartus vi tn chn c nh ngha
sn, vd file DE2_pin_assignments.csv i vi board DE2.
import file ny,vo assignments>import assignments. Chn ng dn n file
DE2_pin_assignments.csvri nhn OK.
kim tra kt qu, vo li Assignments>Pin Planner, s thy nh sau.
trng. Trong ch th hai, ch AS, file cu hnh c lu trong chip flash trn kit
FPGA. V n s c load vo FPGA mi khi bt ngun, v vy, chng ta s khng cn phi
np li file cu hnh mi khi bt ngun kit FPGA na (nh trng hp np JTAG)
. chn la mode np, chn RUN/PROG switch trn DE2 board. V tr RUN l chn JTAG
mode, cn v tr PROG l chn AS mode.
Qu trnh np thng qua mode JTAG nh sau :
o Gt switch RUN/PROG trn FPGA sang v tr RUN.
o Chn Tools>Programmer. Mt ca s s hin ra nh hnh 35.
o y chng ta cn phi ch nh cng c lp trnh v mode lp trnh
o Chn JTAG trong hp thoi mode
o Nu USB-Blaster cha c chn, nhn vo hardware Setup v chn USBBlaster trong hp thoi s xung nh hnh 36
Ty theo c s h tng thit b, cc bi lab c th thc hin theo cc cch khc nhau :
Nu khng c phn cng, c th m phng bng phn mm model-sim hoc quartus
simulation
Nu c phn cng (DE1,DE2 hoc tng ng) c th tng hp trc tip v thc hin
ngay trn phn cng ca kit FPGA (c th m phng hoc khng, ty yu cu ca gio
vin hng dn).
Reference Documents
1) Haibo Wang , ECE428, ECE Department , Southern Illinois University , Carbondale, IL
62901.
2) Ti liu TN FPGA, Khoa KH-KTMT ,Trng i Hc BK TP HCM
3) Altera University Program Documents
4) Altera website
5) Internet