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LG 42pj350 Training Manual
LG 42pj350 Training Manual
OUTLINE
Preliminary:
Contact Information, Preliminary Matters, Specifications,
Plasma Overview, General Troubleshooting Steps,
Disassembly Instructions, Voltage and Signal Distribution
No Main Power Switch (Vacation Switch).
Troubleshooting:
Circuit Board Operation, Troubleshooting and Alignment of :
Switch Mode Power Supply No VS On command input to SMPS
Y-SUS Board Delivers Logic Signals and FG5V to Y-Drive board.
Y-Drive Board
Z-SUS Output Board (Also uses one Z-SUB board for bottom panel connector)
Control Board
X Drive Boards (2)
Main Board
Interconnect Diagram: 11X17 Foldout Section used as a quick reference sheet.
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42PJ350
Plasma
The next section will get the Technician familiar with the Disassembly, Identification
and Layout of the Plasma Display Panel.
At the end of this Section the Technician should be able to Identify the Circuit
Boards and have the ability and knowledge necessary to safely remove and
replace any Circuit Board or Assembly.
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Plasma
LG Contact Information
Customer Service (and Part Sales)
(800) 243-0000
(800) 847-7597
http://gsfs-america.lge.com
us.lgservice.com
Knowledgebase Website
lgtechassist.com
LG Web Training
lge.webex.com
LG CS Academy
lgcsacademy.com
http://136.166.4.200
LCD-DV: 32LG40, 32LH30, 37LH55, 42LG60, 42LG70, 42LH20, 42LH40, 42LH50, 42LH90, 42SL80,
47LG90, 47LH85, 47LE8500
PLASMA: 42PG20, 42PQ20, 42PQ30, 50PG20, 42PJ350, 50PK750, 50PS80, 50PS60, 60PK750,
60PS11, 60PS60, 60PS80
Also available on the Plasma Page:
PDP Panel Alignment Handbook, Schematics with Bookmarks
Plasma Control Board ROM Update (Jig required)
August 2010
42PJ350
Plasma
CAUTION
To avoid personal injury, disconnect the power before servicing this product. If electrical power
is required for diagnosis or test purposes, disconnect the power immediately after performing
the necessary checks. Also be aware that many household products present a weight hazard.
At least two people should be involved in the installation or servicing of such devices.
Failure to consider the weight of an product could result in physical injury.
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ESD Notice
Todays sophisticated electronics are electrostatic discharge (ESD) sensitive. ESD can weaken or damage
the electronics in a manner that renders them inoperative or reduces the time until their next failure.
Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. Alternatively,
you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. Before
removing a replacement part from its package, touch the anti-static bag to a ground connection point or
unpainted metal in the product. Handle the electronic control assembly by its edges only. When
repackaging a failed electronic control assembly in an anti-static bag, observe these same precautions.
Regulatory Information
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy, and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful interference to
radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate
the receiving antenna; Increase the separation between the equipment and the receiver; Connect the
equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the
dealer or an experienced radio/TV technician for help.
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Approximately 10 minute pre-run time is required before any adjustments are performed.
2.
Refer to the Voltage Sticker inside the Panel when making adjustments on the Power Supply, Y-SUS and Z-SUS Boards.
3.
Always adjust to the specified voltage level (+/- volt) unless otherwise specified.
4.
Be cautious of electric shock from the PDP module since the PDP module uses high voltage, check that the Power Supply
and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal.
4.
C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity.
5.
The PDP Module must be carried by two people. Always carry vertical NOT horizontal.
6.
7.
Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit.
8.
Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry.
9.
New Panels and Frames are much thinner than previous models. Be Careful with flexing these panels. Be careful
with lifting Panels from a horizontal position. Damage to the Frame mounts or panel can occur.
10. New Plasma models have much thinner cabinet assemblies and mounts.
Be extremely careful when moving the set around as damage can occur.
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42PJ350 Specifications
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TruSlim Design:
At less than 1" thick the new TruSlim Frame trims away distraction without
compromising screen size.
USB 2.0:
View videos and photos and listen to music on your TV through USB 2.0.
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Plasma
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600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process
(vs. Comp. 8 sub-field/frame)
Original Image
Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.
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Plasma
BOTTOM PORTION
p/n AKB72914201
TOP PORTION
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42PJ350
Plasma
AC In
SIDE
INPUTS
REAR
INPUTS
USB
HDMI 3
Composite
Video/Audio
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Plasma
42PJ350 Dimensions
Power:
285W (Typical)
0.2W (Stand-By)
38-7/8"
955.06mm
11-7/16
290mm
27-1/8"
688.34mm
24-5/6"
617.22mm
2-3/16"
55.88mm
4-9/16
116mm
15-3/4"
400mm
Model No.
Serial No.
Label
15-3/4"
400mm
Remove 4 screws
to remove stand
for wall mount
3-15/16
100mm
2-13/16"
71.43mm
Weight:
2-3/16"
56mm
47.6 lbs with Stand
41.1 lbs without Stand
18-3/4"
476.25mm
17
10-3/16"
259.08mm
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DISASSEMBLY SECTION
This section of the manual will discuss Disassembly, Layout and Circuit
Board Identification, of the 42PJ350 Advanced Single Scan Plasma Display Panel.
Upon completion of this section the Technician will have a better
understanding of the disassembly procedures, the layout of the printed
circuit boards and be able to identify each board.
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Plasma
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42PJ350
Plasma
FPC
FPC
FPC
Z-SUS
FPC
Y-Drive Board
FPC
Power Supply
(SMPS)
Y-SUS
Z-SUB
Main Board
Control
FPC
FPC
FPC
Conductive Tape
Left X
TCP
Heat Sink
AC In
Side
Input
(part of
main)
Right X
Conductive Tape
Conductive Tape
IR/LED
Board
Soft Touch
Keyboard
Invisible Speakers
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42PJ350
Plasma
P201
Y-DRIVE
Board
P202
p/n: EBR63633601
P2
P811
P206
SMPS
POWER SUPPLY
Board
P303
P201
P204
Y-SUS
Board
P205
P106
P211
P101
p/n: EBR63038801
Top row Odd
Back row Even
SC101
L N
p/n: EBR63038301
P163
n/c
P813
LVDS
P703
P301
P900
n/c
P704
MAIN
Board
P162
P206
AC
In
P100
P201
LEFT X Board
P202
p/n: EBR63628801
P203
P204
P211 P232
P205
P206
P1
Z-SUB Board
P801
P233
P2
P121 P102
p/n: EBR63632301
P161
P3
p/n: EBR63634601
CONTROL
Board
P209
P4
P1
p/n: EAY60912401
P101
Z-SUS
Board
P331 P311
P301
p/n: EBT60953602
RIGHT X Board
p/n: EBR63628701
P302
P303
P304
P305
P306
P101
FRONT IR
p/n: EBR65007704
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Remove the Left Vertical Brace. 4 screws, 2 metal tap and 2 plastic tap.
Disconnect the following connectors: P201, P203, P206, P211 and Ribbon Cable P101.
To remove P101, lift up on the locking mechanism and pull the ribbon cable out.
Remove the 16 screws holding the Y-SUS in place. Do not run the set with P211removed.
Remove the Y-SUS board. When replacing, be sure to readjust the Va/Vs voltages in accordance with the
Panel Label.
Confirm VSC, -Vy and Z-bias as well.
Y-Drive Board Removal
Board Standoff
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Heat transfer
material
Heat sink
Disconnect all TCP ribbon cables from the defective X-Drive board and all other Ribbon cables going to
the board.
Remove the (3 Left or Right X) or (5 Center X) screws holding the defective X-Drive board in place.
Remove the board. Reassemble in reverse order. Recheck Va / Vs / VScan / -VY / Z-Drive.
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42PJ350
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E
Left
E
Right
D
Warning:
Ground
Wire
F
Heat Sink
D
Warning Shorting Hazard: Conductive Tape. Do not allow to touch energized circuits.
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August 2010
42PJ350
Plasma
P211 to P311
Left X to Right X
P211, P311
Are the same
TCP
Example
Cushion (Chocolate)
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Tab
Tab
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Plasma
The Left X Board drives the Right 5/16 of the side of the screen vertical electrodes
The Center X Board drives the Center 3/8 of the of the screen vertical electrodes
The Right X Board drives the Left 5/16 of the side of the screen vertical electrodes
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At the end of this Section the technician should understand the operation of each
circuit board and how to adjust the controls. The technician should be able with
confidence to troubleshoot a circuit board failure, replace the defective circuit and
perform all necessary adjustments.
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Y Drive
FPCs
P201
Error Com
Vs
Display Panel
Horizontal
Electrodes
Sustain
Vs
P206
FPCs
P811
FG
P202
P203
SMPS
Board
P201
M5V, Vs, Va
Y-SUS Board
Note:
Va not used
by Y-SUS only
fused and routed
to the X-Board
FG
P2
SK101
P813
AC
Input
Filter
FPCs
P4
SMPS
Turn On
Commands
RL_ON +17V, +5V, AC Det
M_On
Z-SUS
Board
M5V, Va, Vs
FG
P204
FG5V
FG15V
18V
VSC
-VY
FG
P205
P101
Scan
P206
Logic Signals
To Y-SUS and Y-Drive
P121
P161
P106
P211
P209
3.3V
Va
RGB Logic
Signals
P162
MAIN Board
RGB Logic
Signals
P704
P801
3.3V
STBY
P201
P202
X-Board-Left
P203
P204
P211 P232
P205
P331
P206
P301
P311
FPCs
3.3V
Key Board
Pull Up
IR,
Soft Touch Keys
Intelligent Sensor P101 And Power Button
P100
Va
P233
P1
Speakers
P703
P301
3.3V
P2
Z-SUB
Board
P102
P3
P211
P302
P331
P303
X-Board-Right
P304
P305
P306
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(11)
(3)
(4)
(5)
(6)
(10)
(9)
(8)
(12)
(13)
(14)
(15)
(7)
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Plasma
Adjustment Notice
Set-Up -Vy
Vsc Ve
ZBias
Panel
Rear View
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Plasma
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42PJ350
Plasma
Y-SUS Board
Main Board
VS
VA
M5V
Used to develop Bias Voltages on the Y-SUS then routed to the Control
board and then to the Z-SUS Board.
STBY 5V
Microprocessor Circuits
17V
5V
Also AC_Det (if missing, shuts of TV in 10 seconds) and Error_Det (not used)
Adjustments
There are 2 adjustments located on the Power Supply Board VA and VS. The
M5V is pre-adjusted and fixed. All adjustments are made referenced to Chassis
Ground. Use Full White Raster 100 IRE
VS
VR901
VA
VR502
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Plasma
P811
Q902
VS
F801
4A 250V
2.6V STBY
390V Run
D801
T901
Q802
IC301
Q504
VA
Q501
D807
POWER SUPPLY
p/n: EAY60912401
D307
D601
T301
T901
D308
D309
D306
D302
At Power Off
3sec 1st Relay click
4sec 2nd Relay click
D102
RL103
D301
D101
VR502
VA
Q351
Q603
Q355
M5V
D609
D303
Q601
L691
VR901
VS
Q901
Q801
D802
Q602
D904
IC701
Q351
(STBY 5V)
F101
10A 250V
RL101
CN701
n/c
P813
L602
AC In
35
SC101
August 2010
42PJ350
Plasma
VS
Source
Fuse F801
2.6V Stby
390V Run
To Y-SUS
4Amp/250V
VA
Source
VA VR502
PFC
Circuit
Primary
Source
Bridge
Rectifier
Fuse F302
160V Stby
389V Run
M5V
Source
2.5Amp/250V
RL104
RL103
+5V
Source
17V
Source
STBY-5V Controller
Source N/C
STBY-5V
+5V
and
Controller
On Back of
the board
To MAIN
Main Fuse
F101
36
P813
AC Input
SC 101
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Plasma
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42PJ350
Plasma
AC In
AC
Det
+5V
Regulator
Stand
By 5V Reg
STBY
3.46V
AC
Det.
RUN
5.14V
17V
Reg
5V
Vs
Reg
Vs
Va
Reg
Va
M_On
3.3V Reg
3.3VST
IC302
2
17V
Audio
IC801
3
6
+5V HDMI
EDID
And other
circuits
Microprocessor
IC1
M_On
Va
18V
5VFG
8
M5V
18V / M5V
3.3V
18V / M5V
Y DRIVE Upper
3.3V
Va
MAIN
Board
CONTROL
Z-SUS
5V
Floating
Gnd
At point 3
TV is in
Stand-By
state. It is
Energy Star
Compliant.
Less than 1
Watt
VA
8
X Board Left Va
Va
3.3V
X Board Right
3.3V_ST
7
4
Vs
Y-SUS
5
Error Relay
Det. On
Vs M5V Vs
AC Det.
If missing,
set will not
turn on.
Vs
RL On
Error Det.
Reset
C108, D1,
R62
M5V
17V
Not
Used
M5V
Reg
Va
If
missing
set
shuts
off in 10
Sec.
Power On
Front IR
Board
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August 2010
42PJ350
Plasma
Example
Voltage Label
Va TP
Pin 6 or 7
Vs Adjust:
Place voltmeter on VS TP.
Adjust VR901 until the reading
matches your Panels label.
Va Adjust:
Place voltmeter on VA TP.
Adjust VR502 until the reading
matches your Panels label.
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42PJ350
Plasma
100W
VS
VR901
VS Adj
T901
P811
Pins
100W
F801
4A 250V
Gnd
VR502
VA Adj
Pins
or
or
P811
F302 2.5A
250V
Check Pins 1 or 2
for Vs voltage
Check Pins 6 or 7
for Va voltage
Note:
Always test the SMPS under a
load using the 2 light bulbs.
Abnormal operational
conditions may result if not
loaded.
T301
L601
F101
10A 250V
P813
L602
SC101
AC In
Note:
To turn on the Power Supply;
1) With Main Board connected, press power.
2) Without Main Board connected SMPS will turn on automatically.
P813
Any time AC is applied to the SMPS, STBY 5V will be 3.49V and will
be 5.23V when the set turns on.
AC DET WILL NOT be present until set comes on.
If AC Det is missing, the TV will come on and shut off in 10 Seconds.
Check Pins 13 or 14
For 5V SBY (5.23V)
Check Pins 1 or 2
For 16.79V
Check Pin 8
For Error Det (4.9V)
Check Pin 16
For AC Det (4.45V)
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Plasma
(A) Ground the Auto Gnd Line (Pin 18) will allow the supply to be
powered up one section at a time.
(B) Add a 100 watt resistor from 5V Standby to RL_ON and the 17V
and 5V Run Lines on P813 will become active. Also AC-Det and
Error_Det will go high.
(C) Add a 100 watt resistor from any 5V line to M_ON (Monitor On) to
make the M5V, VS and VA lines operational.
P811 (VS pins 1 and 2) (VA pins 6 and 7) and the (M5V pins 9 and 10).
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Label
STBY
Run
No Load
Diode
1~2
17V
0V
16.8V
16.79V
Open
3~4
Gnd
Gnd
Gnd
Gnd
Gnd
5~7
5V
0.47V
5.24V
5.25V
1.29V
Error_Det
2.88V
4.93V
4.91V
2.96V
9~12
Gnd
Gnd
Gnd
Gnd
Gnd
13~14
STBY_5V
3.49V
5.23V
5.25V
2.43V
15
RL_ON
0V
2.43V
0.0V
Open
16
AC Det
0V
4.45V
4.93V
2.95V
M_ON
0V
3.27V
0.0V
Open
Auto_Gnd
Gnd
Gnd
4.84V
2.34V
17
18
P813
1
a Note: The 17V, 5V, AC_Det and Error Det turn on when the RL_On command arrives.
b Note: The M5V, Va and Vs turn on when the M_On (Monitor On) command arrives.
c Note: The Error Det line is not used in this model.
d Note: If the AC Det line is Missing, the TV will shut off after 10 seconds of operation.
e Note: Pin 18 is grounded on the Main board. If this line is floated, the SMPS turns on
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
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SMPS Connector SC101 and P811 Identification, Voltages and Diode Check
SC101 AC INPUT
Connector
SC101
P811
1
Vs TP
Va TP
Pin Number
L and N
Standby
Run
120VAC
120VAC
Diode Mode
Open
Pin
Label
Run
Diode Mode
1, 2
*Vs
*206V
Open
n/c
n/c
n/c
4, 5
Gnd
Gnd
Gnd
6, 7
*Va
*60V
Open
Gnd
Gnd
Gnd
9, 10
M5V
5.25V
2.12V
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
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(Overview)
Y-SUS Board develops the V-Scan drive signal to the Y-Drive boards.
This Section of the Presentation will cover alignment and troubleshooting the Y-SUS Board
for the Single Scan Plasma. Upon completion of the Section the technician will have a better
understanding of the operation of the circuit and will be able to locate voltage and
Diode mode test points needed for troubleshooting and alignments.
Adjustments
DC Voltage and Waveform Checks
Diode Mode Measurements
OPERATING VOLTAGES
SMPS Supplied
VA
VS
M5V
Y-SUS Developed
-VY VR502
VSC VR501
V SET UP VR601
V SET DN VR401
18V
Floating Ground
FG 5V
FG 15V
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August 2010
42PJ350
Plasma
Distributes
VA
Left X Board
Circuits generate
Y-Sustain Waveform
Z-SUS Board
VA
Distributes Vs
Control Board
Y-Drive Board
Receives Scan Waveform
Display Panel
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August 2010
42PJ350
Plasma
VS and ERR_COM
to the Z-SUS
p/n: EBR63038301
Floating Gnd
P206
c
FS203 (VS)
4A/250V
Floating Gnd
FS201 (M5V)
4A/125V
c
P201
VR601
Set Up
Floating Gnd
-Vy TP
Y-SCAN
Floating Gnd
VR501
VSC
To Y-Drive
P211
Logic Signals to
Y-Drive Board
FS203 (Va)
10A/125V
VR401
Set Up
VSC TP
P101
P209
VR502
-Vy
Ribbon
Logic Signals from
the Control Board
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August 2010
42PJ350
Plasma
42PJ350 Y-SUS
Layout Drawing
Y-SUS BOARD
p/n: EBR63038301
Example:
Model : PDP 42T1###
Voltage Setting: 5V/ Va:60/ Vs:205
N.A. / -195 / 145 / N.A. / 110
Max Watt : 250 W (Full White)
-Vy
P206
IC703
D33
Q22
Q16
FS201 M5V
125V
4A
Q21
Q15
VSC
D712
IC701
IC702
WARNING:
The Y-DRIVE Board has to be
removed completely if P211 is removed.
D713
D31
Label
Run
Diode Check
SUS_DN (FG)
FG
FG
SUS_DN (FG)
FG
FG
OC2
2.63V
1.46V
OC2
2.63V
DATA
DATA
IC601
P201
Q31
VR601
Set-UP
Q13
Label
Run
1~2
+Vs
*206V
n/c
n/c
n/c
4~7
ER_PASS
133V
Open
n/c
n/c
n/c
9~12
Gnd
Gnd
Gnd
Q33
FG
Diode
Check
Open
Pin
FS202 Vs
125V
4A
Pin
Diode
Check
Open
Label
Run
1~2
VS
*206V
n/c
n/c
n/c
4~5
Gnd
Gnd
Gnd
6~7
VA
*60V
Open
Gnd
Gnd
Gnd
9~10
M5V
5.25V
2.12V
Label
Run
Diode Check
1~3
+15V
18.24V
1.14V
4~7
+5V
5V
1.11V
1.45V
8~11
Gnd
Gnd
Gnd
0V
1.36V
12
Dummy_2
2.14V
2.80V
0V
1.37V
13
Y-OE
0.02V
1.81V
14
OC2
1.85V
2.81V
15
ER_DN
1.05V
2.81V
16
DATA
0V
2.81V
17
ER_UP
0.26V
2.81V
2.81V
OC1
2.2V
1.45V
OC1
2.2V
1.45V
STB
2.8V
1.36V
10
STB
2.8V
1.36V
11
CLK
0.86V
1.36V
12
CLK
0.86V
1.36V
13
SUS_DN (FG)
FG
FG
14
SUS_DN (FG)
FG
FG
15
FG5V
4.9V
1.97V
16
FG5V
4.9V
1.96V
17
SUS_DN (FG)
FG
FG
From VS
T501 Driver IC501
-VY D502
VSC D503 to Q501
From M5V
T502 Driver IC509
18V D506
FG 5V D509
FG 15V D508
Q12
FG
VSC
TP
Q41
-Vy
TP
Q11
VR501
VSC
VR401
Set-Dn
-VY
IC401
Q503
-Vy
422V p/p
D502
VSC
Q501
C213
D513
15V FG
J18
15V FG D508
IC502
IC301
IC510
D506
5V FG
IC201
IC303
+18V
D509
IC202
T501
D503
SCAN
P211
+18V
T502
IC501
FS203 VS
125V / 10A
D716
+15V
J461
P101
IC103
OE TP
VR502
-Vy
J11
IC102
P209
IC509
47
August 2010
18
BLK
1.4V
19
SET_UP
0.24V
2.81V
20
STB
1.5V
2.81V
21
Dummy_5
1.05V
3.19V
22
CLK
0.59V
2.81V
23
SUS_DN
2.75V
2.81V
24
Dummy_3
1.97V
2.81V
25
Dummy_1
1.04V
2.81V
26
Dummy_4
1.23V
3.19V
27
SUS_UP
0.05V
2.81V
28
CTL_OE
0.23V
3.18V
29
SET_DN
2.10V
2.81V
30
Gnd
Gnd
Gnd
42PJ350
Plasma
CAUTION: Use the actual panel label and not the book for exact voltage settings.
This is just for example
Set should run for 15 minutes, this is the Heat Run mode.
Set screen to White Wash.
1) Adjust Vy VR502 to Panels Label voltage (+/- 1V)
2) Adjust VSC VR501 to Panels Label voltage (+/- 1V)
-Vy
VSC
-Vy TP
VSC TP
VR501
VSC Adj
VR502
-Vy Adj
Voltages Reads
Positive
48
August 2010
42PJ350
Plasma
2MSec
69 to 72 Vrms
540V p/p
White to Black
200uSec
100uSec
49
August 2010
42PJ350
Plasma
50
August 2010
42PJ350
Plasma
Adjustment
Area
Fig 1:
As an example of how to lock in to the Y-Drive Waveform.
Fig 1 shows the signal locked in at 2ms per/div.
Note the 2 blanking sections.
The area for adjustment is pointed out within the Waveform
Fig 2:
At 200uSec per/division, the area of the waveform to
use for SET-UP or SET-DN is now becoming clear.
Now the only two blanking signals are present.
Area to
expand
FIG1
2mS
Blanking
Blanking
Adjustment
Area
FIG2
200uS
Area to
expand
Blanking
Fig 3:
At 100us per/div the area for adjustment of SET-UP or SET-DN
is now easier to recognize. It is outlined within the Waveform.
Remember, this is the 1st large signal to the right of blanking.
FIG3
100uS
Expanded from above
155V
p/p
170 uSec
51
August 2010
42PJ350
Plasma
Observe the Picture while making these adjustments. Normally, they do not have to be done.
ADJUSTMENT LOCATION:
Center Right of the board.
VR601
SET-UP ADJUST:
1) Adjust VR601 and set the (A) portion of the signal to
match the waveform above. (155V p/p 5V)
VR401
B
SET-DN ADJUST:
2) Adjust VR401 and set the (B) time of the signal to match
the waveform above. (170uSec 5uSec)
ADJUSTMENT LOCATION:
Lower Center Right
of the board.
52
August 2010
42PJ350
Plasma
Normal
170uSec
Normal
155V
Too Low
146V
Too Short
116uSec
Too Low
204V
Floor
53
August 2010
118V off
the Floor
42PJ350
Plasma
C213
Scan
TIP: You can also use C213 left leg to test for
V-Scan signal when the Y-Drive board is removed
54
August 2010
42PJ350
Plasma
P211
Y-Scan
Signal
c
c
Y-Drive
Board
Y-SUS
Board
55
August 2010
42PJ350
Plasma
Pins 3~12
P211
P211 Connector
Y-Scan
Signal
c
c
Y-Drive
Board
Y-SUS
Board
Pin
Label
17
SUS_DN (FG)
15-16
FG5V
13-14
SUS_DN (FG)
11-12
CLK
9-10
STB
7-8
OC1
5-6
DATA
3-4
OC2
1-2
SUS_DN (FG)
(4mSec per/div)
The signal for these pins look very similar
due to the fact they are read from Chassis Gnd,
but they are actually Floating Ground related.
DO NOT hook scope Gnd to Floating Gnd TP
without an Isolation Transformer.
56
August 2010
42PJ350
Plasma
P211
Y-Scan
Signal
Y-Drive
Board
Y-SUS
Board
Red Lead on FG
Pin
Label
Run
Diode Check
Diode Check
17
SUS_DN (FG)
FG
FG
FG
15-16
FG5V
4.9V
1.97V
0.59V
13-14
SUS_DN (FG)
FG
FG
FG
11-12
YB_CLK
0.86V
1.36V
0.53V
9-10
YB_STB
2.8V
1.36V
0.53V
7-8
YTB_OC1
2.2V
1.45V
0.68V
5-6
YT_DATA
0V
1.36V
0.53V
3-4
YB_OC2
2.63V
1.46V
0.68V
1-2
SUS_DN (FG)
FG
FG
FG
Chassis
Ground
Red Lead
Black Lead
57
August 2010
42PJ350
Plasma
FG 15V
C519 (+ Side)
FG15V Source 23.6V
D506
18.24V
T502
FG 15V
Location
J393
OE
C520 (+ Side)
FG5V Source 10.9V
58
August 2010
42PJ350
Plasma
Location
D506
18.24V
T502
D506
18V Source
Cathode Right Side
Just to the right of T502
59
August 2010
42PJ350
Plasma
Locations
FS201 (M5V)
4V/125V
Diode Check 1.19V
With Board Disconnected. 0.65V
with board connected.
FS203
FS202 Protects VS
(VA)
10A/125V
FS202 (VS)
4V/250V
60
August 2010
42PJ350
Plasma
Label
Run
Diode Check
9~12
Gnd
Gnd
Gnd
n/c
n/c
Open
4~7
ER_PASS
133V
Open
n/c
n/c
Open
1~2
Vs
*206V
Open
P206
Label
Run
Diode Check
1~2
Vs
*206V
Open
n/c
n/c
n/c
4~5
Gnd
Gnd
Gnd
6~7
Va
*60V
Open
Gnd
Gnd
Gnd
9~10
M5V
5.25V
2.12V
c
P201
61
August 2010
42PJ350
Plasma
Label
Run
Diode Check
1~2
Gnd
Gnd
Gnd
n/c
n/c
n/c
4~5
*Va
*60V
Open
c
P209
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
62
August 2010
42PJ350
Plasma
Label
Run
Diode
Pin
Label
Run
Diode
+15V
18.24V
1.24V
16
DATA
0V
2.81V
+15V
18.24V
1.24V
17
ER_UP
0.26V
2.81V
+15V
18.24V
1.24V
18
BLK
1.40V
2.81V
+5V
5V
1.11V
19
SET_UP
0.24V
2.81V
+5V
5V
1.11V
20
STB
1.50V
2.81V
+5V
5V
1.11V
21
Dummy_5
1.05V
3.19V
+5V
5V
1.11V
22
CLK
0.59V
2.81V
Gnd
Gnd
Gnd
23
SUS_DN
2.75V
2.81V
Gnd
Gnd
Gnd
24
Dummy_3
1.97V
2.81V
10
Gnd
Gnd
Gnd
25
Dummy_1
1.04V
2.81V
11
Gnd
Gnd
Gnd
26
Dummy_4
1.23V
3.91V
12
Dummy_2
2.14V
2.80V
27
SUS_UP
0.05V
2.81V
13
Y_OE
0.02V
1.81V
28
CTL_OE
0.23V
3.19V
14
OC2
1.85V
2.81V
29
SET-DN
0.05V
2.81V
15
ER_DN
1.05V
2.81V
30
Gnd
Gnd
Gnd
63
August 2010
42PJ350
Plasma
64
August 2010
42PJ350
Plasma
Floating Ground
Floating Ground
Floating Ground
Floating Ground
Y-Scan Signal
P106
Logic (Scan Control
signals) and
Floating Ground 5V
65
August 2010
42PJ350
Plasma
Y-Drive Layout
PANEL
SIDE
Y-SUS
SIDE
Floating
Ground
Standoff
The Floating Ground
Standoffs deliver FG
to the Y-Drive Board.
There are 4 total.
VScan
The VScan
Standoff delivers the
VScan signal to the
Y-Drive Boards.
There is per/board.
P106
66
August 2010
42PJ350
Plasma
Y-SUS
SIDE
FL1
FG5V Fuse
Scan
Signal
TP
67
August 2010
42PJ350
Plasma
FRONT SIDE
Using the Diode Test on the DVM, check
the pins for shorts or abnormal loads.
BUFFER IC
(FGnd)
RED LEAD On
BLACK LEAD On ANY
Floating Ground
Output Lug Reads 0.80V
Indicated by white outline
BLACK LEAD On
RED LEAD On ANY
Floating Ground
Output Lug Reads Open
Indicated by white outline
68
August 2010
42PJ350
Plasma
Gently Pry
Up Here
Locking tab in
upright position
Fig 1
Fig 3
Fig 2
To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated
securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1).
69
August 2010
42PJ350
Plasma
70
August 2010
42PJ350
Plasma
P106
P211
Y-Scan
Signal
c
c
Y-Drive
Board
71
August 2010
Y-SUS
Board
42PJ350
Plasma
P106
P211
Y-Scan
Signal
P106 Connector
Pin
Label
SUS_DN (FG)
2-3
FG5V
4-5
SUS_DN (FG)
6-7
CLK
8-9
STB
10-11
OC1
12-13
DATA
14-15
OC2
16-17
SUS_DN (FG)
(4mSec per/div)
72
Y-Drive
Board
August 2010
Y-SUS
Board
42PJ350
Plasma
Y-Scan
Signal
Y-Drive
Board
Red Lead on FG
Pin
Label
Run
Diode Check
Diode Check
SUS_DN (FG)
FG
FG
FG
2-3
FG5V
4.9V
2.57V
0.53V
4-5
SUS_DN (FG)
FG
FG
FG
6-7
CLK
0.86V
Open
0.62V
8-9
STB
2.8V
Open
0.62V
10-11
OC1
2.2V
Open
0.62V
12-13
DATA
0V
3.28V
0.76V
14-15
OC2
2.63V
Open
0.62V
16-17
SUS_DN (FG)
FG
FG
FG
Red Lead
Black Lead
73
August 2010
42PJ350
Plasma
Z-SUS SECTION
This Section of the Presentation will cover troubleshooting the Z-SUS Board Assembly.
Upon completion of this section the Technician will have a better understanding of the circuit and be
able to locate voltage and diode mode test points needed for troubleshooting and all alignments.
Note: The Z-SUS can not be run Stand-Alone in the 42T1 Panel Models.
Locations
Operating Voltages
Power Supply Supplied VS
M5V Routed through Control Board
Y-SUS Supplied
Developed on Z-SUS
Z Bias
74
August 2010
42PJ350
Plasma
Y-SUS Board
18V
M5V
Control Board
VS and
ERR_COM
M5V
18V
Receives
Logic
Signals
Via 2 FPC
Flexible
Printed
Circuits
NO IPMs
PDP
Display
75
August 2010
Z-SUB
42PJ350
Panel
Plasma
P/N EBR63038801
P2
VS from Y-SUS.
Error Com to
the Y-SUS
No IPMs
Z-Bias TP
R151
Z-Bias
VR1
P1
from
Control
P4
Z-SUS
Output
FETs
No IPMs
Z-SUS
Waveform
Development
FETs
No IPMs
Z-SUS
Waveform
Test Point
J43
P3
M5V from SMPS to the Y-SUS generates +18V.
M5V and 18V are routed through the Control board.
Logic Signals generated on the Control board.
76
P3 To Z-SUB
August 2010
42PJ350
Plasma
P2
P4
Q201
Z-Bias
Waveform
J43
VZB TP
R151
D101
Q202
Q203
Z-SUS BOARD
p/n: EBR63038801
Q2
VR1
VZB
Q205
D103
Q206
Q3
P1
Q4
Q202
Q102
P3
77
August 2010
42PJ350
Plasma
Z-SUS Waveform
The Z-SUS (in combination with the Y-SUS) generates a SUSTAIN Signal and an ERASE PULSE
for generating SUSTAIN and DISCHARGE in the Panel.
This waveform is supplied to the panel through two FPC (Flexible Printed Circuit) connections
P4 and to the Z-SUB P3 to P2 and to P1.
Reset
Y Drive
Waveform
Oscilloscope Connection Point.
J43 to check Z Output waveform.
Right Hand Side Center.
Z Drive
Waveform
This Waveform is just for reference to observe the effects of Zbz adjustment
78
August 2010
42PJ350
Plasma
VZB (Z-Bias) TP
R151
LOCATION
VZB (Z Bias)
VR1
Set should run for 15 minutes, this is the Heat Run mode.
Set screen to White Wash mode or 100 IRE White input.
All SMPS adjustments should have been completed.
1. Place DC Volt meter between VZB TPs.
2. Adjust VZB (Z Bias) VR1 in accordance with your Panels voltage label.
79
August 2010
42PJ350
Plasma
Pin
Label
Run
Diode Check
1~2
+Vs
*205V
Open
n/c
n/c
n/c
4~5
ER_COM
98V~102V
Open
n/c
n/c
n/c
7~11
Gnd
Gnd
Gnd
Pin 1
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
80
August 2010
42PJ350
Plasma
Label
Run
Diode Check
Gnd
Gnd
Gnd
Y-OE
0.0V
Open
Z_BIAS
1.9V
2.82V
Gnd
Gnd
Gnd
ER_UP
0.1V
2.82V
ZSUS_DN
0.86V
2.82V
ZSUS_UP
0.15V
2.82V
Gnd
Gnd
Gnd
+5V
5V
Open
10
+5V
5V
Open
11
+15V
18.24V
1.9V
12
+15V
18.24V
1.9V
Pin 1
81
August 2010
42PJ350
Plasma
Signals
Main Board Supplied Panel Control and LVDS (Video) Signals
Control Board Generated Y-SUS and Z-SUS Drive Signals (Sustain)
X Board Drive Signals (RGB Address)
Operating Voltages
From the Y-SUS Supplied
August 2010
42PJ350
Plasma
p/n: EBR63632301
LVDS
To Z-SUS
P163
P121
P102
P101
IC121
VS_DA
For External Trigger
IC102
IC171
Pattern Generator
For Panel Test
D101 Should
be blinking
To Y-SUS
P161
P162
To X-Left
To X-Right
83
August 2010
42PJ350
Plasma
1~3 (16V)
4-7 (M5V)
Ribbon Cable
Y-SUS and Y Drive Signals
To Y-SUS
CONTROL BOARD
p/n: EBR63632301
n/c Upgrades
P163
P101
P102
P121
25Mhz
X103
IC121
(1) Gnd
(2) 3.3V
(3) 5.0V
IC121
D101 LED
P161
IC103
IC201
3.3V TP
IC171
Auto Gen
3.3V TP P162
84
18V generated by
D506 on Y-SUS
IC171
(1) Gnd
(2) 1.2V
(3) 3.3V
VS_DA
August 2010
42PJ350
Plasma
BACK SIDE OF
THE BOARD
IC151
04) 3.3V 03) Gnd
05) Gnd 02) Gnd
06) 3.3V 01) 3.3V
Pin 1
IC151
85
August 2010
42PJ350
Plasma
86
August 2010
42PJ350
Plasma
X103
CONTROL
BOARD
CRYSTAL
LOCATION
87
August 2010
42PJ350
Plasma
MCM
CONTROL BOARD
EEPROM
MCM
IC201
Resistor Array
16 bit words
To Left
X-Board
To 6 TCPs
2 Buffer
Outputs
per TCP
To Right
X-Board
To 6 TCPs
88
August 2010
X-DRIVE BOARD
PANEL
There are 12 total TCPs.
43072 Vertical Electrodes
43072 (RGB) / 3 =
1024 Total Pixels (H)
42PJ350
Plasma
Control Board Connector P101 to Y-SUS P101 Voltages and Diode Mode Checks
These pins are very close together. Use Caution when taking Voltage measurements.
Note: 18V is labeled 15V on silk screen.
Pins 1 through 3
Receive 18V from the Y-SUS.
Developed by D506
Pin c
Pins 4 through 7
Receive M5V from the Y-SUS.
Protected on Y-SUS by FS201
89
August 2010
42PJ350
Plasma
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
+15V
18.24V
Open
+15V
18.24V
Open
+15V
18.24V
Open
+5V
5V
1.47V
+5V
5V
1.47V
+5V
5V
1.47V
+5V
5V
1.47V
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
10
Gnd
Gnd
Gnd
11
Gnd
Gnd
Gnd
12
Dummy_2
2.14V
2.83V
13
Y-OE
0.02V
Open
14
OC2
1.85V
Open
15
ER_DN
1.05V
2.83V
16
DATA
0V
2.83V
17
ER_UP
0.26V
2.81V
18
BLK
1.4V
2.82V
19
SET_UP
0.24V
2.83V
20
STB
1.5V
2.82V
21
Dummy_5
1.05V
2.81V
22
CLK
0.59V
2.82V
23
SUS_DN
2.75V
2.82V
24
Dummy_3
1.97V
2.82V
25
Dummy_1
1.04V
2.81V
26
Dummy_4
1.23V
Open
27
SUS_UP
0.05V
2.82V
28
CTL_OE
0.23V
Open
29
SET_DN
2.10V
2.82V
30
Gnd
Gnd
Gnd
Pin c
P101
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
90
August 2010
42PJ350
Plasma
P121
LVDS
Video Signals from the Main Board to the Control Board are referred
to as Low Voltage Differential Signals or LVDS. The video is
delivered in 10 bit LVDS format. Their presence can be confirmed
with the Oscilloscope by monitoring the LVDS signals with SMPTE
Color Bar input. Loss of these Signals would confirm the failure is on
the Main Board or the LVDS Cable itself.
Example of LVDS Video Signal
LVDS
LVDS Removed
91
August 2010
42PJ350
Plasma
Label
Run
Diode
Check
Pin
Label
Run
Diode
Check
n/c
n/c
Gnd
16
n/c
n/c
Open
RA1N
1.13V
1.23V
17
n/c
n/c
Open
RA1P
1.37V
1.23V
18
n/c
n/c
Open
RB1N
1.18V
1.23V
19
Gnd
Gnd
Gnd
RB1P
1.31V
1.23V
20
n/c
n/c
Open
Gnd
Gnd
Gnd
21
n/c
n/c
Open
RC1N
1.27V
1.23V
22
CLK
0.59V
2.99V
RC1P
1.23V
1.23V
23
DATA
3.24V
2.99V
RCLK1N
1.29V
1.23V
24
RE1N
1.19V
1.23V
10
RCLK1P
1.26V
1.23V
25
RE1P
1.29V
1.23V
11
RD1N
1.23V
1.23V
26
Gnd
Gnd
Gnd
12
RD1P
1.31V
1.23V
27
DISP_EN
2.79V
Open
13
Gnd
Gnd
Gnd
28
Module_SDA1
3.29V
Open
14
Gnd
Gnd
Gnd
29
Module_SCL1
3.29V
Open
15
n/c
n/c
Open
30
n/c
n/c
Open
31
Gnd
Gnd
Gnd
1
Pin 27 is the reason the LVDS
cable must be removed to use the
EX_AUTO_GEN shorting pins to
create multiple internal generated
test patterns (Panel Test).
Enables the
Control Board
92
August 2010
42PJ350
Plasma
18V
Pin
Label
Run
Diode Check
Gnd
Gnd
Gnd
Y-OE
0.0V
Open
Dummy-1
1.9V
Open
CTL_OE
0.0V
Open
ER_UP
0.1V
Open
SUS_DN
0.86V
Open
SUS_UP
0.15V
Open
Gnd
Gnd
Gnd
+5V
5V
1.47V
10
+5V
5V
1.47V
11
+15V
18.24V
Open
12
+15V
18.24V
Open
5V
P102
Label
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
93
August 2010
42PJ350
Plasma
Label
Run
Diode Check
Pin
Label
Run
Diode Check
Gnd
Gnd
Gnd
26
A1_N_3
1.18V
1.31V
A2_P_0
1.12V
1.35V
27
Gnd
Gnd
Gnd
A2_N_0
1.18V
1.31V
28
A2_P_4
1.12V
1.35V
A1_P_0
1.12V
1.35V
29
A2_N_4
1.18V
1.31V
A1_N_0
1.18V
1.31V
30
A1_P_4
1.12V
1.35V
Gnd
Gnd
Gnd
31
A1_N_4
1.18V
1.31V
CLK_P_0
1.12V
1.35V
32
Gnd
Gnd
Gnd
CLK_N_0
1.18V
1.31V
33
CLK_P_2
1.12V
1.35V
Gnd
Gnd
Gnd
34
CLK_N_2
1.18V
1.31V
10
A2_P_1
1.12V
1.35V
35
Gnd
Gnd
Gnd
11
A2_N_1
1.18V
1.31V
36
A2_P_5
1.12V
1.35V
12
A1_P_1
1.12V
1.35V
37
A2_N_5
1.18V
1.31V
13
A1_N_1
1.18V
1.31V
38
A1_P_5
1.12V
1.35V
14
Gnd
Gnd
Gnd
39
A1_N_5
1.18V
1.31V
15
A2_P_2
1.12V
1.35V
40
Gnd
Gnd
Gnd
16
A2_N_2
1.18V
1.31V
41
3.3V
3.3V
0.64V
17
A1_P_2
1.12V
1.35V
42
3.3V
3.3V
0.64V
18
A1_N_2
1.18V
1.31V
43
3.3V
3.3V
0.64V
19
Gnd
Gnd
Gnd
44
Gnd
Gnd
Gnd
20
CLK_P_1
1.12V
1.35V
45
STB0
3.24V
Open
21
CLK_N_1
1.18V
1.31V
46
STB1
3.27V
Open
22
Gnd
Gnd
Gnd
47
X_BLK
3.24V
Open
23
A2_P_3
1.12V
1.35V
48
X_POL
1.86V
Open
24
A2_N_3
1.18V
1.31V
49
HTZ
0V
Open
25
A1_P_3
1.12V
1.35V
50
Gnd
Gnd
Gnd
94
41~43
3.3V
August 2010
White hash
marks count
as 5
42PJ350
Plasma
Label
Run
Diode Check
Pin
Label
Run
Diode Check
Gnd
Gnd
Gnd
26
A2_N_8
1.18V
1.31V
HTZ
0V
Open
27
A1_P_8
1.12V
1.35V
X_POL
1.86V
Open
28
A1_N_8
1.18V
1.31V
X_BLK
3.24V
Open
29
Gnd
Gnd
Gnd
STB2
3.24V
Open
30
CLK_P_4
1.12V
1.35V
STB3
3.27V
Open
31
CLK_N_4
1.18V
1.31V
Gnd
Gnd
Gnd
32
Gnd
Gnd
Gnd
3.3V
3.3V
0.64V
33
A2_P_9
1.12V
1.35V
3.3V
3.3V
0.64V
34
A2_N_9
1.18V
1.31V
10
3.3V
3.3V
0.64V
35
A1_P_9
1.12V
1.35V
11
Gnd
Gnd
Gnd
36
A1_N_9
1.18V
1.31V
12
A2_P_6
1.12V
1.35V
37
Gnd
Gnd
Gnd
13
A2_N_6
1.18V
1.31V
38
A2_P_10
1.12V
1.35V
14
A1_P_6
1.12V
1.35V
39
A2_N_10
1.18V
1.31V
15
A1_N_6
1.18V
1.31V
40
A1_P_10
1.12V
1.35V
16
Gnd
Gnd
Gnd
41
A1_N_10
1.18V
1.31V
17
CLK_P_3
1.12V
1.35V
42
Gnd
Gnd
Gnd
18
CLK_N_3
1.18V
1.31V
43
CLK_P_5
1.12V
1.35V
19
Gnd
Gnd
Gnd
44
CLK_N_5
1.18V
1.31V
20
A2_P_7
1.12V
1.35V
45
Gnd
Gnd
Gnd
21
A2_N_7
1.18V
1.31V
46
A2_P_11
1.12V
1.35V
22
A1_P_7
1.12V
1.35V
47
A2_N_11
1.18V
1.31V
23
A1_N_7
1.18V
1.31V
48
A1_P_11
1.12V
1.35V
24
Gnd
Gnd
Gnd
49
A1_N_11
1.18V
1.31V
25
A2_P_8
1.12V
1.35V
50
Gnd
Gnd
Gnd
95
August 2010
8~10
3.3V
White hash
marks count
as 5
42PJ350
Plasma
August 2010
42PJ350
Plasma
97
August 2010
42PJ350
Plasma
98
August 2010
42PJ350
Plasma
VA
Pins 4~7
VA
Pins 44~47
Gnd
On Gnd
On the below:
VA from Y-SUS
disconnected
from Left X board
99
TCP
On Gnd
On the below:
August 2010
42PJ350
Plasma
Y-SUS Board
Logic
X_B/D
Frame
Rear panel Vertical Address
Front panel Horizontal Address
256 Vertical
Electrodes
Va
Control Board
3.3V
ctor
Conne
TCP
Taped Carrier
Package
Chocolate
128 lines
Con
nect
or
Flex
ibl
Cabl e
e
TCP
Attached directly
to Flexible cable
Long Black
Heat Sink
100
August 2010
42PJ350
Plasma
TCP Testing
On any Gnd
Gnd
Reversed
On Va (0.59V)
On 3.3V (1.08V)
On Va (Open)
On 3.3V (Open)
Gnd
Va
On the below:
Gnd Va
3.3V
n/c
n/c
1
10
15
101
20
25
30
35
40
45
50
August 2010
42PJ350
Plasma
Gnd
5.0V
3.3V
3.3V
Control Board
P161 and P162
3.3V
102
August 2010
42PJ350
Plasma
TCP
Tapped
Carrier
Package
Look for burns, pin
holes, damage, etc.
103
August 2010
42PJ350
Plasma
Pin
Label
Run
Diode Check
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
n/c
n/a
n/a
VA
*60V
Open
VA
*60V
Open
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
104
August 2010
42PJ350
Plasma
P211, P232, P311 and P331 X Board Connector (VA Diode Check)
P232
3.3V 9~11
Va 4~5
P331
3.3V 42~44
Va 4~5
In
Out
1
P211 Left X
On Chassis Gnd
P311 Right X
105
On Chassis Gnd
On Va (0.52) Y-SUS connector
removed, TCPs connected.
On Va (Open) all connectors removed,
TCPs disconnected.
August 2010
42PJ350
Plasma
106
August 2010
42PJ350
Plasma
P703
LVDS
P301 to
SMPS
P802
Audio
Optical
Audio
USB
IC1
Microprocessor
Video Processor
PC
Audio
Remote
RS232
PC
HDMI
HDMI
RS232
RGB
RF
In
Rear
Inputs
107
August 2010
42PJ350
Plasma
C
C
A1 A2
P301
P703
IC308
D2
P704
IC201
IC202
To Ft IR
L313
IC1
L803
To SPK
IC801
All Pins
12.3V
C2
C1
L+
LR+
R-
P802
D1
L804
12Mhz
X1
Mstar
Micro/
Video
X402
25Mhz
MAIN BOARD
p/n: EBT60953602
X401
31.875Mhz
D501
IC401
C A2
A1
IC402
E B
C
C B
E B E
C
C
B E
A1
A2 C
D505
Q402 Q404
Q401 Q403
TUNER
C A2
D504
A1
108
August 2010
42PJ350
Plasma
IC202
7V (to IC405)
Pin
[1]
[2]
[3]
[4]
[5]
[6]
Q401
Regulator
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
Q402
[7] Gnd
[8] 3.3V
IC308
1.3V_VDDC
Pin Regulator
[1] Do not measure
[2] Gnd
[3] 5.04V
[4] 6.07V
[5] 4.99V
[6] 1.28V
[7] 1.28V
[8] 4.27V
Tuner CVBS
Pin
[B]
[E]
[C]
Q403
Use scope:
Pin 1: 1.4~1.7V P/P
Using DVM, set shuts off.
Use scope:
Pin 8: 600mV P/P
Using DVM, set shuts off.
Q404
Q502
Buffer (Analog)
1.19V
1.86V
Gnd
IF_P Buffer
Pin (Digital)
Pin
[1 B]
[2 S]
[3 D]
[4 G]
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
D501
D504
D1
B+ Routing
Pin
[A1]
[A]
[A2]
Reset
to IC502
0V
4.54V
5.0V
B+ Routing
Pin to IC504
[B] 1.18V
[E] 1.18V
Pin Speed Up
[A1] Gnd
[A1] 0V
[A] 4.54V
[C] Gnd
[A] 0V
[A2] Gnd
[A2] 5.0V
Tuner SIF
Pin Buffer (Digital)
D505
D2
LED-R
B+ Routing
Pin to IC503
[B] 1.32V
[E] 1.99V
Pin Routing
[A1] 0V
[A1] 0V
[A] 4.54V
[C] Gnd
[C] 0.13V
[A2] 0.28V
[A2] 5.0V
IF_N Buffer
Pin (Digital)
[B] 1.32V
[E] 1.99V
[C] Gnd
109
August 2010
42PJ350
Plasma
IC302
2
2 1E B
3
Q301
S G
D
Q703 IC501
Q302
C E
B
IC701
IC203
Q504
IC304
E B
IC303
Q303
S GE B
IC504
IC306
3
Q304
IC703
D502
MAIN BOARD
p/n: EBT60953602
A2
A1
Q501
E B
C
IC502
2
3
Q702
C E
B
Q503
E B
C
IC503
IC307
IC602
110
July 2010
42PJ350
Plasma
IC203
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
Winbond Serial
Flash
0V
3.30V
n/c
n/c
n/c
n/c
0V
3.3V
0V
Gnd
n/c
n/c
n/c
n/c
0V
0V
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.85V (Out)
3.3V (In)
IC303
Pin
[1]
[2]
[3]
IC304
IC501
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
Only on
[2] 1.2V (Out) with Dig
Channel
[3] 3.3V (In)
IC306
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
Gnd
3.3V (Out)
4.97V (In)
Pin
[1]
[2]
[3]
1.8V_TU
Regulator
Gnd
1.8V (Out)
3.3V (In)
IC307
IC301
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC502
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
4.52V
4.52V
3.33V
4.53V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
EEPROM
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
3.33V
5.09V
IC602
IC302
Pin
[1]
[2]
[3]
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
HDCP Data
EEPROM
Gnd
Gnd
3.3V
Gnd
3.3V
3.3V
3.3V
3.3V
IC701
Pin
[1]
[2]
[3]
[4]
[5]
[6]
IC703
Q301
3.3V
5.45V
0V
0V
(-5.37V)
(-5.4V)
(-5.4V)
0V
3.3V
3.3V
n/c
n/c
0V
5.45V
Gnd
3.3V (B+)
Q702
Pin
[B]
[C]
[E]
5V_MST
Switch
0V
5.09V
5.04V
D502
Pin
[G]
[S]
[D]
Q302
RS232 Tx/Rx
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
111
USB 5V
Limiter
4.97V (In)
Gnd
3.3V (Enable)
0V
0V
4.97V (Out)
Q303
Pin
[B]
[C]
[E]
RS232
Tx Buffer
0.6V
0V
Gnd
3.3V_PVSB Sw
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
Q304
Pin
[B]
[C]
[E]
Q501, Q503
Q504
Hot Swap
Pin Switch for HDMI
[B] 0V
[C] 0V
[E] Gnd
August 2010
42PJ350
Plasma
112
August 2010
42PJ350
Plasma
X1 12Mhz
X1
1.58V
1.49V
X402 25MHZ
X402
1.48V
1.6V
X401 31.875MHZ
X1
X401
MAIN Board
0.54V
0.66V
Crystal Location
Left Side 0.7V p/p
113
August 2010
42PJ350
Plasma
P301 or P703
114
August 2010
42PJ350
Plasma
115
August 2010
42PJ350
Plasma
1
P703 Main Board Connector to P121 "Control Board
Pin
Label
Run
Diode
Check
Pin
Label
Run
Diode
Check
n/c
n/c
Open
n/c
n/c
Open
ROM_RX
3.29V
2.6V
ROM_TX
3.29V
2.59V
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Module_SCL1
3.29V
2.6V
10
Module_SDA1
3.29V
2.6V
11
RE2+
1.29V
0.86V
12
RE2-
1.19V
0.86V
13
RD2+
1.31V
0.86V
14
RD2-
1.23V
0.86V
15
RCLK2+
1.26V
0.86V
16
RCLK2-
1.29V
0.86V
17
RC2+
1.23V
0.86V
18
RC2-
1.27V
0.86V
19
RB2+
1.31V
0.86V
20
RB2-
1.18V
0.86V
21
RA2+
1.37V
0.86V
22
RA2-
1.13V
0.86V
23
PC_SER_CLK
0.59V
1.02V
24
PC_SER_DATA
3.24V
1.52V
25
DISP_EN
2.79V
0.49V
26
Gnd
Gnd
Gnd
116
August 2010
42PJ350
Plasma
3&4
Soft Touch
Key Board
7&8
Intelligent
Sensor
Stand-By
3.3V
Pin
Label
STBY
Run
Diode
Check
IR
3.43V
4.9V
Open
Gnd
Gnd
Gnd
Gnd
Key_CTL_0
3.29V
3.29V
1.73V
Key_CTL_1
3.29V
3.29V
1.73V
LED_RED
2.72V
0V
Open
Gnd
Gnd
Gnd
Gnd
EYE_SCL
0V
3.29V
2.63V
EYE_SDA
0.23V
3.29V
2.63V
Gnd
Gnd
Gnd
Gnd
10
3.3VST
3.29V
3.29V
1.09V
11
3.3V_MST
0V
3.29V
0.55V
12
LED_BLUE
0V
0V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
117
August 2010
42PJ350
Plasma
Main Board Plug P301 to Power Supply Voltages and Diode Check
Pin c front
Label
STBY
Run
Diode Check
1_2
17V
0V
16.8V
Open
3-4
Gnd
Gnd
Gnd
Gnd
5-7
5V
0.47V
5.24V
0.94V
Error_Det
2.88V
4.93V
3.04V
9-12
Gnd
Gnd
Gnd
Gnd
13-14
STBY_5V
3.49V
5.23V
1.1V
0V
2.43V
2.52V
AC Det
0V
4.45V
2.93V
M_ON
0V
3.27V
Open
Auto_Gnd
Gnd
Gnd
Gnd
15
16
RL_ON
17
18
P301
a Note: The RL_On turns on +5V, 17V Error Det. and AC_DET.
b Note: The M5-On command turns on M5V, Va and Vs.
c Note: The Error Det line is not used in this model.
d Note: If the AC Det line is Missing, the TV will turn off in 10 Seconds.
e Note: Pin 18 is grounded on the Main. If opened, the power
supply turns on automatically.
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.
118
August 2010
42PJ350
Plasma
Pin
Label
SBY
Run
Diode Mode
R-
0V
8.39V
Open
R+
0V
8.39V
Open
L-
0V
8.39V
Open
L+
0V
8.39V
Open
IC801
Audio Amp
Left (+)
Left (-)
Right (+)
Right (-)
P802
Speaker
Connector
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.
119
August 2010
42PJ350
Plasma
FRONT IR, POWER LED and SOFT TOUCH KEY PAD SECTION
The following section gives detailed information about the Front IR and Soft
Touch Key Pad. These boards contains the Infrared Receiver, Intelligent
Sensor and Power LEDs section. The Soft Touch Function Keys is actually
a thin pad adhered to the front protective shield.
The Power LED Driver and Intelligent Sensor IC communicate with the Main
Board Microprocessor (IC1) via Clock and Data lines.
These boards have no adjustments.
The Front Control Board (IR and Intelligent Sensor) receives its operational
B+ from the Main Board:
3.3V_ST from the Main Board. This voltage is generated on the
Main Board (IC302)
3.3V_MST generated on the Main Board (IC303).
The Intelligent Sensor sends its data from the IR board to the Video
Processor by 2 separate pins from the Main board SCL/SDA pins 7 and 8.
The IR signal is routed back to the Main Board via pin 1.
Also, the Soft Touch Key Pad is routed through the Front IR board and
out P100 to P704 pins 3 and 4.
120
August 2010
42PJ350
Plasma
Front Control (IR and Intelligent Sensor) Board and Power LED Board Location
Lower Left Side (As viewed from rear).
Front IR Board
P100
To Main
P101
To Soft Touch
Key Board
Soft Touch
Key Pad
121
August 2010
42PJ350
Plasma
7&8
Front LEDs
and
Intelligent
Sensor
Stand-By
3.3V
Pin
Label
STBY
Run
Diode Check
IR
3.43V
4.9V
Open
Gnd
Gnd
Gnd
Gnd
Key_CTL_0
3.29V
3.29V
2.52V
Key_CTL_1
3.29V
3.29V
2.52V
LED_RED
2.72V
0.0V
3.13V
Gnd
Gnd
Gnd
Gnd
EYE_SCL
0V
3.29V
2.22V
EYE_SDA
0.23V
3.29V
2.21V
Gnd
Gnd
Gnd
Gnd
10
3.3VST
3.29V
3.29V
2.17V
11
3.3V_MST
0V
3.29V
2.25V
12
LED_BLUE
0V
0V
Open
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
122
August 2010
42PJ350
Plasma
Front IR Board Plug P101 to Soft Touch Keys (Voltages and Pin Identification)
Voltage and Diode Mode Measurements for the Main Board
STBY
Run
Diode Check
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
123
August 2010
42PJ350
Plasma
IC100
static sensitive
key press
decoder
c
Button Identification for the Front the static sensitive key pad
124
August 2010
42PJ350
Plasma
Plastic Frame
Lifted up slightly
P101
Ribbon Cable
Soft Touch
Key Pad
125
August 2010
42PJ350
Plasma
P100 (Key 1, Key 2) Resistance Reading with Soft Touch Key pressed.
KEY
Pin 3 measured
from Gnd
KEY
Pin 4 measured
from Gnd
CH (Up)
0.61K Ohms
Volume (+)
3.6K Ohms
CH (Dn)
9K Ohms
Volume (-)
0.62K Ohms
Input
3.66K Ohms
Enter
22K Ohms
Menu
9K Ohms
Pin 3 measured
from Gnd
KEY
Pin 4 measured
from Gnd
CH (Up)
2.1V
Volume (+)
0.89V
CH (Dn)
1.619V
Volume (-)
0.214V
Input
0.88V
Enter
2.42V
Menu
1.667V
P100 Connector IR/LED Control Board to P703 Main (No Key Pressed)
Diode Mode
Readings taken with
all connectors
Disconnected. Black
lead on Gnd. DVM
in Diode Mode.
Pin
Label
STBY
Run
Diode Mode
KEY 1
3.29V
3.29V
2.58V
KEY 2
3.29V
3.29V
1.58V
126
August 2010
42PJ350
Plasma
p/n: EAB60962801
Installed View
Reading
across speaker
wires, 8.2 ohm.
Cone View
127
August 2010
42PJ350
Plasma
128
August 2010
42PJ350
Plasma
540V p/p
Y-DRIVE BOARD
p/n: EBR63633601
155Vpp 5V
1
0V
(B) VR401
Set-Dn
IC101
100V
100uS
540V p/p
IC102
FS201 M5V
FS203 VA
FS202 VS
D21
Y Drive
TP
M217
Y-SUS BOARD
p/n: EBR63038301
P202
IC703
D33
Q22
Q16
IC103
P206
Q33
FG
IC701
D713
M216
P201
Q31
Q13
Q12
Q41
Q11
FG
VR501
VSC
VSC
TP
P204
M214
-VY
VR501
VSC
SCAN TP
M213
Q501
D503
P106
P205
IC107
VR401
VR401
Set-Dn
FS203
IC401 125V
Q503 Labeled +15V
10A (VA)
T501
D513
15V FG
J18
IC301 IC502
C519
IC510
FG 15V
IC303
IC202 D508
D506
C520
FG 5V
D509
J393
IC509
IC201
P211
-Vy
TP
Meters 18V
C213
T502
Open
n/c
n/c
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
VR502
D716
J461
IC501
0V
*60V
Open
Va
0V
*60V
Open
Gnd
Va
Gnd
Gnd
Gnd
M5V
0V
5.25V
2.12V
STBY
2.6V
0
0
.23V
12.26V
13.81V
14.06V
160.6V
160.6V
160.6V
56.2V
56.2V
57.0V
1.3V
0
P101
IC103
OE TP
VR502
-Vy
J11
IC102
VS ADJ
Q902
VS
F801
4A 250V
D801
Q901
Q801
2.6V STBY
390V Run
VA ADJ
Q504
Q802
Run
390.0V
192.0V
6.16V
195.0V
15.6V
21.8V
22.58V
467.0V
389.9V
389.9V
62.6V
62.9V
62.7V
56.8V
205.0V
VA
D807
D802
Q501
POWER SUPPLY
p/n: EAY60912401
D307
Q602
Q601
D601
D609
Q355
Q351
17V
T301
D305
IC701
Q356
D308
D309
D302
Q351
(STBY 5V)
D102
D306
Q603
At Power Off
3sec 1st Relay click
4sec 2nd Relay click
M5V
D303
IC301
L691
F101
10A 250V
RL103
D301
L602
CN701
n/c
P813
RL101
D101
SC101
AC In
PANEL TEST:
Remove LVDS Cable.
Short across Auto Gen
TPs to generate a test
pattern.
From M5V
T502 Driver IC509
18V D506
*FG 5V D509 or C520
*FG 15V D508 or C519
From VS
T501 Driver IC501
Control Board
-VY D502
p/n: EBR63632301
VSC D503 to Q501
*NOTE: J393 must be grounded when
testing these with only M5V supplied to
P101
the PWB.
Ribbon Cable
Y-SUS and Y Drive Signals
25Mhz
X103
VS_DA
IC171
(1) Gnd
(2) 1.2V
(3) 3.3V
IC108
P206
WARNING:
Remove the Y-DRIVE
Board completely if P211
or P106 is removed.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Label
SUS_DN (FG)
SUS_DN (FG)
OC2
OC2
DATA
DATA
OC1
OC1
STB
STB
CLK
CLK
SUS_DN (FG)
SUS_DN (FG)
FG5V
FG5V
SUS_DN (FG)
Red Lead on FG
Run Diode Check Diode Check
FG
FG
FG
FG
FG
FG
2.63V
1.46V
0.68V
2.63V
1.45V
0.68V
0V
1.36V
0.53V
0V
1.36V
0.55V
2.2V
1.45V
0.68V
2.2V
1.45V
0.68V
2.8V
1.36V
0.53V
2.8V
1.36V
0.66V
0.86V
1.36V
0.53V
0.86V
1.36V
0.53V
FG
FG
FG
FG
FG
FG
4.9V
1.97V
0.59V
4.9V
1.96V
0.56V
FG
FG
FG
Pin
1,2
3
4,5
P201
P202
Pin
1,2
3
4,5
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Label
+15V
+15V
+5V
+5V
Gnd
Gnd
Y-OE
ER_DN
ER_UP
SET_UP
Dummy_5
SUS_DN
Dummy_1
SUS_UP
SET_DN
P233
X-Board Left
p/n: EBR63628801
P203
P204
Pin
1,2
3
4,5
P205
P206
P232
P232
3.3V in
on Pins
9, 10, 11
P1
Q205
D103
Q206
Q3
Q4
IC202
P703
2
IC203
12Mhz
X1
C2
C1
IC501
B EG S
C D
MAIN BOARD
p/n: EBT60953602
Q304
2
3
X401
31.875Mhz
IC502
C
P100
P311
P301
B E
C
Pin
1,2
3
4,5
IC401
Q501
A2 B E
C
A1
IC402
Q402 Q404
Q401 Q403
E B C A1
C
E B B E A2
C
C
B E
Q503
D505
IC504
IC306
2
3
E C
B
Q504
B E
TUNER
Q702
P101
IC307
IC602
P100 "IR Board" to "Main" P704
Ft Key Pad
P331
P331
3.3V in
on Pins
42, 43, 44
A2
IC701
L313
IC503 A1D501
D504
Ft IR
Q703
X402
25Mhz
IC304
A1 A2
C
To Speakers
All Pins 8.39V
Diode: (Open)
P1
Q303
IC703
Z Sub BOARD
p/n: EBR63634601
IC308
E C
B
IC1
Mstar
Micro/
Video
P2
Pin
Label
Run Diode Check
7 ZSUS_UP 0.15V
2.82V
8
Gnd
Gnd
Gnd
9
(+5V)
5V
Open
10
(+5V)
5V
Open
11
(+15V)
18.24V
1.9V
12
(+15V)
18.24V
1.9V
IC301
1 3
Q302
IC801
P3
Q202
Q102
D2
D1
J43
Q203
Q2
VR1
VZB
L804
D502
P211
VR1
P4
Q202
Z-SUS BOARD
p/n: EBR63038801
IC201
P802
Auto Gen
3.3V TP
P162
Pin
Label
1
Gnd
2
Y-OE
3 Dummy-1
4
CTL_OE
5
ER_UP
6 ZSUS_DN
7 ZSUS_UP
8
Gnd
9
(+5V)
10
(+5V)
11
(+15V)
12
(+15V)
Pin
Label
Run Diode Check
2
+15V
18.24V
1.14V
4
+5V
5V
1.11V
6
+5V
5V
1.11V
8
Gnd
Gnd
Gnd
10
Gnd
Gnd
Gnd
12 Dummy_2 2.14V
2.80V
14
OC2
1.85V
2.81V
16
DATA
0V
2.81V
18
BLK
1.4V
2.81V
20
STB
1.5V
2.81V
22
CLK
0.59V
2.81V
24 Dummy_3 1.97V
2.81V
26 Dummy_4 1.23V
3.19V
28 CTL_OE
0.23V
3.18V
30
Gnd
Gnd
Gnd
D101
IC303
To SPK
P209 Y-SUS
C 3
G S
P704
VZB TP
R151
C
C
A1 A2
B E1 2
242V p/p
Z-Bias
Waveform
J43
L803
IC171
P161
P301
Q301
IC302
200uS
Q201
LVDS
To SMPS
50V
P2
IC103
IC201
Diode
Open
Gnd
1.29V
2.96V
Gnd
2.43V
Open
2.95V
Open
2.34V
P102
P121
To Ft IR
IC121
IC121
TCP/Cntl 3.3V Reg
(1) Gnd
(2) 3.3V D101
(3) 5V
LED
P209
D904
L+
LR+
R-
IC106
D502
*206V
n/c
FS202
125V
4A
(VS) FS203 Open with all
VR601
connectors connected.
VR601
Set-UP
M215
IC105
0V
n/c
IC601
P203
Vs
IC702
IC104
Open
Loc
*D601
*D801
*D802
* Note: Voltages taken *D807
*D307
from HOT GND.
*D609
*D303
*D305
*D308
*D309
*D306
*D302
*D301
*D102
D904
D712
D31
Diode Check
*206V
FS201
125V
4A (M5V)
Q21
Q15
Run
0V
10
M5V
0V
5.25V
2.12V
* Note: This voltage will vary by Panel label
STBY
Vs
170uSec 5uSec
P201
Label
*Vzb
110V
Pin Label
Run Diode Check * Note: This voltage will vary in
accordance with Panel Label
1~2
+Vs
*205V
Open
3
n/c
n/c
n/c
4~7 ER_COM *133V
Open
6
n/c
n/c
n/c
9~12 Gnd
Gnd
Gnd
P811
100V
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Label
IR
Gnd
Key_CTL_0
Key_CTL_1
LED_RED
Gnd
EYE_SCL
EYE_SDA
Gnd
3.3VST
3.3V_MST
LED_BLUE
P302
STBY
3.43V
Gnd
3.29V
3.29V
2.72V
Gnd
0V
0.23V
Gnd
3.29V
0V
0V
0.07
0.07
0.07
0.07
0.07
0.07
0.07
0.07
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
2.4V
2.4V
2.4V
2.4V
2.4V
2.4V
2.4V
2.4V
Stand-By
Waveform No
No 12
No 13
No 14
No 15
No 16
No 17
No 18
No 19
TCP IC Diagram
Run
Waveform No.
No 0
No 1
No 2
No 3
No 4
No 5
No 6
No 7
TCP TESTING
X-Board Right
p/n: EBR63628701
P303
P304
TCP INSTALLED
Red Lead on TCP VA Open
Black Lead on TCP VA 0.52V
Red Lead on TCP 3.3V 0.6V
Black Lead on TCP 3.3V 0.39V
P305
P306
7V (to IC405)
Regulator
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
Gnd
3.3V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.3V_VDDC
Regulator
Do not measure
Gnd
5.04V
6.07V
4.99V
1.28V
1.28V
4.27V
IC308
Q401
Pin
[B]
[E]
[C]
Tuner CVBS
Buffer (Analog)
1.19V
1.86V
Gnd
Pin
[B]
[E]
[C]
IF_P Buffer
(Digital)
1.18V
1.18V
Gnd
Pin
[B]
[E]
[C]
Tuner SIF
Buffer (Digital)
1.32V
1.99V
Gnd
Pin
[B]
[E]
[C]
IF_N Buffer
(Digital)
1.32V
1.99V
Gnd
Q402
Use scope:
Pin 1: 1.4~1.7V P/P
Using DVM, set
shuts off.
Q403
Q404
Use scope:
Pin 8: 600mV P/P
Using DVM, set
shuts off.
Q502
Pin
[1 B]
[2 S]
[3 D]
[4 G]
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
Pin
[A1]
[A]
[A2]
Reset
Speed Up
Gnd
0V
Gnd
Pin
[A1]
[C]
[A2]
LED-R
Routing
0V
0.13V
0.28V
D501
Pin
[A1]
[A]
[A2]
B+ Routing
to IC502
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC504
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC503
0V
4.54V
5.0V
D504
D1
D505
D2
Winbond Serial
Flash
0V
3.30V
n/c
n/c
n/c
n/c
0V
3.3V
0V
Gnd
n/c
n/c
n/c
n/c
0V
0V
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.85V (Out)
3.3V (In)
IC303
Pin
[1]
[2]
[3]
IC304
IC501
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
Only on
[2] 1.2V (Out) with Dig
Channel
[3] 3.3V (In)
IC306
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
Gnd
3.3V (Out)
4.97V (In)
Pin
[1]
[2]
[3]
1.8V_TU
Regulator
Gnd
1.8V (Out)
3.3V (In)
IC307
IC301
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC502
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
4.52V
4.52V
3.33V
4.53V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
EEPROM
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
3.33V
5.09V
IC602
IC302
Pin
[1]
[2]
[3]
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
HDCP Data
EEPROM
Gnd
Gnd
3.3V
Gnd
3.3V
3.3V
3.3V
3.3V
IC701
Pin
[1]
[2]
[3]
[4]
[5]
[6]
IC703
USB 5V
Q301
Limiter
4.97V (In)
Gnd
3.3V (Enable)
0V
0V
Q302
4.97V (Out)
RS232 Tx/Rx
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
3.3V
5.45V
0V
0V
(-5.37V)
(-5.4V)
(-5.4V)
0V
3.3V
3.3V
n/c
n/c
0V
5.45V
Gnd
3.3V (B+)
Q303
Q702
Pin
[B]
[C]
[E]
5V_MST
Switch
0V
5.09V
5.04V
D502
Pin
[G]
[S]
[D]
3.3V_PVSB Sw
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
Q304
Pin
[B]
[C]
[E]
Q501, Q503
Q504
Pin
[B]
[C]
[E]
Hot Swap
Switch for HDMI
0V
0V
Gnd
Pin
[B]
[C]
[E]
RS232
Tx Buffer
0.6V
0V
Gnd
42PJ350 LVDS
Video Waveforms
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
15 and 16
are the Video Clock and
Data lines
End of Presentation
132
August 2010
42PJ350
Plasma