EE-423: Embedded Systems Design

Combinational Logic Design

Awais M. Kamboh

Slide 1

Single-purpose processors
A custom single-purpose processor is
Fast
Low power
Small size

But,
Large Design Time, time-to-market
High NRE Cost,
No Flexibility

Awais M. Kamboh

Slide 2

CMOS transistor on silicon

Transistor
The basic electrical component in digital systems
Acts as an on/off switch
Voltage at gate controls whether current flows from
source to drain
Dont confuse this gate with a logic gate
gate
1
IC package

IC

source

gate
oxide
channel

source
Conducts
if gate=1
drain

drain
Silicon substrate

Awais M. Kamboh

Slide 3

CMOS transistor implementations

Complementary Metal Oxide
Semiconductor
We refer to logic levels

drain
gate

Typically 0 is 0V, 1 is 5V

Conducts
if gate=1
source

nMOS
Two basic CMOS types
nMOS conducts if gate=1
pMOS conducts if gate=0
Hence complementary

source
gate

Conducts
if gate=0
drain

pMOS

Awais M. Kamboh

Slide 4

CMOS transistor implementations

Basic gates

Inverter
1

F = x'

Awais M. Kamboh

Slide 5

CMOS transistor implementations

Basic gates
NAND
NOR
1

x
x
y

y
F = (xy)'

F = (x+y)'
x
0
NAND gate

Awais M. Kamboh

x
y
y
0
NOR gate

Slide 6

CMOS transistor implementations

Activity
CMOS Implementation of AND gate

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Slide 7

CMOS transistor implementations

Solution to Activity
CMOS Implementation of AND gate

Awais M. Kamboh

Slide 8

Basic logic gates

Awais M. Kamboh

Slide 9

Combinational Logic Design

B) Truth table

A) Problem description
y is 1 if
a is 1,
or b and c are 1.
z is 1 if
b or c is 1, but not both,
or if all are 1.
C) Output equations
y = a'bc + ab'c' + ab'c + abc' + abc

z = a'b'c + a'bc' + ab'c + abc' + abc

Awais M. Kamboh

Outputs

Inputs
a

Slide 10

Combinational Logic Design

D) Minimized output equations

y

E) Logic Gates

bc

a
0
1

00

01

11

10

b
c

y = a + bc
z

bc

00

01

11

10

z = ab + bc + bc

Awais M. Kamboh

Slide 11

Combinational Components
I(m-1) I1 I0
n

S0
n-bit, m x 1
Multiplexor
S(log m)
n
O

O=
I0 if S=0..00
I1 if S=0..01

I(m-1) if S=1..11

MUX

I(log n -1) I0

B
n

A
n

n-bit
Adder

O(n-1) O1 O0

carry sum

less equal greater

O0 =1 if I=0..00
O1 =1 if I=0..01

O(n-1) =1 if I=1..11

sum = A+B
(first n bits)
carry = (n+1)th
bit of A+B

less = 1 if A<B
equal =1 if A=B
greater=1 if A>B

Decoder

n-bit
Comparator

Adder
With carry-in input Ci
sum = A + B + Ci

log n x n
Decoder

With enable input e

all Os are 0 if e=0

Awais M. Kamboh

Comparator

B
n

n bit,
m function S0
ALU

S(log
m)
n
O

O = A op B
op determined
by S.

ALU
May have status outputs
carry, zero, etc.
Commonly, Add, Sub,
Mul, AND, XOR etc

Slide 12

EE-430: Embedded Systems Design

Sequential Logic Design

Awais M. Kamboh

Slide 13

Sequential Components

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Slide 14

Sequential logic design

Example
Design a 3-bit counter that counts the following sequence: 1, 2, 4,
5, 7, 1, 2, etc. This counter has an output odd whose value is
1 when current count value is odd.
Start from a state diagram, draw the state table, minimize the
logic, and draw the final circuit.

Awais M. Kamboh

Slide 15

Sequential logic design

State Diagram

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Slide 16

Sequential logic design

State Table

odd

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Slide 17

Sequential logic design

Given this implementation model
Sequential logic design quickly reduces to combinational logic design

Awais M. Kamboh

Slide 18

Sequential logic design

Logic Circuit

odd
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Slide 19

Sequential logic design

Block Diagram

Awais M. Kamboh

Slide 20