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Time Interleaved Adcs
Time Interleaved Adcs
I. I NTRODUCTION
Parallel processing of ADCs leads to performance gains by
exploiting efficient arrays of reduced speed quantizers that
operate on sub-sections of the signal, partitioned usually in
time [1], [2] or perhaps in frequency [3][5]. Interleaving in
the time-domain, Fig. 1, is more widely used as frequency subbanding approaches require precise knowledge of channelizing
filter transfer functions and therefore more computationally
intensive reconstruction and calibration.
Whether paralyzation is implemented in the time- or frequency domain, the very nature of interleaving forces the
input signal to branch and traverse multiple paths on its
way to the output. Physically distinct circuits process various
sub sections of the signal: any mismatch results in patterndependent artifacts. Sources of errors and their impact on the
combined output of parallel ADCs have been analyzed and
described as early as the 1980s [6], [7], further into the 1990s
[8], [9], and more recently by several authors [10][15].
Often the goal of proposed calibration techniques are ambitious with aims to provide workable solutions for virtually
all classes of input signals. With mixed-signal SoCs being
more common due to ever increasing integration, rarely are we
concerned with general applications, but need only concentrate
on the specific. The two most common embedded applications
for time-interleaved ADCs are: 1) channelization of multichannel frequency division multiplexed signals such as in
cable and satellite TV and 2) baseband applications for optical
and backplane transceivers. The first is best understood by
viewing signals and errors in the frequency domain, while
the second is easiest to understand in the time domain. This
paper will focus on the requirements and impact of error
sources on ADCs for the first class of applications, broadband
frequency channelization. Error sources will be revisited in the
context of their sensitivity to overall system performance for
ADC
DADC1
Clk1
VIN
ADC
DADC 2
Clk2
ADC
Calibration
DADC3
Clk3
ADC
DADC 4
Clk4
THA
tilt
1
ADC
THA
ACI
ADC
THA
+
-
Frequency
Fm
Fs /2
12
ADC
THA
Calibration
Amplitude
Digital
THA
ADC
THA
ADC
ADC
90o Delay
IQ PLL
ADC
IQ PLL
Digital
90o Delay
ADC
ADC
IQ PLL
N
1
ADC
90o Delay
Fundamental
Single-Slice
Distortion
Time Interleaving
Noise
Smooth INL
Offsets
INL
probability
Quantization
Fs/4
Radix errors
VPP
Fs/2
probability
Fs/2
Fs/4
Cap Mismatch
Time-Skew
Fs/2
Fs/4
Stage
#1
D1
Stage
#2
Gain
Stage
#3
D2
D3
Stage
#4
D4
D
D
D4
x = D1 + 2 + 3 +
A1 A2 A1 A3 A2 A1
Rare occurrence.
Clipping
error
INL
VPP
Clipping
error
Squared error
INL2
VPP
Weighted
squared
error
significant
clipping
occurs
Weighted
squared
error
Signal
Probability
Fig. 10. For an ideal ADC there is no error in the operating range. As the
signal clips, the error is equal to the difference of the signal value and the
clipped value.
VPP
Clipping
Distortion
Vpp RMS
Total Noise
1
p
2
errsq ( ) =
(1)
c(x)2 e
1
2
(x
) dx
Gaussian
Squared
INL
Fig. 11. Changing the back-off impacts the total error due to clipping. The
higher the noise floor the larger the signal needs to be before the distortion
equals the integrated noise.
44
42
24
8.3-bit
Front-End Noise
38
04
83
36
63
7.3-bit
Front-End Noise
34
32
43
)Bd( RNS
cos (2fn t)
(2)
kbo 128 n
Vpp
RMS
40
D. Optimal Back-off
23
30
6.3-bit
Front-End Noise
28
515
1
414
1
313
1
212
1
111
1
010
1
99
)Bd( elacSlluF ot tcepser htiw ffokcaB
03
82
62
88
Fig. 12. For low amplitude signals increasing amplitude increases the SNR
one dB per dB until clipping dominates and SNR falls abruptly. The optimal
back-off depends on the level of additive noise.
INL
INL2
Total integrated
distortion ratio
improves 1dB per dB
for broadband
Fig. 13. INL errors for compressive distortion with overlay of Gaussian and
single-tone probabilities.
0.03
Errors Due to
LNA Distortion
= 7.67-bits
Probability Error2
0.025
0.02
0.015
0.01
0.005
0
1.5
Errors Due to
Clipping with
Broadband signal
At 11-dB Backoff
=7.8 bits
Errors Due to
Clipping with
Broadband signal
At 11-dB Backoff
= 7.8 bits
0.5
0
0.5
Normalized Input Signal
1.5
Fig. 14. The optimal back-off level must include the static distortion. This
method allows calculation of overal system sensitivity to distortion.
Integrating the squared error over a full sine wave period, the
SNR is found to be
1
= 2fin trms
(5)
SNR
Because the error of a single tone is proportional to the signal
slope and therefore proportional to the input frequency, lower
frequencies have lower time skew errors. Finding the overall
noise in general requires taking the derivative of the complete
spectrum. This can be approximated quite accurately assuming
a flat spectrum. Because the noise adds in an rms fashion
however, the integration of squares involves a factor of 1/3
in squared noise. Therefore, its not surprising that the total
broadband
noise relative to the maximum frequency is reduced
VIN
H. Offsets
noffset
= nnoise + nmargin +
1
6.02 10 log
fs /2
fBW
1
6.02 10 log
N
slice
(8)
bits
(9)
ADC
ADC
Clk2
DADC 4
DADC1
Clk1
ADC
ADC
Clk4
DADC3
Calibration
If the total energy from all offset errors is split equally between
Nslice /2 bins then the rms offset tone, which falls in one
of the desired channels needs to be smaller than the in-band
noise. If a margin of 2nmargin is assumed to avoid the offset
error dominating the SNR, then the accuracy of the offset
correction needs to be significantly better than the resolution of
broadband noise. The offset accuracy required is given below
in bits.
DADC 2
Calibration
Clk3
ClkFs
VI
Stage
#1
TH
Stage
#2
D1
Stage
#3
Stage
#4
D3
D2
D4
x! = G y(D1 , D2 , D3 , D4 ) +Voff
8
Radix and Cap
mismatch correction
LMS Calibration
SLOW
ADC
TH
24
Digital
Tuners
Memory#
LNA##
AGC&#
2.7
GS/s
12-b
ADC
LNA
Channelizers#1:12#
LOWPASS
FILTER
PGA#
HIGH
SPEED
INTERFACE
DDFS
Tx
Tx
LOWPASS
Calibration#FILTER
BUF
XTAL
OSC
FFT#Processor#
PLL
SERIAL
INTERFACE
PLL#
&#
CLK#
Gen#
Channelizers#13:24#
Serial#Output#
Fig. 17. Layout of a 2.5GS/s 12-bit ADC with 71dB SFDR through the first
Nyquist zone and 60dB through the 3rd Nyquist zone.
Amp
-10
Nyquist
Zone 1
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
Amplitude dBFS
-20
-30
SFDR 75dBc
-40
-50
-60
-70
3rd
-80
-90
-100
0
200
400
600
800
1000
1200
Frequency (MHz)
Fig. 18. Measured frequency response with an 8k-sample FFT for an input
in the first Nyquist zone, fin = 252-MHz and fs =2.525GS/s.
turn adjusts the edge position of eight capacitive clock-delayDACs, thus closing time-skew correction in the analog domain.
RMS
LNA
PGA
ADC
Radix
NonLinear
MDAC
CapMismatch
LUT
Mean &
Zero
Crossing
d/dt
T
Time Skew
Adjustment
Course Skew
500-1000fs
XTAL
OSC
PLL