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design
ideas
microcontroller you select has a builtin A/D converter, response time can decrease by a couple of orders of magnitude with the elimination of the input-filtering network. Op-amp selec-
tion is important if you use a singlesupply topology. An operational amplifier that can maintain stability close to
its negative, or ground, rail is an important asset.
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design
ideas
M1
FDS7788
RS
0.006
12VIN
R1
100
D1
5.1V
C2
100 nF
12VOUT
R3
1k
Q1B
R2
100
Q1A
FFB2227A
360 mV
Figure 5
Figure 4
IN
ON
This hot-swap
controller has
fast limiting of
short-circuitcurrent peaks.
CSPD
SENSE
GATE
MAX4272ESA
GND
NC
STAT
POR
CTIM
C1
22 nF
but at diminished amplitudes. The simple circuit in Figure 1 makes the switching converter operate over multiple frequencies rather than one, thereby
reducing the time average at any one frequency. This scheme effectively lowers
the peak emissions.
The circuit in Figure 1 is a self-starting
oscillator with an oscillation frequency of
approximately 500 Hz. When you apply
power, C3 begins to charge up from 0V,
and the output of the TL331 comparator
is in a high-impedance state because its
noninverting input sees a higher voltage
than that of the inverting input. As C3
charges, its voltage crosses the voltage reference of the R1-R6 divider, and the com-
design
ideas
5V BIAS
C1
0.1 F
R3
10k
5
4
TL331DBV
R1
10k
R2
49.9k
1
IC1
C2
1 F
RT
13.7k
R4
24.9k
IC1
UCC3813
1
2
COMP
REF
FB
VCC
8
7
3
6
Capacitor C2 ac-couples the ramp
2
R5
CS
OUT
4
5
6.04k
voltage of C3 into the UCC3813s oscilRC
GND
lator pin. The injected signal adds to the
CT
C3
R6
330 pF
4.99k
0.1 F
charging current of CT during its positive portion (ac signal), thus increasing
the controllers operating frequency.
During the injected signals
Figure 1
negative portion, some of CTs
A low-frequency oscillator ramp, injected into the RC pin, modulates the supplys switchcharging current disappears, slowing ing frequency.
the controllers operating frequency.
Figure 2 shows the effects of the inject- the frequency-sweep rate.
the circuit below the power converters
The differential EMI-current measure- low-frequency limits, or saturation of
ed signal on the charging of CT. R4 controls the magnitude of the current that ment of Figure 3 (1 dBV1 dBA) magnetics may occur. This circuit demonis injected. Reducing R4s value increas- shows the before-and-after effects of strates a low-cost, small-area approach to
es the range, or spread, of the operat- adding the frequency-shifting oscillator. reducing conducted-EMI emissions.
ing frequency around its nominal fixed This design easily achieves a 10frequency. The injected signals oscilla- dBA reduction with a 12-kHz
tion frequency, which C3 sets, controls sweep window. A wider window further reduces EMI, but
1
1 SEC
the modulator frequency may
0.50V
be noticeable in the converters
10115 SWPS
output ripple voltage. It is also
desirable to make the injected
ramp voltage as linear in shape
as possible to prevent the
switching converter from
1 SEC BWL
spending excess time at its
1 50 mV DC
2 50 mV DC
switching-frequency limits. The
200 mSAMPLES/SEC
3 0.1V DC
STOPPED
nonlinearity can result in an
1 DC 1.39V
4 0.5V DC
EMI response with two
Figure 2
Figure 3
distinct frequencies. You
The external oscillator varies
The EMI of the flyback converter
must take care not to operate differs with and without external modulation.
the charging of the timing capacitor.
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design
ideas
of 65V. In this case, VIN14V (nominal),
so you need VOUT to be 24V (nominal).
First, calculate a value for R2, thus establishing the reference current. If you select
a reference current of 1 mA, you obtain
ditions. The circuit maintains a 10V difference between VIN and VOUT, but you
can easily change it to provide other voltages. The PWM circuit in Figure 1 is the
CS5171 from On Semiconductor (www.
onsemi.com), but you can use the idea
with any boost circuit. The current-mirror circuit, comprising the dual-pnp
transistor, Q1, and the associated resistors, establishes a current that depends on
the voltage difference between VIN and
VOUT. The dual-pnp transistor has a VCEO
VIN
IN
+
C1
MAIN
C3
SWIN
SDIG
REF
C5
MAX1552
C8
COR1
C4
ON
SDIG
ENSD
OFF
1.8V
20 mA
COR2
ENC2
OFF
voltage, VCONT:
C6
ON
COR2
LED driver (Figure 3). The circuit comprises simply the PWM source, capacitor
C, and resistors RD and RW. For CMOS
circuits, you calculate the open-circuit
output voltage as VCONTDVDD, where
VCONT is the control circuits output voltage, D is the PWM duty cycle, and VDD is
the logic-supply voltage. The control circuits output impedance is the sum
3.3V
300 mA
of the resistor values
RD and RW: RCONT
RDRW. For the cir3.3V
200 mA
cuit of Figure 1, the
output
voltage,
1.5V
VOUT, is a function
200 mA
of the PWM average
SW
LCD
ON
ENLCD
RESET
OUTPUT
LOW-BATTERY
OUTPUT
LCD
20V
1 mA
D1
MAIN
R3
RSENSE
C9
L1
OFF
C7
LFB
LBO
GND
R1
ADJ
C2
DIGITAL
ADJUST
3
CTRL
R2
Figure 2
RD
Figure 1
This simple circuit provides positive-output voltage LCD drive.
VOUT
DLOW
GND
RFB
CCOMP
RW
0
ON/OFF
4
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
DHI
MAX749
FB
FROM
PROCESSOR
PWM OUTPUT
CS 8
V
LX
R4
RS
0.1 F
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
RW
FROM
PROCESSOR
PWM OUTPUT
0
RD
design
ideas
1 F
1 F
C1F C1N
C2P
C2N
VIN
2.7 TO 5.5V
OUT
1/1.5
REGULATING CHARGE PUMP
4.7 F
1 F
MAXIM
MAX1570
LED1
EN1
ON/OFF
AND
DIMMING
EN2
REFERENCE
AND
CONTROL
SET
LED2
LOW-DROPOUT
CURRENT
REGULATORS
LED3
LED4
LED5
RSET
GND
PGND
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
RW
FROM
PROCESSOR
PWM OUTPUT
0
RD
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design
ideas
C4
100 pF
R2
22k
C3
22 F
+
D4
BYV28-50
Q1
2N2907A
R3
1M
R4
22
D5
UF5406
Q2
IRFP450
D6
BYV28-50
OUTPUT
D7
1N4148
PWM
R5
22
Q3
IRFP450
D8
UF5406
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design
ideas
12V
base-emitter junction of Q1.
inverter with 150% overload caIn the turn-on of Q2, the folpacity. If you change the MOSlowing scenario occurs: When
FET, the value of C4 has to change
1k
the control input, PWM,
according to the total gate charge
2N2222A
Figure 2
goes low, Q3 quickly turns
plus the output capacitance of Q3,
off, thanks to D7. A displacement
which is much lower and, in fact,
2.2 nF 300
negligible. Q1 amplifies the cacurrent, C4dV/dt, flows
OUTPUT
through C4 to the base of Q1. Q1
pacitor current, so C4 is propor1N4148
charges the output capacitance
tional to QG2hFE1. Make C4s valINPUT
of Q3 and the gate capacitance of
ue no higher than necessary,
2.2k
2N2222A
Q2, and Q2 turns on. C3 supplies
because the base current in Q1
560
would be too high. To obtain all
the collector current. If the pethe speed advantages of the cirriod is long, Q1 keeps conducting and compensating the leakcuit, the PWM signal should be
age of Q3. If D6 were a Schottky This buffer enhances speed at the PWM input of Figure
able to quickly drive Q3. If necesdiode, which is leaky, you would 1s circuit.
sary, you can use a buffer circuit
have to reduce the value of R1. A
(Figure 2). You can drive the cirshort cross-conduction period exists be- current spikes. The inductor needs a cuit with a single CMOS gate. The circuit
tween the two MOSFETs, a phenomenon snubber comprising D1, R1, and C2. Note in Figure 1 is probably the simplest highthat is more apparent when Q3 turns off that the inductor value is conservative voltage inverter you can design. It has
and Q2 turns on. A small inductor, L1, in and can be smaller.
served in thousands of three-phase moseries with the main supply limits the
The values are for a 370W, three-phase tor drives from 0.37 to 0.75 kW.
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