Professional Documents
Culture Documents
Verilog Questions
Verilog Questions
else if (enable)
out <= out + 1;
50. Write a code for 8 bit parity checker?
Ans : assign parity_out = ^data_in; // data_in is 8 bits
51. Write a code for 8 bit shift-left register?
Ans : always @(posedge Clock)
begin
register <= register << 1;
register[0] <= Input;
end
assign output = register[7];
52. Write a code for 8 bit Unsigned adder?
Ans : assign {Carry_Out,SUM} = input_A + input_B + Carry_In;
53. Write a code for comparator?
Ans : assign out = (in_1 >= in_2)? 1'b1:1'b0;
54. When we use FSMs?
Ans : FSMs are widely used in applications that require prescribed sequential activity.
55. Difference between `define and parameter?
Ans : Define Parameter only one constant with the same name can exist in the whole scope
multiple modules can have same parameter name cannot be overridden can be overridden
used to specify macro used to specify constants
56. What value is inferred when multiple procedural assignments made to the same reg
variable in an always block?
Ans : When there are multiple nonblocking assignments made to the same reg variable in a
sequential always block, then the last assignment is picked up for logic synthesis.
57. What are snake paths?
Ans : A snake path, as the name suggests is a path that traverses through a number of
hierarchies, and may eventually return back to the same hierarchy from which it originated.
58. What is constant propagation? How can I use constant propagation to minimize
area?
Ans : Constant propagation is a very effective technique for area minimization, since it forces
the synthesis tools to optimize the logic in both forward and backward directions. Since the
area minimization is achieved using constants, this technique is called constant propagation.
59. What happens to the bits of a reg which are declared, but not assigned or used?
Ans : When any of the bits of a reg declaration is unused, the logic corresponding to those
bits gets optimized
60. Why we use `ifdef and generate for in verilog?
Ans : Both `ifdef and generate constructs can be used for the purpose of area minimization.
61. What is the difference between using `ifdef and generate?
Ans : `ifdef generate we can use it inside the module as well as outside the module. (g)we can
only use it inside the module works on the boolean presence or absence of `define of the
`ifdef variable use the value of a variable using genvar, can be used inside loops used only in
if-else and cannot perform any looping operation the genvar variable can be used inside for
loop or case statements
62. What is retime logic between registers?
Ans : Retiming is the process of relocating registers across logic gates, without affecting the
underlying combinatorial logic structure. This process is achieved by borrowing logic from
one time frame and lending it to the other, while maintaining the design behavior.
63. Why one-hot encoding is preferred for FSMs?
Ans : Since there is one explicit FF per stage of a one-hot encoded state machine, there is no
need of output state decoding. Hence, the only anticipated delay is the clock to q delay of the
FF. This makes the one-hot encoding mechanism preferable for high-speed operation.
64. What are the main factors that affect testability of a design?
Ans : Reset of a FF driven by the output of another FF Presence of tri-state buses in the
design Presence of derived clocks in the design Presence of gated clocks in the design
Presence of latches in the design
65. What are the various methods to reduce power during RTL coding?
Ans : Reduce switching of the data input to the Flip-Flops. Reduce the clock switching of the
Flip-Flops. Have area reduction techniques within the chip, since the number of gates/FlipFlops that toggle can be reduced.
66. What is the advantage of using hierarchical names to refer to Verilog objects?
Ans : It is easy to debug the internal signals of a design, especially if they are not a part of the
top level pinout.
67. What are the disadvantages of using hierarchical name to refer to Verilog objects?
Ans : During synthesis, these hierarchical names get ungrouped or dissolved or renamed,
depending upon the synthesis strategy and switches used, and hence, will cease to exist. In
that case, special switches need to be added to the synthesis compiler commands, in order to
maintain the hierarchical naming. If the Verilog code needs to be translated into VHDL, the
hierarchical names are not translatable.
68. What is the effect of specifying delays in assignments during synthesis?
Ans : Specifying any kind of delay before an assignment, or within an assignment, in a
blocking or non-blocking procedural assignment is ignored by synthesis tools. If the
functionality depends upon the presence of the delay, then a mismatch in functional
simulation will be seen between the model and the synthesized netlist. Ex: reg1 = #3 reg2; //
#3 will be ignored #6 reg3 <= reg4; // #6 will be ignored Since the above construct is
syntactically legal, the synthesis tools will issue a WARNING and not an ERROR.
69. What is the synthesized hardware for the verilog code below?
module generator_ex1(data, select, out);
input [0:7] data;
input [0:2] select;
out out;
assign out = data [select];
endmodule
Ans: 8:1 Mux
70. What is the synthesized hardware for the verilog code below?
module generate_ex2(out,in,select);
input En;
input [0:1] select;
output [0:3] out;
assign out = En? (1 << select) : 4b0;
endmodule
Ans: 2:4 Decoder
71. How to avoid unintentional latches in the design?
Ans : Completely specify all branches for every case and if statement. Completely specify all
outputs for every case and if statement. Use synopsys full-case if all desired cases have
specified.
72. What is a "full" case statement?
Ans : A "full" case statement is a case statement in which all possible case-expression binary
patterns can be matched to a case item or to a case default. If case statement does not include
a case default and if it is possible to find a binary case expression that does not match any of
the defined case items, the case statement is not full.
and logical shift right(>>) operators, shift the bits left/right by the number of bit positions
specified by the right operand, and the vacated bits are filled with zeros. The arithmetic right
shift operator (>>>) will fill the vacated bits with 0 if the left operand is unsigned, and the
most significant bit if the left operand is signed.
84. What is the difference between the logical (==) and the case (===) equality
operators?
Ans : The == are synthesizable while === operators are not synthesizable.
85. What is the difference between assign-deassign and force-release?
Ans : Force - release can be applicable to nets and variables, whereas assign - deassign is
applicable only to variables.
86. What is a critical path in a design?
Ans : There can be more than one critical path in a design. A critical path is the path through a
circuit that has the least slack. Need not necessarily the longest path in the design.
87. If there are only inputs and no output what it will be synthesized?
Ans : A module with only inputs and no outputs will synthesize into a module with no logic,
since there is nothing to be synthesized as an output.
88. what is the difference between casex and casez?
Ans : Casex treats x,z both as dont cares.
89. Write a Verilog code for ring counter?
module ring_counter(clk, initial_count, count);
input clk, initial_count;
output reg [7:0] count;
always @ (posedge clk)
begin
if (initial_count)
count = 8b00000000;
else
count = {count (6:0), count[7]};
endmodule
90. What is `timescale?
Ans : It is compiler directive which indicates the time unit to be used for delays specified in
the testbench.
91. What are different types of Verilog simulators?
Ans : Event-based Simulator:
Event base Simulation method sacrifices performance for rich functionality.
Every active signal is calculated for every device it propagates through during a clock cycle.
Full timing calculations for all devices and the full HDL standard.
Cycle Based Simulator:
Cycle based Simulation method eliminates unnecessary calculations to achieve huge
performance gains in verifying Boolean logic.
At the end of every clock cycle results are examined.
The digital logic is the only part of the design simulated. These simulators are mainly meant
for logic verification, no timing calculations. By limiting these calculations, cycle based
Simulators can provide huge increases in performance over Event-based simulators.
92. How we can use Verilog function to define the width of a multi-bit port, wire, or reg
type?
Ans : The width elements of ports, wire or reg declarations require a constant in both MSB
and LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the
value of these widths. For example, the following code is erroneous before Verilog 2001
version. reg [ port1(val1:vla2) : port2 (val3:val4)] reg1; Verilog-2001 allows the use of a
function call to evaluate the MSB or LSB of a width declaration.
93. What is alias?
Ans : System Verilog has introduced a keyword alias, which can be used only on nets to have
a two-way assignment.
module top_alias ();
wire rhs,lhs;
alias lhs=rhs;
In the above verilog code, if LHS changes it reflets to RHS and similarly if RHS changes it
reflects to LHS as well.
94. What is the difference between: c = con ? a : b; and if (con) c = a; else c = b;
Ans :The operator (?) gives answers even if the condition is "x", so for example if con = 1'bx,
a = 'b10, and b = 'b11, it will give c = 'b1x. Whereas if treats Xs or Zs as FALSE, so it will
return always c = b.
95. What is scheduling semantics for the simulation time in Verilog?
Ans : Verilog basically imply a four-level deep queue for the current simulation time:
Active Events (blocking statements)
Inactive Events (#0 delays, etc)
Non-Blocking Assign Updates (non-blocking statements)
Monitor Events ($display, $monitor, etc).
96. What is PLI?
Ans : Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface
Verilog programs with programs written in C language. It also provides mechanism to access
internal databases of the simulator from the C program.
97. List all the system tasks and their purpose?
Ans : $display Displays once every time when they are executed.
$strobe Displays the parameters at the very end of the current simulation time rather than
exactly where it is executed.
$monitor Displays every time when one of its parameter changes.
$reset Resets the simulation back to zero.
$stop Halts the simulator and puts in the interactive mode where user can enter commands
$finish Exits simulator back to operating system.
$time, $stime, $realtime Currenmt simulation time as a 64-bit integer, 32-bit integer and
real number respectively.
$scope (hierarchy_name) sets the current scope to hierarchy scope to hierarchy name.
$showscopes Lists all modules,tasks & block naems in current scope.
$fopen Opens an ouput file and gives the open file a handle for use by the other commands.
fclose Closes the file and lets the other programs access it.
$fdisply, $fwrite Writes formated data to a file when ever they executed. Both are same
except $fdisplay inserts a new line after every execution and $fwrite does not inserts.
$fstrobe Writes a file when executed, but waits until all other operations in the time step are
complete before writing.
initilal
# 1 a= 1; b=0;
#fstrobe (file, a,b );
b=1;
Will writes 11 for a and b.
$fmonitor Writes to a file when ever any argument changes
$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall The dump files are capable of
dumping all the variables in a simulation.
$dumpvar dumps all the variables in the design.
$dumpvar(1,top) Dumps all variables in the top and below but not sub modules.
$dumpvar(2,top) Dumps all variables in the top and one level below.
$dumpvar(n,top) Dumps all variables in the top and n-1 level below.
$dumpvar(0,top) Dumps all variables in the top and all levels below.
$dumpon Initiates the dump.
$dumpoff - Stops dumping.
$random Generates radom integer every time when it is called.
98. What is a netlist?
Ans : Gate level representation of RTL.
99. How memory is declared in Verilog?
Ans : Memories are declared as two-dimensional arrays of registers.
syntax: reg [msb:lsb] identifier [first_addr:last_addr] ;
Where msb:lsb determine the width (word size) of the memory first_addr:last_addr determine
the depth (address range) of the memory
100.What are the guidelines for using functions in Verilog?
Ans : A function cannot advance simulation-time, using constructs like #, @. etc.
A function should not have nonblocking assignments.
A function without a range defaults to a one bit reg for the return value.
It is illegal to declare another object with the same name as the function in the scope where
the function is declared.